Communication apparatus and communication method

This application claims priority to Taiwan Application Serial Number 106129204, filed Aug. 28, 2017, which is herein incorporated by reference.

The present disclosure relates to a communication apparatus and a method for receiving signals. More particularly, the present disclosure relates to an apparatus and a method for reducing interference in a communication system.

In digital communication systems, intersymbol interference (IR) is a common issue in the signal transmission progress. The ISI is caused from the interference between the successive signal signs.

In high speed transmission interfaces, if the characteristic of the transmission channel (e.g., the length, the impedance, and/or the inductance of the transmission line) is known, the ISI may be compensated. However, in practical applications, the characteristic of the transmission channel cannot be estimated or known, the compensation cannot be effectively performed. As a result, the communication between the transmitter and the receiver may not be correct, and the signal quality may be reduced.

In some aspects, the disclosure provides a communication apparatus. The communication apparatus includes an input terminal, an output terminal, and an interference reduction circuit. The input terminal is configured to receive a time-varying data signal. The interference reduction circuit is coupled between the input terminal and the output terminal. The interference reduction circuit is configured to acquire first partial data, at a first time, of the data signal and to generate a first level-shifted result and a second level-shifted result according to the first partial data. The interference reduction circuit is further configured to acquire second partial data, at a second time, of the data signal, and to select one of the first level-shifted result and the second level-shifted result as a selected result according to the second partial data, and to transmit the selected result to the output terminal.

In some aspects, the disclosure provides a communication method that includes following operations: receiving a time-varying data signal; acquiring first partial data, at a first time, of the data signal, and generating a first level-shifted result and a second level-shifted result according to the first partial data; acquiring second partial data, at a second time, of the data signal; and selecting one of the first level-shifted result and the second level-shifted result as a selected result, and transmitting the selected result to an output terminal.

These and other features, aspects, and advantages of the present disclosure will become better understood with reference to the following description and appended claims.

It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.

The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:

FIG. 1 is a schematic diagram of a communication system, according to some embodiments of the present disclosure.

FIG. 2 is a functional block diagram of the communication apparatus, according to some embodiments of the present disclosure.

FIG. 3A is a circuit diagram of the communication apparatus in FIG. 2 , according to some embodiments of the present disclosure.

FIG. 3B is a circuit diagram of the communication apparatus in FIG. 2 , according to some embodiments of the present disclosure.

FIG. 4 is a flow chart of a communication method, according to some embodiments of the present disclosure.

FIG. 5 is a schematic diagram illustrating the data signal processed by the interference reduction circuit, according to some embodiments of the present disclosure.

FIG. 6 is a functional block diagram of a communication apparatus, according to some other embodiments of the present disclosure.

FIG. 7 is a flow chart of a method, according to some embodiments of the present disclosure.

FIG. 8 is a schematic diagram illustration signals processed by the method in FIG. 7 , according to some embodiments of the present disclosure.

FIG. 9 is a functional block diagram of a communication apparatus, according to some embodiments of the present disclosure.

FIG. 1 is a schematic diagram of a communication system 200 , according to some embodiments of the present disclosure. The communication system 200 includes a signal source 210 and a communication apparatus 100 . The communication apparatus 100 receives a data signal DIN transmitted from the signal source 210 . In some embodiments, the data signal DIN is an analog signal that is time-varying and serialized.

The communication apparatus 100 includes an input terminal 110 , an interference reduction circuit 120 , and an output terminal 130 . The interference reduction circuit 120 is coupled between the input terminal 110 and the output terminal 130 . The input terminal 110 receives the time-varying data signal DIN. In some embodiments, the input terminal 110 includes a linear equalizer (not shown). The linear equalizer performs a preliminary processing on the data signal DIN, in order to adjust signal strength of the data signal DIN at each band. In some embodiments, the output terminal 130 includes a deserializer (not shown). The deserializer deserializes the data signal DIN received by the communication apparatus 100 , in order to output the deserialized signals to other circuits.

Reference is also made to FIG. 2 . FIG. 2 is a functional block diagram of the communication apparatus 100 , according to some embodiments of the present disclosure. The interference reduction circuit 120 includes shifter circuits 121 and 122 , a processing circuit 125 , an adder 126 , and a multiplexer 127 . In some embodiments, certain interferences (e.g., intersymbol interference) may present in data levels, at different timings, of the data signal DIN during a transmission progress from the signal source 210 to the communication apparatus 100 . In some embodiments, the interference reduction circuit 120 is configured to reduce the interference of the data signal DIN at different timings.

A partial data, at a first time, of the data signal DIN is transmitted to the shifter circuits 121 and 122 via the adder 126 . The shifter circuit 121 sums up the partial data at the first time and a first shift to generate a level-shifted result RA 1 . The shifter circuit 122 sums up the partial data at the first time and a second shift to generate a level-shifted result RB 1 .

After the first time, the processing circuit 125 acquires a partial data, at a second time, of the data signal DIN. In some embodiments, a sampling unit time interval (which may be 0.5 ms, 1 ms, or be set according to practical requirements) is present between the first time and the second time, but the present disclosure is not limited thereto. The partial data, at the second time, of the data signal DIN may be different from the partial data at the first time. The partial data at the first time and the partial data at the second time may have different voltage levels, and/or may carry the same information or different information. In some embodiments, a delay of the sampling unit time interval is caused during the shifter circuits 121 and 122 generate the level-shifted results RA 1 and RB 1 according the partial data at the first time, respectively, but the present disclosure is not limited thereto.

In some embodiments, a difference between the first time and the second time is one sampling unit time interval, and the level-shifted results RA 1 and RB 1 are delayed by one sampling unit time interval when compared with the partial data at the first time. The processing circuit 125 outputs a selection signal S 0 according to the partial data at the second time. The level-shifted results RA 1 and RB 1 and the selection signal S 0 are transmitted to the multiplexer 127 at the same time. The multiplexer 127 selects one of the level-shifted results RA 1 and RB 1 as a selected result according to the selection signal S 0 , and transmits the selected result to the output terminal 130 . In other words, the partial data at the first time is adjusted to be the level shifted results RA 1 and RB 1 . The level-shifted result RA 1 or RB 1 is then selected according to the partial data at the second time. As a result, the input voltage level of the previous data signal DIN (e.g., data signal DIN at the first time) can be adjusted according to the subsequent data signal DIN (e.g., data signal DIN at the second time). With this adjustment, the interference from subsequent signs to the previous signs can be compensated, and precursor ISI is able to be reduced.

FIG. 3A is a circuit diagram of the communication apparatus 100 in FIG. 2 , according to some embodiments of the present disclosure. As shown in FIG. 3A , the shifter circuit 121 includes a level shifter 310 a , a comparator 320 a , and a delay circuit 330 a . The level shifter 310 a is configured to shift the partial data of the data signal DIN by a first predetermined voltage difference. For example, the partial data at the first time is shifted up by a voltage difference Vth and outputted as an analog level-shifted signal aRA 1 . Accordingly, the first predetermined voltage difference is +Vth, and the voltage level of the analog level-shifted signal aRA 01 is equal to DIN+Vth. The comparator 320 a compares the analog level-shifted signal aRA 1 with a predetermined value REF 0 , in order to output a digitized level-shifted signal. The digitized level-shifted signal is outputted as the level-shifted result RA 1 to the multiplexer 127 via the delay circuit 330 a . In some embodiments, the predetermined value REF 0 is a value for distinguishing between a high level (i.e., logic value of 1) and a low level (i.e., logic value of 0) of the digitized signal. If the voltage level of the analog level-shifted signal aRA 1 is higher than the predetermined value REF 0 , the level-shifted result RA 1 is the high level (i.e., the logic value of 1). If the voltage level of the analog level-shifted signal aRA 1 is lower than the predetermined value REF 0 , the level-shifted result RA 1 is the low level (i.e., the logic value of 0).

The shifter circuit 122 includes a level shifter 310 b , a comparator 320 b , and a delay circuit 330 b . The level shifter 310 b is configured to shift partial data of the data signal DIN by a second predetermined voltage difference. For example, the partial data at the first time is shifted down by the voltage difference Vth and outputted as an analog level-shifted signal aRB 1 . Accordingly, the second predetermined voltage difference is −Vth, and the voltage level of the analog level-shifted signal aRB 1 is equal to DIN−Vth. The comparator 320 b compares the analog level-shifted signal aRB 1 with the predetermined value REF 0 , in order to output a digitized level-shifted signal. The digitized level-shifted signal is outputted as the level-shifted result RB 1 via the delay circuit 330 b to the multiplexer 127 .

In some embodiments, a delay time introduced from the delay circuits 330 a and 330 b may be one sampling unit time interval or an integral multiple of the sampling unit time interval.

As described above, the level-shifted results RA 1 and RB 1 are different level-shifted results which are generated by increasing and decreasing the voltage from an initial level of the partial data at the first time, respectively. Therefore, if the interference reduction circuit 120 determines that the partial data at the second time may increase the partial data at the first time (i.e., a raised ISI is introduced to the partial data at the first time), the level-shifted result RB 1 is selected. Otherwise, if the interference reduction circuit 120 determines that the partial data at the second time may reduce the partial data at the first time (i.e., a lowered ISI is introduced to the partial data at the first time), the level-shifted result RA 1 is selected. With this selection, the impacts, introduced from the subsequent partial data, on the previous partial data are able to be removed or reduced.

The processing circuit 125 is coupled to the input terminal 110 . In the embodiments of FIG. 3A , the processing circuit 125 includes a comparator 340 and a delay circuit 350 . The multiplexer 127 is coupled to the processing circuit 125 and the shifter circuits 121 and 122 , and is configured to select one of the level-shifted results RA 1 and RB 1 , and to output the selected result to the output terminal 130 .

In some embodiments, the comparator 340 is configured to compare the partial data with a threshold value, in order to generate the selection S 0 . The threshold value is set according to a characteristic of the data signal DIN. For example, if the characteristic of the data signal DIN corresponds to a binary signal and the binary signal is indicated as a transition between a high level (e.g., 1V) and a low level (e.g., −1V or 0V), the threshold value may be set as an average level between the high level and the low level (e.g., 0V or 0.5V). In some embodiments, if the data signal DIN is lower than the threshold value, the multiplexer 127 outputs the level-shifted result RA 1 in response to the selection signal S 0 . On the other hand, if the data signal DIN is higher than the threshold value, the multiplexer 127 outputs the level-shifted result RB 1 in response to the selection signal S 0 . In some embodiments, the threshold value and the selection between the level-shifted results RA 1 /RB 1 may be determined according to a characteristic of the ISI of the data signal DIN.

In some embodiments, the delay time introduced from the delay circuit 350 is less than the delay time introduced from the delay circuit 330 a by one sampling unit time interval. If the delay time introduced from the delay circuit 330 a or from the delay circuit 330 b are N sampling unit time intervals, the delay time introduced from the delay circuit 350 is (N−1) sampling unit time intervals. In addition, if N equals to 1, the delay time introduced from the delay circuit 350 is set to be zero, or no delay circuit 350 is employed in the processing circuit 125 . The partial data at the second time, of the data signal DIN is outputted as the digitized partial data by the comparator 340 . This partial data at the second time is digitized as the selection signal S 0 which is then inputted to the multiplexer 127 . It is noted that, in FIG. 3A , the selection S 0 is labeled at the output of the delay circuit 350 is for ease of illustrating operations of the multiplexer 127 (i.e., timing synchronization).

A decision feedback equalizer 128 is coupled to the processing circuit 125 and the multiplexer 127 , and is configured to generate a feedback signal FB according to the partial data (e.g., the partial data at the second time) and the selected result. In some embodiments, the decision feedback equalizer 128 is configured to generate the feedback signal FB according to the selection signal S 0 corresponding to the partial data and the selected result. The adder 126 is coupled to the input terminal 110 , the decision feedback equalizer 128 , the shifter circuits 121 and 122 , and the processing circuit 125 . The adder 126 receives the feedback signal FB to adjust subsequent partial data of the data signal DIN.

The decision feedback equalizer 128 is configured to gather information of the previous level (e.g., the level at the second time) of the data signal DIN, and to feedback the same to the adder 126 correspondingly, in order to adjust the subsequent input voltage level of the data signal DIN. With this adjustment, the interference from the previous signs to subsequent signs can be compensated, and postcursor ISI is able to be reduced.

Reference is made to FIGS. 2, 3A, 4, and 5 . FIG. 4 is a flow chart of a communication method 400 , according to some embodiments of the present disclosure. FIG. 5 is a schematic diagram illustrating the data signal DIN processed by the interference reduction circuit 120 , according to some embodiments of the present disclosure. The communication method 400 may be implemented with the following operations. In operation S 402 , the time-varying data signal DIN is received. In operation S 404 , partial data VT 1 , at a first time T 1 , of the data signal DIN is acquired, the shifter circuit 121 generates the level-shifted result RA 1 according to the partial data VT 1 , and the shifter circuit 122 generates the level-shifted result RB 1 according to the partial data VT 1 .

As shown in FIG. 5 , at the time T 1 , the partial data VT 1 of the data signal DIN is transmitted to the shifter circuits 121 and 122 via the adder 126 . The shifter circuit 121 sums up the partial data VT 1 and a first shift (which may be +Vth in some embodiments), in order to generate the analog level-shifted signal aRA 1 , and the shifter circuit 122 sums up the partial VT 1 and a second shift (which may be −Vth in some embodiments), in order to generate the analog level-shifted signal aRB 1 . The analog level-shifted signals aRA 1 and aRB 1 are then processed by the comparators 320 a and 320 b in FIG. 3A and the delay circuits 330 a and 330 b , respectively, in order to be the digitalized level-shifted results RA 1 and RB 1 .

In operation S 406 , after the first time T 1 , partial data VT 2 , at a second time T 2 , of the data signal DIN is acquired.

In operation S 408 , one of the level-shifted results RA 1 and RB 1 is selected, and the selected result is transmitted to the output terminal 130 . Under this condition, the output terminal 130 considers the one of the level-shifted results RA 1 and RB 1 as the data, at the first time T 1 , of the data signal DIN.

In operation S 410 , the decision feedback equalizer 128 generates the feedback signal FB according to the partial data VT 2 and the selected result of the multiplexer 127 , and transmits the same to the adder 126 to adjust subsequent data (e.g., partial data VT 3 at a third time T 3 ). In some embodiments, the decision feedback equalizer 128 generates the feedback signal FB according to the selection signal S 0 (which corresponds to the partial data VT 2 ) and the selected result of the multiplexer 127 .

In other words, the decision feedback equalizer 128 may generate the feedback signal FB based on the previously-received data, which may be, for example, the received selection signal S 0 (which corresponds to the second time T 2 ) and the selected result (which corresponds to the first time T 1 ), in order to adjust subsequent data (e.g., the partial data VT 3 at the third time T 3 ). Accordingly, the decision feedback equalizer 128 is able to be employed to reduce the postcursor ISI.

The first shift and the second shift may be voltage having the same value but with different signs. For example, the first shift may be a positive voltage difference +Vth, and the second shift may be a negative voltage difference −Vth. The arrangements of the shifts are given for illustrative purposes, and the present disclosure is not limited thereto. By selecting one of the level-shifted results RA 1 and RB 1 as correct data at the first time according to subsequent signals, impacts from channel noises can be reduced, and the impacts of the ISI on the signal quality can be compensated. In some embodiments, an absolute value of the voltage difference Vth, as used in the first and the second shift, can be obtained by using a least mean square algorithm, but the present disclosure is not limited thereto.

It is noted that, the interference reduction circuit 120 performs the compensation over time. In other words, the interference reduction circuit 120 may repeatedly perform operations S 404 to S 410 in FIG. 4 . As far as the second time T 2 is concerned, the partial data VT 2 , at the second time T 2 , of the data signal DIN is acquired and transmitted to the shifter circuits 121 and 122 via the adder 126 . The shifter circuit 121 is configured to sum up the partial data VT 2 and the first shift (which may be +Vth in some embodiments), in order to generate the level-shifted result RA 2 (which corresponds to aRA 2 ), and the shifter circuit 122 is configured to sum up the partial data VT 2 at the second time and the second shift (which may be −Vth in some embodiments), in order to generate the level-shifted result RB 2 (which corresponds to aRB 2 ).

In operation S 406 , after the second time T 2 , partial data VT 3 , at a third time T 3 , of the data signal DIN is acquired. In operation S 408 , one of the level-shifted results RA 2 and RB 2 is selected according to the partial data VT 3 , and the selected result is transmitted to the output terminal 130 . The output terminal 130 then considers one of the level-shifted results RA 2 and RB 2 as the data, at the second time T 2 , of the data signal DIN.

In operation S 410 , the decision feedback equalizer 128 receives the partial data VT 3 and the selected result (e.g., the level-shifted result RA 2 or RB 2 ) of the multiplexer 127 , and generates the feedback signal FB according to the partial data VT 3 and the selected result. The adder 126 receives the feedback signal FB. By transmitting the data back to the adder 126 , subsequent data (e.g., a fourth partial data (not shown) or partial data sampled at subsequent times) is able to be adjusted.

Reference is made to FIG. 3B . FIG. 3B is a circuit diagram of the communication apparatus 100 in FIG. 2 , according to some embodiments of the present disclosure. The operations of the communication method 400 may be performed by the circuit shown in FIG. 3B , in order to achieve the similar results. Compared with FIG. 3A , in the shifter circuits 121 and 122 in FIG. 3B , the level shifters 310 a and 310 b sum up the predetermined value REF 0 with the first shift and sum up the predetermined value REF 0 with the second shift, respectively, in order to generate reference signals REF 1 and REF 2 . The reference signals REF 1 and REF 2 are then compared with the partial data VT 1 , by the comparators 320 a and 320 b respectively, to generate the digitized level-shifted signals. These digitized level-shifted signals are then processed by the delay circuits 330 a and 330 b to generate the level-shifted results RA 1 and RB 1 to the multiplexer 127 , and the output of the multiplexer 127 is sent to the decision feedback equalizer 128 to adjust the subsequent partial data. In the embodiments of FIG. 3B , each of the first shift and the second shift is summed up with the predetermined value, in order to generate different reference signals REF 1 (which equals to REF+Vth) and REF 2 (which equals to REF 0 −Vth). By comparing the same partial data VT 1 with the different reference signals REF 1 and REF 2 , the digitized results RA 1 and RB 1 can be obtained.

Reference is made to FIGS. 6-8 . FIG. 6 is a functional block diagram of a communication apparatus, according to some other embodiments of the present disclosure. Except including the shifter circuits 121 and 122 shown in FIGS. 2, 3A , or 3 B, the interference reduction circuit 120 further includes shifter circuits 123 and 124 . FIG. 7 is a flow chart of a method, according to some embodiments of the present disclosure. FIG. 8 is a schematic diagram illustration signals processed by the method in FIG. 7 , according to some embodiments of the present disclosure.

In operation S 702 , the time-varying data signal DIN is received.

In operation S 704 , the partial data VT 1 , at the first time T 1 , of the data signal DIN is acquired, and the shifter circuits 121 - 124 generate level-shifted results RA 1 , RB 1 , RC 1 , and RD 1 , respectively, according to the partial data VT 1 . In greater details, the shifter circuits 121 - 124 provide different shifts to the partial data VT 1 . Level shifters 310 a - 310 d of the shifter circuits 121 - 124 generates analog level-shifted signals aRA 1 , aRB 1 , aRC 1 , and aRD 1 , and comparators 320 a - 320 d and delay circuits 330 a - 330 d generate level-shifted results RA 1 , RB 1 , RBC, and RD 1 . Similar to operations shown in FIG. 4 , in some embodiments, in operation S 704 , analog shifted signals aRA 1 , aRB 1 , aRC 1 , and aRD 1 , which are generated by summing different shifts, are compared with the reference value to obtain level-shifted results RA 1 , RB 1 , RC 1 , and RD 1 . In some other embodiments, the predetermined value is summed up with different shifted voltages, and the partial data VT 1 is then compared with the shifted predetermined values to generate the level-shifted results RA 1 , RB 1 , RC 1 , and RD 1 .

In some embodiments of FIG. 8 , the analog level-shifted signal aRA 1 is the partial data VT 1 plus a predetermined shifted voltage, the analog level-shifted signal aRC 1 is the partial data VT 1 plus two times of the predetermined shifted voltage, the analog level-shifted signal aRB 1 is the partial data VT 1 minus the predetermined shifted voltage, and the analog level-shifted signal aRD 1 is the partial data VT 1 minus two times of the predetermined shifted voltage, but the present disclosure is not limited thereto.

In some embodiments, the analog level-shifted signal aRA 1 and the analog level-shifted signal aRB 1 may have the same shifted value (or voltage) but with different signs. In some embodiments, the analog level-shifted signal aRC 1 and the analog level-shifted signal aRD 1 may have the same shifted value (or voltage) but with different signs. In some embodiments, the shifted values of analog level-shifted signals aRA 1 and aRB 1 and those of the analog level-shifted signals aRC 1 and aRD 1 may not be proportional. The above examples of the analog level-shifted signals aRA 1 -aRD 1 are given for illustrative purposes, and various configurations of analog level-shifted signals aRA 1 -aRD 1 , which are able to be applied to the communication apparatus 100 , are within the contemplated scope of the present disclosure.

In some embodiments, the shift and direction of the analog level-shifted signals aRA 1 , aRB 1 , aRC 1 , and aRD 1 may be determined based on the characteristic of the ISI of the data signal DIN. For example, if the characteristic of the precursor ISI of the data signal DIN tends to lower the previous data signal, the shifted direction of the analog level-shifted signals aRA 1 , aRB 1 , aRC 1 , and aRD 1 is set to be an increment (i.e., plus different shifted voltages), or the shifted direction of the analog level-shifted signals aRA 1 , aRB 1 , and aRC 1 is set to be the increment while the shifted direction of the analog level-shifted signal aRD 1 is set to be a decrement. Alternatively, if the precursor ISI of the data signal DIN tends to increase the previous data signal, the shifted direction of the analog level-shifted signals aRA 1 , aRB 1 , aRC 1 , and aRD 1 is set to be a decrement (i.e., minus different shifted voltages), or the shifted direction of the analog level-shifted signals aRA 1 , aRB 1 , and aRC 1 is set to be the decrement while the shifted direction of the analog level-shifted signal aRD 1 is set to be an increment.

In operation S 706 , the processing circuit 125 further acquires the partial data VT 2 , at the second time T 2 , and the partial data VT 3 , at the third time T 3 , of the data signal DIN, in order to generate the selection signals S 0 and S 1 to the multiplexer 127 for decision. In some embodiments, the processing circuit 125 may compare the partial data VT 2 with a first threshold value to generate the selection signal S 0 , and compare the partial data VT 2 with a second threshold value to generate the selection signal S 1 , in which the first and second threshold values may be set according to the characteristic of the data signal DIN and may be the same value or different values.

In operation S 708 , the multiplexer 127 further selects one of the level-shifted results RA 1 , RB 1 , RC 1 , and RD 1 , which correspond to the partial data VT 1 , according to the selection signals S 0 and S 1 , and transmits the selected result to the output terminal 130 .

In some embodiments, the shifter circuits 123 and 124 may be implemented with the same architecture of the shifter circuit 121 . The remaining operations in FIG. 6 are similar to FIG. 2 , and thus the repetitious descriptions are not given herein.

In operation S 710 , the decision feedback equalizer 128 generates the feedback signal FB according to the selected result, the partial data VT 2 , and the partial data VT 3 , in order to adjust subsequent data. In some embodiments, the decision feedback equalizer 128 may receive the selection signal S 0 (which corresponds to the partial data VT 2 ), the selection signal S 1 (which corresponds to the partial data VT 3 ), and the selected result, in order to generate the feedback signal FB.

FIG. 9 is a functional block diagram of a communication apparatus 100 , according to some embodiments of the present disclosure. FIG. 9 is a general case having 2 N shifter circuits, and this case is able to be derived from FIG. 2 and FIG. 6 of the present case, in which N is a positive integer. The operations and the arrangements shown in FIG. 9 are similar to FIG. 2 and FIG. 6 , and thus the repetitious descriptions are not further given herein.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.