Gate driver and display device including the same

This application claims the benefit of Republic of Korea Patent Application No. 10-2017-0174443 filed on Dec. 18, 2017, which is incorporated herein by reference for all purposes in its entirety.

The present disclosure relates to a gate driver and a display device including the same.

Discussion of the Related Art

An electroluminescent display is classified into an inorganic electroluminescent display and an organic electroluminescent display depending on a material of an emission layer. An active matrix organic light emitting diode (OLED) display includes a plurality of OLEDs capable of emitting light by themselves and has many advantages of fast response time, high emission efficiency, high luminance, wide viewing angle, and the like.

An OLED display includes pixels arranged in a matrix and adjusts a luminance of the pixels in accordance with gray levels of image data. Each pixel includes an OLED, a driving thin film transistor (TFT) controlling a driving current flowing in the OLED depending on a gate-to-source voltage of the driving TFT, and switching TFTs programming the gate-to-source voltage of the driving TFT in response to a scan signal. The pixel adjusts a display gray level (or a luminance) with an amount of light emitted by the OLED proportional to the driving current.

The OLED display includes a gate driver generating the scan signals. The gate driver sequentially supplies the scan signals to gate lines. The scan signal is supplied to the switching TFT of each pixel through the gate lines and controls a switching operation of the switching TFT.

A gate driver may be implemented as a gate shift register including a plurality of stages. Each stage outputs a scan signal at a gate-off voltage or a gate-on voltage depending on a voltage of a node Q and a voltage of a node QB. The scan signal of the gate-off voltage is a signal capable of turning off switching TFTs, and the scan signal of the gate-on voltage is a signal capable of turning on the switching TFTs. The scan signal of the gate-on voltage is output to each stage while the node Q is activated, and the scan signal of the gate-off voltage is output to each stage while the node QB is activated.

When the scan signal of the gate-on voltage is output, an initialization operation of pixels can be performed. Because a gate-on voltage period of a scan signal is short in a high resolution display device, the high resolution display device secures an initialization period through an overlap drive. The overlap drive allows gate-on voltage periods of adjacent scan signals to partially overlap one another using clock signals which overlap one another by a predetermined phase.

In order to secure operation stability of the gate driver, the voltage of the node Q and the voltage of the node QB in each stage have to be controlled to be opposite to each other. In other words, the node QB has to be deactivated to the gate-off voltage while the node Q is activated to the gate-on voltage, and the node QB has to be activated to the gate-on voltage while the node Q is deactivated to the gate-off voltage. However, a current path interval, in which the voltage of the node Q and the voltage of the node QB in each stage are not controlled to be opposite to each other, may occur in the overlap drive. In the current path interval, an input terminal of the gate-off voltage and an input terminal of the gate-on voltage are short-circuited to each other, and both the node Q and the node QB are activated to the gate-on voltage. Therefore, a voltage of the scan signal may unstable, and power consumption may increase.

Accordingly, an object of the present disclosure is to address the above-described and other problems and provide a gate driver capable of securing operation stability and operation reliability and reducing power consumption by removing a current path interval, in which a voltage of a node Q and a voltage of a node QB are unstable, and a display device including the gate driver.

In one aspect, there is provided a gate driver comprising a plurality of stages, wherein each stage includes a transistor T 6 configured to output a first clock signal as a scan signal in accordance with a node Q, a transistor T 7 configured to output a gate-off voltage as the scan signal in accordance with a node QB which is activated as opposed to the node Q, a Q controller configured to activate the node Q to a gate-on voltage in response to a start signal or a carry signal, of which a phase is earlier than a phase of the first clock signal, and a fourth clock signal, of which a phase is earlier than the phase of the first clock signal, and a QB controller configured to activate the node QB to the gate-on voltage in response to a second clock signal, of which a phase is later than the phase of the first clock signal, and a third clock signal, of which a phase is later than the phase of the second clock signal.

The accompanying drawings, that may be included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain various principles of the disclosure.

FIG. 1 illustrates a display device according to an embodiment of the disclosure.

FIG. 2 illustrates a pixel array included in a display panel shown in FIG. 1 according to an embodiment of the disclosure.

FIG. 3 schematically illustrates a pixel circuit included in a pixel array shown in FIG. 2 according to an embodiment of the disclosure.

FIG. 4 illustrates a gate signal applied to a pixel circuit shown in FIG. 3 according to an embodiment of the disclosure.

FIG. 5 illustrates first and second scan drivers and an emission driver included in a gate driver shown in FIG. 1 according to an embodiment of the disclosure.

FIG. 6 illustrates a gate shift register included in a first scan driver or a second scan driver shown in FIG. 5 according to an embodiment of the disclosure.

FIGS. 7 to 10 illustrate various connection configurations of a stage shown in FIG. 6 according to an embodiment of the disclosure.

FIG. 11 illustrates an operation waveform of a stage in accordance with an overlap drive according to an embodiment of the disclosure.

FIG. 12 illustrates an operation waveform of a stage in accordance with a non-overlap drive according to an embodiment of the disclosure.

FIGS. 13A to 13E illustrate operation states of a stage respectively corresponding to periods {circle around ( 1 )} to {circle around ( 5 )} shown in FIG. 11 according to an embodiment of the disclosure.

Reference will now be made in detail to embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. However, the present disclosure is not limited to embodiments disclosed below, and may be implemented in various forms. These embodiments are provided so that the present disclosure will be described more completely, and will fully convey the scope of the present disclosure to those skilled in the art to which the present disclosure pertains. Particular features of the present disclosure can be defined by the scope of the claims.

Shapes, sizes, ratios, angles, number, and the like illustrated in the drawings for describing embodiments of the disclosure are merely exemplary, and the present disclosure is not limited thereto unless specified as such. Like reference numerals designate like elements throughout. In the following description, when a detailed description of certain functions or configurations related to this document that may unnecessarily cloud the gist of the disclosure have been omitted.

In the present disclosure, when the terms “include”, “have”, “comprised of”, etc. are used, other components may be added unless “˜ only” is used. A singular expression can include a plural expression as long as it does not have an apparently different meaning in context.

In the explanation of components, even if there is no separate description, it is interpreted as including margins of error or an error range.

In the description of positional relationships, when a structure is described as being positioned “on or above”, “under or below”, “next to” another structure, this description should be construed as including a case in which the structures directly contact each other as well as a case in which a third structure is disposed therebetween.

The terms “first”, “second”, etc. may be used to describe various components, but the components are not limited by such terms. The terms are used only for the purpose of distinguishing one component from other components. For example, a first component may be designated as a second component, and vice versa, without departing from the scope of the present disclosure.

In embodiments disclosed herein, each of a pixel circuit and a gate driver on a substrate of a display panel may be implemented as transistors of p-type metal oxide semiconductor field effect transistor (MOSFET) structure. However, embodiments are not limited thereto. The transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode for supplying carriers to the transistor. The carriers inside the transistor begin to flow from the source. The drain is an electrode from which the carriers exit the transistor. Namely, carriers in the MOSFET flow from the source to the drain. In case of a p-type thin film transistor (TFT) (or p-type MOSFET (PMOS)), because carriers are holes, a source voltage is greater than a drain voltage so that holes can flow from a source to a drain. In the p-type TFT, because holes flow from the source to the drain, a current flows from the source to the drain. It should be noted that the source and the drain of the MOSFET are not fixed. For example, the source and the drain of the MOSFET may be changed depending on an applied voltage. Thus, in embodiments disclosed herein, one of the source and the drain is referred to as a first electrode, and the other is referred to as a second electrode.

The following embodiments are described using an organic light emitting diode (OLED) display including an organic light emitting material as an example of a display device. However, it should be noted that the technical idea of the present disclosure is not limited to the OLED display. For example, the present disclosure may be applied to an inorganic electroluminescent display including an inorganic electroluminescent material.

FIG. 1 illustrates a display device according to an embodiment of the disclosure. FIG. 2 illustrates a pixel array included in a display panel shown in FIG. 1 according to an embodiment of the disclosure. FIG. 3 schematically illustrates a pixel circuit included in a pixel array shown in FIG. 2 according to an embodiment of the disclosure. FIG. 4 illustrates a gate signal applied to a pixel circuit shown in FIG. 3 according to an embodiment of the disclosure. FIG. 5 illustrates first and second scan drivers and an emission driver included in a gate driver shown in FIG. 1 according to an embodiment of the disclosure.

Referring to FIG. 1 , a display device according to an embodiment of the disclosure includes a display panel 100 , a timing controller 110 , a data driver 120 , a gate driver 130 , and a level shifter 150 , and the like.

A plurality of data lines 14 and a plurality of gate lines 15 a , 15 b and 15 c are disposed to intersect each other on the display panel 100 . Pixels PXL are respectively arranged at intersections of the data lines 14 and the gate lines 15 a , 15 b and 15 c in a matrix to form a pixel array.

As shown in FIG. 2 , the pixel array of the display panel 100 includes a plurality of horizontal pixel lines L 1 to L 4 . The pixels PXL, which are horizontally adjacent to one another and are commonly connected to the gate lines 15 a , 15 b and 15 c , are disposed on each of the horizontal pixel lines L 1 to L 4 . In embodiments disclosed herein, each of the horizontal pixel lines L 1 to L 4 is not a physical signal line but a set of pixels implemented by horizontally adjacent pixels PXL of one line. The pixel array may include first power lines 17 supplying a high potential power voltage EVDD to the pixels PXL and second power lines 16 supplying a reference voltage Vref to the pixels PXL. Further, the pixels PXL may be connected to an input terminal of a low potential power voltage EVSS.

As shown in FIG. 2 , each gate line may include a first gate line 15 a supplied with a first scan signal SCAN 1 , a second gate line 15 b supplied with a second scan signal SCAN 2 , and a third gate line 15 c supplied with an emission signal EM. The third gate line 15 c may be omitted depending on a structure of the pixels PXL.

Each pixel PXL may be one of a red pixel, a green pixel, a blue pixel, and a white pixel. A red pixel, a green pixel, a blue pixel, and a white pixel may constitute a unit pixel and can implement various colors. A color implemented by the unit pixel may be determined depending on an emission rate of the red pixel, the green pixel, the blue pixel, and the white pixel. The white pixel may be omitted. In this instance, the red pixel, the green pixel, and the blue pixel may constitute a unit pixel. Each pixel PXL may be connected to the data line 14 , the first gate line 15 a , the second gate line 15 b , the third gate line 15 c , the first power line 17 , the second power line 16 , and the like.

As shown in FIG. 3 , each pixel PXL may include an organic light emitting diode (OLED), a driving thin film transistor (TFT) DT controlling a driving current flowing in the OLED depending on a gate-to-source voltage of the driving TFT DT, and a switch circuit SWC for programming the gate-to-source voltage of the driving TFT DT. Each pixel PXL may further include an emission TFT ET for controlling emission timing of the OLED in response to the emission signal EM, if necessary or desired. The switch circuit SWC may include a plurality of switching TFTs, one or more capacitors, and the like. Configuration of the switch circuit SWC can be variously modified according to model and specification of the product. The TFTs included in each pixel PXL may be implemented as PMOS low-temperature polycrystalline silicon (LTPS) TFTs, and thus each pixel PXL can secure desired response characteristics through the PMOS LTPS TFTs. However, embodiments are not limited thereto. For example, at least one of the TFTs may be implemented as an NMOS oxide TFT having good off-current characteristics, and other TFTs may be implemented as PMOS LTPS TFTs having good response characteristics.

For example, each pixel PXL may be driven in response to a gate signal shown in FIG. 4 . In this instance, each pixel PXL may perform an initialization operation, a sampling operation, a holding operation, and an emission operation in response to the first and second scan signals SCAN 1 and SCAN 2 and the emission signal EM. In an initialization period A, the first scan signal SCAN 1 is output at a gate-off voltage VGH, the second scan signal SCAN 2 is output at a gate-on voltage VGL, and the emission signal EM is output at a gate-on voltage VEL. In a sampling period B, the first and second scan signals SCAN 1 and SCAN 2 are output at the gate-on voltage VGL, and the emission signal EM is output at a gate-off voltage VEH. In a holding period C, the first and second scan signals SCAN 1 and SCAN 2 and the emission signal EM are output at the gate-off voltages VGH and VEH. In an emission period D, the first and second scan signals SCAN 1 and SCAN 2 are output at the gate-off voltage VGH, and the emission signal EM is output at the gate-on voltage VEL.

During the initialization period A, the switch circuit SWC can initialize specific nodes of the pixel circuit to a reference voltage Vref in response to the second scan signal SCAN 2 of the gate-on voltage VGL, in order to secure operation stability. During the sampling period B, the switch circuit SWC can program the gate-to-source voltage of the driving TFT DT based on a data voltage Vdata in response to the first scan signal SCAN 1 of the gate-on voltage VGL. Further, during the sampling period B, the switch circuit SWC can sample a threshold voltage of the driving TFT DT in response to the second scan signal SCAN 2 of the gate-on voltage VGL and reflect the sampled threshold voltage to the gate-to-source voltage of the driving TFT DT, thereby compensating for change in the threshold voltage of the driving TFT DT. During the holding period C, the gate-to-source voltage of the driving TFT DT set in the sampling period B is held. During the emission period D, a driving current corresponding to the gate-to-source voltage flows between a source and a drain of the driving TFT DT, and the OLED emits light with the driving current. In this instance, the emission TFT ET may be turned on in response to the emission signal EM of the gate-on voltage VEL.

In FIG. 4 , the gate-on voltage is a voltage of the gate signal capable of turning on the TFT, and the gate-off voltage is a voltage of the gate signal capable of turning off the TFT. For example, a gate-on voltage in the PMOS is gate low voltages VGL and VEL, and a gate-off voltage in the PMOS is gate high voltages VGH and VEH higher than the gate low voltages VGL and VEL. In FIG. 4 , the gate-on voltages VGL and VEL may be equal to or different from each other, and the gate-off voltages VGH and VEH may be equal to or different from each other.

Referring to FIG. 1 , the data driver 120 receives image data DATA and a source timing control signal DDC from the timing controller 110 . The data driver 120 converts the image data DATA into gamma compensation voltages in response to the source timing control signal DDC received from the timing controller 110 and generates data voltages Vdata. The data driver 120 synchronizes the data voltage Vdata with the scan signal SCAN and supplies the data voltage Vdata to the data lines 14 of the display panel 100 . The data driver 120 may be connected to the data lines 14 of the display panel 100 through a chip-on glass (COG) process or a tape automated bonding (TAB) process.

Referring to FIG. 1 , the level shifter 150 boosts a transistor-transistor logic (TTL) level voltage of a gate timing control signal GDC received from the timing controller 110 to the gate-on voltages VGL and VEL and the gate-off voltages VGH and VEH capable of driving the TFTs of the display panel 100 and supplies them to the gate driver 130 . The gate timing control signal GDC may include a start signal, a clock signal, and the like.

Referring to FIG. 1 , the gate driver 130 operates in response to the gate timing control signal GDC received from the level shifter 150 and generates the gate signals. The gate driver 130 sequentially supplies the gate signals to the gate lines. The gate driver 130 may be directly formed on a lower substrate of the display panel 100 using a gate driver-in panel (GIP) manner. The gate driver 130 may be formed in a non-display area (i.e., a bezel area BZ) outside a screen of the display panel 100 . In the GIP manner, the level shifter 150 may be mounted on a printed circuit board (PCB) 140 together with the timing controller 110 .

As shown in FIG. 5 , the gate drivers 130 are disposed on opposite sides of the display panel 100 in a double bank structure and supply the scan signals in a double feeding manner, thereby reducing signal distortion resulting from a load variation of each gate line. The gate driver 130 includes a first scan driver 131 generating the first scan signal SCAN 1 , a second scan driver 132 generating the second scan signal SCAN 2 , and an emission driver 133 generating the emission signal EM.

The first scan driver 131 may supply the first scan signals SCAN 1 to first gate lines 15 a ( 1 ) to 15 a ( n ) in a line sequential manner. The second scan driver 132 may supply the second scan signals SCAN 2 to second gate lines 15 b ( 1 ) to 15 b ( n ) in a line sequential manner. The emission driver 133 may supply the emission signals EM to third gate lines 15 c ( 1 ) to 15 c ( n ) in a line sequential manner. The first and second scan drivers 131 and 132 may be implemented as a gate shift register including a plurality of stages. Each stage may be implemented as shown in FIGS. 7 to 10 , in order to secure operation stability and operation reliability and reduce power consumption by removing a current path interval, in which a voltage of a node Q and a voltage of a node QB are unstable.

Referring to FIG. 1 , the timing controller 110 may be connected to an external host system through known various interface manners. The timing controller 110 receives the image data DATA from the host system. The timing controller 110 may correct the image data DATA and then transmit the corrected image data DATA to the data driver 120 , so that a luminance variation resulting from a difference between electrical characteristics of the pixels PXL is compensated.

The timing controller 110 receives timing signals such as a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE, and a main clock MCLK from the host system. The timing controller 110 may generate the gate timing control signal GDC and the source timing control signal DDC based on the timing signals.

FIG. 6 illustrates a gate shift register included in a first scan driver or a second scan driver shown in FIG. 5 according to an embodiment of the disclosure.

Each of the first scan driver 131 and the second scan driver 132 of FIG. 5 may be implemented as a gate shift register shown in FIG. 6 . A plurality of stages ST 1 to ST 4 , . . . for implementing the gate shift register may be GIP elements directly formed in the bezel area BZ of the display panel 100 .

Operations of the stages ST 1 to ST 4 , . . . are sequentially activated and sequentially output scan signals SCAN( 1 ) to SCAN( 4 ), . . . . The scan signals SCAN( 1 ) to SCAN( 4 ), . . . may be the first scan signal SCAN 1 or the second scan signal SCAN 2 of FIG. 4 .

The operations of the stages ST 1 to ST 4 , . . . are activated in response to a start signal VST or a carry signal CRY and sequentially output the scan signals SCAN( 1 ) to SCAN( 4 ), . . . . An operation of the uppermost stage ST 1 is first activated in response to the start signal VST, and operations of the second uppermost stage ST 2 below the uppermost stage ST 1 to a lowermost stage are sequentially activated in response to the carry signal CRY received from a previous stage. The carry signal CRY is the scan signal of the previous stage. In embodiments disclosed herein, “previous stage” is a stage that is activated earlier than a reference stage and generates a scan signal of which a phase is earlier than a phase of a scan signal output from the reference stage.

The stages ST 1 to ST 4 , . . . may receive the start signal VST, the carry signal CRY, and a plurality of clock signals CLK 1 to CLK 4 , in order to output the scan signals SCAN( 1 ) to SCAN( 4 ), . . . swinging between the gate-off voltage VGH and the gate-on voltage VGL. The start signal VST and the clock signals CLK 1 to CLK 4 swing between the gate-off voltage VGH and the gate-on voltage VGL.

The stages ST 1 to ST 4 , . . . may be connected to power lines AL 1 and AL 2 , clock lines BL 1 to BL 4 , and signal lines CL 1 and CL 2 through a plurality of connection terminals. The stages ST 1 to ST 4 , . . . may be commonly connected to the signal line CL 2 , the power lines AL 1 and AL 2 , and the clock lines BL 1 to BL 4 . The signal line CL 1 may be connected to only the uppermost stage ST 1 that is first operated. Thus, the start signal VST may be input to the uppermost stage ST 1 through the signal line CL 1 , and the clock signals CLK 1 to CLK 4 may be input to all the stages ST 1 to ST 4 , . . . through the clock lines BL 1 to BL 4 . Further, a global reset signal QRST may be input to all the stages ST 1 to ST 4 , . . . through the signal line CL 2 .

To this end, each of the stages ST 1 to ST 4 , . . . includes a first clock terminal B 1 receiving a first clock signal so that the stage is synchronized with the scan signal, a fourth clock terminal B 4 receiving a fourth clock signal so that the stage is synchronized with the start signal VST (or the carry signal CRY) of which a phase is earlier than a phase of the scan signal, a second clock terminal B 2 receiving a second clock signal of which a phase is later than the phase of the scan signal, and a third clock terminal B 3 receiving a third clock signal of which a phase is later than a phase of the second clock signal. Each of the stages ST 1 to ST 4 , . . . further includes a start terminal C 1 receiving the start signal VST or the carry signal CRY, a reset terminal C 2 receiving the global reset signal QRST, a first power terminal A 1 receiving the gate-off voltage VGH, and a second power terminal A 2 receiving the gate-on voltage VGL.

The first to fourth clock signals may be determined among the clock signals CLK 1 to CLK 4 . For an overlap drive, gate-on voltage periods of the clock signals CLK 1 to CLK 4 may overlap one another by a predetermined phase. The clock line BL 1 is supplied with the clock signal CLK 1 configured such that a phase is later than a phase of the clock signal CLK 4 and a gate-on voltage period partially overlaps a gate-on voltage period of the clock signal CLK 4 . The clock line BL 2 is supplied with the clock signal CLK 2 configured such that a phase is later than a phase of the clock signal CLK 1 and a gate-on voltage period partially overlaps a gate-on voltage period of the clock signal CLK 1 . The clock line BL 3 is supplied with the clock signal CLK 3 configured such that a phase is later than a phase of the clock signal CLK 2 and a gate-on voltage period partially overlaps a gate-on voltage period of the clock signal CLK 2 . The clock line BL 4 is supplied with the clock signal CLK 4 configured such that a phase is earlier than a phase of the clock signal CLK 1 and the clock signal CLK 4 is synchronized with the start signal VST or the carry signal CRY.

In this instance, there is a difference in determining the first to fourth clock signals between the four adjacent stages ST 1 to ST 4 . For example, the first to fourth clock signals in the first stage ST 1 may be sequentially the clock signals CLK 1 , CLK 2 , CLK 3 , and CLK 4 ; the first to fourth clock signals in the second stage ST 2 may be sequentially the clock signals CLK 2 , CLK 3 , CLK 4 , and CLK 1 ; the first to fourth clock signals in the third stage ST 3 may be sequentially the clock signals CLK 3 , CLK 4 , CLK 1 , and CLK 2 ; and the first to fourth clock signals in the fourth stage ST 4 may be sequentially the clock signals CLK 4 , CLK 1 , CLK 2 , and CLK 3 .

FIG. 7 illustrates connection configuration of the stage shown in FIG. 6 according to an embodiment of the disclosure. More specifically, FIG. 7 illustrates the uppermost stage ST 1 shown in FIG. 6 . Configuration of each of the remaining stages ST 2 , ST 3 , ST 4 , . . . of FIG. 6 may be substantially the same as configuration of the uppermost stage ST 1 of FIG. 7 , except a difference in the clock signals and the carry signal.

Referring to FIG. 7 , the stage ST 1 may include a reset unit, an output buffer, a Q controller, a QB controller, and a deterioration reducing unit. The deterioration reducing unit is used to further improve the operation stability and thus may be omitted.

In the clock signals CLK 1 to CLK 4 input to the stage ST 1 , as shown in FIG. 11 , gate-on voltage periods of the first and second clock signals CLK 1 and CLK 2 may partially overlap; gate-on voltage periods of the second and third clock signals CLK 2 and CLK 3 may partially overlap; gate-on voltage periods of the third and fourth clock signals CLK 3 and CLK 4 may partially overlap; and gate-on voltage periods of the fourth and first clock signals CLK 4 and CLK 1 may partially overlap. Further, the gate-on voltage periods of the first and third clock signals CLK 1 and CLK 3 may not overlap, and the gate-on voltage periods of the second and fourth clock signals CLK 2 and CLK 4 may not overlap. A reason why the clock signals CLK 1 to CLK 4 are configured as described above is to perform the overlap drive.

The reset unit may be implemented as a transistor T 9 that is switched in response to the global reset signal QRST. The transistor T 9 resets the node Q to the gate-off voltage VGH when the global reset signal QRST is input at the gate-on voltage VGL, thereby securing the operation stability and the operation reliability of the stage. A gate electrode of the transistor T 9 is connected to a reset terminal C 2 . The global reset signal QRST of the gate-on voltage VGL may be input to all the stages in a power-on period of an initial drive. The global reset signal QRST of the gate-on voltage VGL may be input in the initial drive before the start signal VST.

The output buffer may include a transistor T 6 controlled according to the node Q, a transistor T 7 controlled according to the node QB, and a boosting capacitor CQ connected to the node Q.

The transistor T 6 is a pull-up element that outputs the clock signal CLK 1 , as the scan signal SCAN( 1 ), in accordance with the node Q. A gate electrode of the transistor T 6 is connected to the node Q, a first electrode of the transistor T 6 is connected to the clock terminal B 1 , and a second electrode of the transistor T 6 is connected to a node Na.

The boosting capacitor CQ is connected between the node Q and the node Na. When the clock signal CLK 1 is inverted from the gate-off voltage VGH to the gate-on voltage VGL, a voltage of the node Q is reduced from the gate-on voltage VGL to a boosting voltage level lower than the gate-on voltage VGL due to a coupling effect of the boosting capacitor CQ and the node Q. Due to such a bootstrapping effect, a voltage of the node Na is rapidly changed to the gate-on voltage VGL. The scan signal SCAN( 1 ) of the gate-on voltage VGL can be rapidly output using the bootstrapping effect without the distortion or the delay.

The transistor T 7 is a pull-down element that outputs the gate-off voltage VGH, as the scan signal SCAN( 1 ), in accordance with the node QB which is activated as opposed to the node Q. A gate electrode of the transistor T 7 is connected to the node QB, a first electrode of the transistor T 7 is connected to the power terminal A 1 , and a second electrode of the transistor T 7 is connected to the node Na.

The Q controller may include transistors T 1 , T 2 , and T 3 controlling the voltage of the node Q.

The transistors T 1 and T 2 are connected in series between the power terminal A 2 and the node Q. The transistors T 1 and T 2 are switched in response to the start signal VST, of which a phase is earlier than a phase of the clock signal CLK 1 , and the clock signal CLK 4 and activate the node Q to the gate-on voltage VGL. Thus, the clock signal CLK 4 is a Q activation clock signal for activating the node Q. A gate electrode of the transistor T 1 is connected to the start terminal C 1 to which the start signal VST is input, a first electrode of the transistor T 1 is connected to the power terminal A 2 , and a second electrode of the transistor T 1 is connected to a first electrode of the transistor T 2 . A gate electrode of the transistor T 2 is connected to the clock terminal B 4 to which the clock signal CLK 4 is input, the first electrode of the transistor T 2 is connected to the second electrode of the transistor T 1 , and a second electrode of the transistor T 2 is connected to the node Q via a transistor Tbv 2 .

The transistor T 3 deactivates the node Q to the gate-off voltage VGH while the node QB is activated. A gate electrode of the transistor T 3 is connected to the node QB, a first electrode of the transistor T 3 is connected to the power terminal A 1 , and a second electrode of the transistor T 3 is connected to the node Q via a transistor Tbv 3 .

The QB controller may include transistors T 4 , T 5 , T 8 , and T 10 controlling a voltage of the node QB and a capacitor CQB.

The QB controller controls turn-on timing of a transistor T 4 in response to the two clock signals CLK 2 and CLK 3 in the overlap drive, thereby removing a current path interval in which the voltage of the node Q and the voltage of the node QB are unstable. Thus, the clock signals CLK 2 and CLK 3 are QB activation clock signals for activating the node QB. To this end, the QB controller includes the transistor T 10 connected to a gate electrode of the transistor T 4 . The transistor T 4 controls a current flow between the power terminal A 2 and the node QB in response to the clock signal CLK 3 applied to a node Nx. The gate electrode of the transistor T 4 is connected to the node Nx, a first electrode of the transistor T 4 is connected to the power terminal A 2 , and a second electrode of the transistor T 4 is connected to the node QB. The transistor T 10 applies the clock signal CLK 3 to the node Nx in response to the clock signal CLK 2 . A gate electrode of the transistor T 10 is connected to the clock terminal B 2 , a first electrode of the transistor T 10 is connected to the clock terminal B 3 , and a second electrode of the transistor T 10 is connected to the node Nx.

As described above, the QB controller further receives the clock signal CLK 2 in addition to the clock signal CLK 3 and is operated. In this instance, as shown in FIG. 11 , because the gate-on voltage period of the clock signal CLK 2 partially overlaps the gate-on voltage period of the clock signal CLK 3 and does not overlap the gate-on voltage period of the clock signal CLK 4 controlling turn-on timing of the transistor T 2 , the current path interval, in which both the node Q and the node QB are simultaneously activated to the gate-on voltage VGL, can be removed.

The transistor T 5 is switched in response to the start signal VST and deactivates the node QB to the gate-off voltage VGH. A gate electrode of the transistor T 5 is connected to the start terminal C 1 , a first electrode of the transistor T 5 is connected to the power terminal A 1 , and a second electrode of the transistor T 5 is connected to the node QB.

The transistor T 8 deactivates the node QB to the gate-off voltage VGH while the node Q is activated. A gate electrode of the transistor T 8 is connected to the node Q via a transistor Tbv 4 , a first electrode of the transistor T 8 is connected to the power terminal A 1 , and a second electrode of the transistor T 8 is connected to the node QB.

The capacitor CQB is connected between the node QB and the power terminal A 1 and stabilizes the voltage of the node QB while the node QB is floated.

The deterioration reducing unit includes the transistors Tbv 1 , Tbv 2 , Tbv 3 , and Tbv 4 of which gate electrodes are connected to the power terminal A 2 . One electrode of each of the transistors Tbv 1 , Tbv 2 , Tbv 3 , and Tbv 4 is connected to the node Q. The transistors Tbv 1 , Tbv 2 , Tbv 3 , and Tbv 4 maintain a turn-on state due to the gate-on voltage VGL of the power terminal A 2 . However, a gate-to-source voltage of each of the transistors Tbv 1 , Tbv 2 , Tbv 3 , and Tbv 4 is less than a threshold voltage while the voltage of the node Q is boosted due to the bootstrapping. Therefore, in this instance, the transistors Tbv 1 , Tbv 2 , Tbv 3 , and Tbv 4 are turned off.

The transistor Tbv 1 controls a current path between the node Q and the transistor T 9 . The transistor Tbv 1 maintains a turn-on state and is turned off only while the voltage of the node Q is boosted, thereby blocking current between the node Q and the transistor T 9 . Even when the voltage of the node Q is boosted, the boosting voltage of the node Q does not affect one electrode of the transistor T 9 . Therefore, an increase in a drain-to-source voltage of the transistor T 9 resulting from the boosting voltage of the node Q is prevented. If the drain-to-source voltage of the transistor T 9 increases to a value equal to or greater than a critical value, a device breakdown phenomenon, so-called, a breakdown phenomenon may occur due to an overload. Thus, the transistor Tbv 1 can prevent the breakdown phenomenon.

The transistor Tbv 2 controls a current path between the node Q and the transistor T 2 . The transistor Tbv 2 maintains a turn-on state and is turned off only while the voltage of the node Q is boosted, thereby blocking current between the node Q and the transistor T 2 . Even when the voltage of the node Q is boosted, the boosting voltage of the node Q does not affect one electrode of the transistor T 2 . Thus, the transistor Tbv 2 can prevent the breakdown phenomenon caused when a drain-to-source voltage of the transistor T 2 exceeds a critical value due to the boosting voltage of the node Q.

The transistor Tbv 3 controls a current path between the node Q and the transistor T 3 . The transistor Tbv 3 maintains a turn-on state and is turned off only while the voltage of the node Q is boosted, thereby blocking current between the node Q and the transistor T 3 . Even when the voltage of the node Q is boosted, the boosting voltage of the node Q does not affect one electrode of the transistor T 3 . Thus, the transistor Tbv 3 can prevent the breakdown phenomenon caused when a drain-to-source voltage of the transistor T 3 exceeds a critical value due to the boosting voltage of the node Q.

The transistor Tbv 4 controls a current path between the node Q and the transistor T 8 . The transistor Tbv 4 maintains a turn-on state and is turned off only while the voltage of the node Q is boosted, thereby blocking current between the node Q and the transistor T 8 . Even when the voltage of the node Q is boosted, the boosting voltage of the node Q does not affect the gate electrode of the transistor T 8 . Thus, the transistor Tbv 4 can prevent the breakdown phenomenon caused when a gate-to-drain voltage of the transistor T 8 exceeds a critical value due to the boosting voltage of the node Q.

The transistors T 3 , T 4 , T 5 , T 8 , and T 9 may be configured in a dual gate structure, so that they can suppress a leakage current when they are turned off. In the dual gate structure, two gate electrodes are connected to each other so that they have the same voltage level. A channel length of the dual gate structure is longer than a channel length of a single gate structure. Because an increase in the channel length results in an increase in a resistance, a leakage current decreases when the transistor is turned off. Hence, the operation stability can be secured.

FIG. 8 illustrates another connection configuration of the stage shown in FIG. 6 according to an embodiment of the disclosure. More specifically, FIG. 8 illustrates the uppermost stage ST 1 shown in FIG. 6 . Configuration of each of the remaining stages ST 2 , ST 3 , ST 4 , . . . of FIG. 6 may be substantially the same as configuration of the uppermost stage ST 1 of FIG. 8 , except a difference in the clock signals and the carry signal.

Configuration of the stage ST 1 shown in FIG. 8 is substantially the same as the configuration of the stage ST 1 shown in FIG. 7 , except the QB controller. Thus, duplicative description will be omitted for brevity.

In the stage ST 1 shown in FIG. 8 , a QB controller controls turn-on timing of a transistor T 4 in response to two clock signals CLK 2 and CLK 3 in an overlap drive, thereby removing a current path interval in which the voltage of the node Q and the voltage of the node QB are unstable. In particular, the QB controller further includes a capacitor CX and secures operation stability of the transistor T 4 .

To this end, the QB controller includes a transistor T 10 connected to a gate electrode of the transistor T 4 . The transistor T 4 controls a current flow between the power terminal A 2 and the node QB in response to the clock signal CLK 3 applied to a node Nx. The gate electrode of the transistor T 4 is connected to the node Nx, a first electrode of the transistor T 4 is connected to the power terminal A 2 , and a second electrode of the transistor T 4 is connected to the node QB. The transistor T 10 applies the clock signal CLK 3 to the node Nx in response to the clock signal CLK 2 . A gate electrode of the transistor T 10 is connected to the clock terminal B 2 , a first electrode of the transistor T 10 is connected to the clock terminal B 3 , and a second electrode of the transistor T 10 is connected to the node Nx. The capacitor CX is connected to the node Nx and the clock terminal B 2 , in order to stabilize a gate voltage of the transistor T 4 .

As described above, the QB controller further receives the clock signal CLK 2 in addition to the clock signal CLK 3 and is operated. In this instance, as shown in FIG. 11 , because the gate-on voltage period of the clock signal CLK 2 partially overlaps the gate-on voltage period of the clock signal CLK 3 and does not overlap the gate-on voltage period of the clock signal CLK 4 controlling turn-on timing of a transistor T 2 , the current path interval, in which both the node Q and the node QB are simultaneously activated to the gate-on voltage VGL, can be removed. Further, an operation of the transistor T 4 can be further stabilized by the capacitor CX.

FIG. 9 illustrates another connection configuration of the stage shown in FIG. 6 according to an embodiment of the disclosure. More specifically, FIG. 9 illustrates the uppermost stage ST 1 shown in FIG. 6 . Configuration of each of the remaining stages ST 2 , ST 3 , ST 4 , . . . of FIG. 6 may be substantially the same as configuration of the uppermost stage ST 1 of FIG. 9 , except a difference in the clock signals and the carry signal.

Configuration of the stage ST 1 shown in FIG. 9 is substantially the same as the configuration of the stage ST 1 shown in FIG. 7 , except the QB controller. Thus, duplicative description will be omitted for brevity.

In the stage ST 1 shown in FIG. 9 , a QB controller controls turn-on timing of a transistor T 4 in response to two clock signals CLK 2 and CLK 3 in an overlap drive, thereby removing a current path interval in which the voltage of the node Q and the voltage of the node QB are unstable.

To this end, the QB controller includes a transistor T 11 and the transistor T 4 that are connected in series between the power terminal A 2 and the node QB. A gate electrode of the transistor T 11 is connected to the clock terminal B 2 , a first electrode of the transistor T 11 is connected to the power terminal A 2 , and a second electrode of the transistor T 11 is connected to a node Ny. A gate electrode of the transistor T 4 is connected to the clock terminal B 3 , a first electrode of the transistor T 4 is connected to the node Ny, and a second electrode of the transistor T 4 is connected to the node QB. FIG. 9 illustrates that the transistor T 11 is connected between the power terminal A 2 and the transistor T 4 , by way of example. However, the transistor T 4 may be connected between the power terminal A 2 and the transistor T 11 . In this instance, the gate electrode of the transistor T 4 is connected to the clock terminal B 3 , the first electrode of the transistor T 4 is connected to the power terminal A 2 , and the second electrode of the transistor T 4 is connected to the node Ny. The gate electrode of the transistor T 11 is connected to the clock terminal B 2 , the first electrode of the transistor T 11 is connected to the node Ny, and the second electrode of the transistor T 11 is connected to the node QB.

As described above, the QB controller further receives the clock signal CLK 2 in addition to the clock signal CLK 3 and is operated. In this instance, as shown in FIG. 11 , because the gate-on voltage period of the clock signal CLK 2 partially overlaps the gate-on voltage period of the clock signal CLK 3 and does not overlap the gate-on voltage period of the clock signal CLK 4 controlling turn-on timing of a transistor T 2 , the current path interval, in which both the node Q and the node QB are simultaneously activated to the gate-on voltage VGL, can be removed.

FIG. 10 illustrates another connection configuration of the stage shown in FIG. 6 according to an embodiment of the disclosure. More specifically, FIG. 10 illustrates the uppermost stage ST 1 shown in FIG. 6 . Configuration of each of the remaining stages ST 2 , ST 3 , ST 4 , . . . of FIG. 6 may be substantially the same as configuration of the uppermost stage ST 1 of FIG. 10 , except a difference in the clock signals and the carry signal.

Configuration of the stage ST 1 shown in FIG. 10 is substantially the same as the configuration of the stage ST 1 shown in FIG. 7 , except the QB controller. Thus, duplicative description will be omitted for brevity.

In the stage ST 1 shown in FIG. 10 , a QB controller controls a timing, at which the node QB is activated to the gate-on voltage VGL, in response to two clock signals CLK 2 and CLK 3 in an overlap drive, thereby removing a current path interval in which the voltage of the node Q and the voltage of the node QB are unstable.

To this end, the QB controller includes a transistor T 11 and a transistor T 4 that are connected in series between the power terminal A 2 and the node QB. A gate electrode of the transistor T 11 is connected to the clock terminal B 2 , a first electrode of the transistor T 11 is connected to the power terminal A 2 , and a second electrode of the transistor T 11 is connected to a node Ny. A gate electrode of the transistor T 4 is connected to the clock terminal B 3 , a first electrode of the transistor T 4 is connected to the node Ny, and a second electrode of the transistor T 4 is connected to the node QB. FIG. 10 illustrates that the transistor T 11 is connected between the power terminal A 2 and the transistor T 4 , by way of example. However, the transistor T 4 may be connected between the power terminal A 2 and the transistor T 11 . In this instance, the gate electrode of the transistor T 4 is connected to the clock terminal B 3 , the first electrode of the transistor T 4 is connected to the power terminal A 2 , and the second electrode of the transistor T 4 is connected to the node Ny. The gate electrode of the transistor T 11 is connected to the clock terminal B 2 , the first electrode of the transistor T 11 is connected to the node Ny, and the second electrode of the transistor T 11 is connected to the node QB.

As described above, the QB controller further receives the clock signal CLK 2 in addition to the clock signal CLK 3 and is operated. In this instance, as shown in FIG. 11 , because the gate-on voltage period of the clock signal CLK 2 partially overlaps the gate-on voltage period of the clock signal CLK 3 and does not overlap the gate-on voltage period of the clock signal CLK 4 controlling turn-on timing of a transistor T 2 , the current path interval, in which both the node Q and the node QB are simultaneously activated to the gate-on voltage VGL, can be removed.

The QB controller may further include a transistor T 12 that is connected in parallel to the transistor T 11 and is turned on or off in response to an overlap control signal OVL. The overlap control signal OVL is input at a turn-on level in a non-overlap drive and is input at a turn-off level in the overlap drive. The overlap drive allows gate-on voltage periods of adjacent scan signals to partially overlap one another using clock signals which overlap one another by a predetermined phase as shown in FIG. 11 . The non-overlap drive allows gate-on voltage periods of scan signals not to overlap one another using clock signals, of which gate-on voltage periods do not overlap as shown in FIG. 12 . The overlap drive or the non-overlap drive may be determined depending on a length of the initialization period A and a length of the sampling period B of FIG. 4 . For example, because a length of the initialization period A and a length of the sampling period B are short in a high resolution display device, a sufficient time can be ensured through the overlap drive. When the stages are configured as shown in FIG. 10 , the overlap drive or the non-overlap drive can be easily selected. Thus, embodiments of the disclosure can easily accommodate various models and specifications of display devices.

In the overlap drive, the transistor T 12 is turned off, and an operation of the QB controller is as described above.

In the non-overlap drive, the transistor T 12 is turned on, and turn-on timing of the transistor T 4 is controlled by the clock signal CLK 3 irrespective of the clock signal CLK 2 . As shown in FIG. 12 , because the gate-on voltage period of the clock signal CLK 3 does not overlap the gate-on voltage period of the clock signal CLK 4 controlling the turn-on timing of the transistor T 2 , the current path interval, in which both the node Q and the node QB are simultaneously activated to the gate-on voltage VGL, can be removed.

FIG. 11 illustrates an operation waveform of a stage in accordance with an overlap drive according to an embodiment of the disclosure. FIGS. 13A to 13E illustrate operation states of a stage respectively corresponding to periods {circle around ( 1 )} to {circle around ( 5 )} shown in FIG. 11 according to an embodiment of the disclosure. In FIG. 11 , “1H” indicates one horizontal period allocated to drive one horizontal pixel line. In the periods {circle around ( 1 )} to {circle around ( 5 )} shown in FIG. 11 , the global reset signal QRST is continuously input at the gate-off voltage VGL.

Referring to FIGS. 11 and 13A , in the period {circle around ( 1 )}, the start signal VST and the clock signals CLK 3 and CLK 4 are input at the gate-on voltage VGL, and the clock signals CLK 1 and CLK 2 are input at the gate-off voltage VGH.

In the period {circle around ( 1 )}, the transistors T 1 and T 5 are turned on in response to the start signal VST of the gate-on voltage VGL, and the transistor T 2 is turned on in response to the clock signal CLK 4 of the gate-on voltage VGL. Further, the transistors T 10 and T 4 are turned on in response to the clock signal CLK 2 of the gate-off voltage VGH.

In the period {circle around ( 1 )}, the transistors Tbv 1 , Tbv 2 , Tbv 3 and Tbv 4 maintain an on-state.

In the period {circle around ( 1 )}, the transistors T 1 and T 2 are turned on in response to the start signal VST of the gate-on voltage VGL and the clock signal CLK 4 of the gate-on voltage VGL, and the node Q is activated to the gate-on voltage VGL. The transistors T 6 and T 8 are turned on by the gate-on voltage VGL of the node Q. Thus, the clock signal CLK 1 of the gate-off voltage VGH as the scan signal SCAN( 1 ) is output to the node Na due to the turn-on of the transistor T 6 .

In the period {circle around ( 1 )}, the transistor T 8 is turned on by the gate-on voltage VGL of the node Q, and the transistor T 5 is turned on in response to the start signal VST of the gate-on voltage VGL. Therefore, the node QB is deactivated to the gate-off voltage VGH, and the transistors T 3 and T 7 are turned off.

Referring to FIGS. 11 and 13B , in the period {circle around ( 2 )}, the start signal VST and the clock signals CLK 1 and CLK 4 are input at the gate-on voltage VGL, and the clock signals CLK 2 and CLK 3 are input at the gate-off voltage VGH.

In the period {circle around ( 2 )}, the transistors T 1 and T 5 maintain an on-state in response to the start signal VST of the gate-on voltage VGL, and the transistor T 2 maintains an on-state in response to the clock signal CLK 4 of the gate-on voltage VGL. Further, the transistor T 4 maintains an off-state in response to the clock signals CLK 2 and CLK 3 of the gate-off voltage VGH.

In the period {circle around ( 2 )}, the clock signal CLK 1 is inverted from the gate-off voltage VGH to the gate-on voltage VGL and is input to the clock terminal B 1 . When the voltage of the clock terminal B 1 is reduced from the gate-off voltage VGH to the gate-on voltage VGL due to a coupling effect of a parasitic capacitor existing between the clock terminal B 1 and the node Q, the voltage of the node Q is reduced from the gate-on voltage VGL to a boosting voltage BL. As a result, the clock signal CLK 1 of the gate-on voltage VGL is charged to the node Na through the transistor T 6 without the delay and the distortion. In other words, the scan signal SCAN( 1 ) of the gate-on voltage VGL is rapidly output to the node Na.

In the period {circle around ( 2 )}, as the voltage of the node Q is reduced from the gate-on voltage VGL to the boosting voltage BL, the transistors Tbv 1 , Tbv 2 , Tbv 3 and Tbv 4 are turned off. The transistors Tbv 1 , Tbv 2 , Tbv 3 and Tbv 4 are turned off while the voltage of the node Q is boosted, and blocks an overload from being applied to the transistors T 2 , T 3 , T 8 and T 9 .

In the period {circle around ( 2 )}, the gate electrode of the transistor T 8 is floated, the transistor T 8 maintains an on-state, and the transistors T 4 and T 10 maintain an off-state in response to the clock signals CLK 2 and CLK 3 of the gate-off voltage VGH. Therefore, the node QB holds the gate-off voltage VGH, and the transistors T 3 and T 7 maintain an off-state.

Referring to FIGS. 11 and 13C , in the period {circle around ( 3 )}, the start signal VST and the clock signals CLK 3 and CLK 4 are input at the gate-off voltage VGH, and the clock signals CLK 1 and CLK 2 are input at the gate-on voltage VGL.

In the period {circle around ( 3 )}, the transistors T 1 and T 5 maintain an off-state in response to the start signal VST of the gate-off voltage VGH, and the transistor T 2 is turned off in response to the clock signal CLK 4 of the gate-off voltage VGH. Further, the transistor T 10 is turned on in response to the clock signal CLK 2 of the gate-on voltage VGL, and the transistor T 4 maintains an off-state in response to the clock signal CLK 3 of the gate-off voltage VGH.

In the period {circle around ( 3 )}, the node Q is floated. Because the voltage of the clock terminal B 1 is held at the gate-on voltage VGL in the period {circle around ( 3 )}, the voltage of the node Q is held at the boosting voltage BL. Further, the transistors Tbv 1 , Tbv 2 , Tbv 3 and Tbv 4 maintain an off-state, and the transistors T 6 and T 8 maintain an on-state. As a result, the scan signal SCAN( 1 ) of the gate-on voltage VGL is output to the node Na through the transistor T 6 .

Referring to FIGS. 11 and 13D , in the period {circle around ( 4 )}, the start signal VST and the clock signals CLK 4 and CLK 1 are input at the gate-off voltage VGH, and the clock signals CLK 2 and CLK 3 are input at the gate-on voltage VGL.

In the period {circle around ( 4 )}, the transistors T 1 and T 5 maintain an off-state in response to the start signal VST of the gate-off voltage VGH, and the transistor T 2 maintains an off-state in response to the clock signal CLK 4 of the gate-off voltage VGH. Further, the transistors T 4 and T 10 are turned on in response to the clock signals CLK 2 and CLK 3 of the gate-on voltage VGL.

In the period {circle around ( 4 )}, the gate-on voltage VGL is applied to the node QB due to the turn-on of the transistor T 4 . Further, the transistors T 7 and T 3 are turned on by the node QB of the gate-on voltage VGL. As a result, the scan signal SCAN( 1 ) of the gate-off voltage VGH is output to the node Na through the transistor T 7 , and the gate-off voltage VGH is applied to the node Q through the transistor T 3 .

In the period {circle around ( 4 )}, the voltage of the node Q is inverted to the gate-off voltage VGH, and the transistors Tbv 1 , Tbv 2 , Tbv 3 and Tbv 4 are turned on. Further, the transistor T 6 is turned off by the node Q of the gate-off voltage VGH.

Referring to FIGS. 11 and 13E , in the period {circle around ( 5 )}, the start signal VST and the clock signals CLK 1 and CLK 2 are input at the gate-off voltage VGH, and the clock signals CLK 3 and CLK 4 are input at the gate-on voltage VGL.

In the period {circle around ( 5 )}, the transistors T 1 and T 5 maintain an off-state in response to the start signal VST of the gate-off voltage VGH, and the transistor T 2 is turned on in response to the clock signal CLK 4 of the gate-on voltage VGL. Further, the transistor T 10 is turned off in response to the clock signal CLK 2 of the gate-off voltage VGH, and the node Nx is floated. Because the node Nx is held at the gate-on voltage VGL, the transistor T 4 maintains an on-state.

In the period {circle around ( 5 )}, the gate-on voltage VGL is continuously applied to the node QB via the transistor T 4 , and the transistors T 7 and T 3 maintain an on-state by the node QB of the gate-on voltage VGL. As a result, the scan signal SCAN( 1 ) of the gate-off voltage VGH is continuously output to the node Na through the transistor T 7 , and the gate-off voltage VGH is continuously applied to the node Q through the transistor T 3 .

In the period {circle around ( 5 )}, because the voltage of the node Q is held at the gate-off voltage VGH, the transistors Tbv 1 , Tbv 2 , Tbv 3 and Tbv 4 are turned on. Further, the transistor T 6 maintains an off-state by the node Q of the gate-off voltage VGH.

As described above, the embodiments of the disclosure control a timing, at which the node QB is activated, in response to the second and third clock signals, of which the gate-on voltage periods partially overlap each other, in the overlap drive and do not overlap the gate-on voltage period of the fourth clock signal for activating the node Q and the gate-on voltage period of the second clock signal, thereby removing the current path interval in which the voltage of the node Q and the voltage of the node QB are simultaneously activated. Thus, the embodiments of the disclosure can secure the operation stability and the operation reliability and reduce the power consumption by removing the current path interval in which the voltage of the node Q and the voltage of the node QB are unstable.

Although the embodiments have been described with reference to a number of illustrative embodiments thereof, numerous other modifications and embodiments may be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. In particular, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.