Hybrid differential amplifier and method thereof

The present invention generally relates to differential amplifier circuits, and more particularly one that can alleviate the adverse effect of the ground bounce and source degeneration.

As depicted in FIG. 1 , a conventional differential amplifier 100 comprises a core circuit 110 and a load 130 . The core circuit 110 comprises a differential pair 111 and a cascode pair 112 . The differential pair 111 comprises a first NMOS (n-channel metal oxide semiconductor) transistor 111 A and a second NMOS transistor 111 B configured to receive an input signal comprising a first end V IP and a second end V IN and output a first current I 1a and a second current I 1b , while the cascode pair 112 comprises a third NMOS transistor 112 A and a fourth NMOS transistor 112 B configured to receive the first current I 1a and the second current I 1b and output a third current I 1c and a fourth current I 1d . The load 130 comprises a first inductor 131 and a second inductor 132 configured to provide termination to the third current I 1c and the fourth current I 1d and establish an output signal comprising a first end V ON and a second end V OP . Throughout this disclosure, “V DD ” denotes a first DC (direct current) node referred to as a power node, and “V SS ” denotes a second DC node referred to as a ground node. In FIG. 1 , “V BC ” denotes a DC node that provides a bias voltage for NMOS transistors 112 A and 112 B of the cascode pair 112 . Conventional differential amplifier 100 is well known by those of ordinary skills in the art and thus not described in detail here. Mathematically, V 1p and V IN can be expressed by

V IP =V BI +v in ( t )  (1)

V IN =V BI −v in ( t )  (2)

Here, V BI is DC (direct current) component of V IP and V IN that establishes a bias voltage for NMOS transistors 111 A and 111 B, and v in (t) represents an AC (alternating current) signal as a function of time t.

An issue with the conventional differential amplifier 100 is: when v in (t) is large, there is a large AC current flowing into the ground node “V SS .” Ideally, the ground node “V SS ” has zero impedance and thus will not be perturbed by the large AC current. In practice, however, the ground node “V SS ” has nonzero impedance, resulting in a “ground bounce” and a “source degeneration” that can reduce a gain of the differential pair 111 and thus degrade a performance aspect of the differential amplifier 100 .

What is desired is a differential amplifier that can alleviate the adverse effect of the ground bounce and source degeneration.

In an embodiment, an apparatus comprises: a first common-source amplifier comprising a first PMOS (p-channel metal oxide semiconductor) transistor configured to receive a first voltage and output a first current; a second common-source amplifier comprising a first NMOS (n-channel metal oxide semiconductor) transistor configured to receive a second voltage and output a second current, wherein the first common-source amplifier and the second common-source amplifier share a common source node, and an AC (alternating current) component of the first voltage is an inversion of an AC component of the second voltage; a first common-gate amplifier comprising a second PMOS transistor configured to receive the first current and output a third current; a second common-gate amplifier comprising a second NMOS transistor configured to receive the second current and output a fourth current; and a load configured to terminate the third current and the fourth current.

In an embodiment, an apparatus comprises: a first hybrid differential amplifier configured to receive a first input signal and a second input signal and output a first output signal and a second output signal using a first cascode amplifier and a second cascode amplifier, respectively; and a second hybrid differential amplifier configured to receive a third input signal and a fourth input signal and output a third output signal and a fourth output signal using a third cascode amplifier and a fourth cascode amplifier, respectively; wherein: the first cascode amplifier and the third cascode amplifier are based on using PMOS (p-channel metal oxide semiconductor) transistors, the second cascode amplifier and the fourth cascode amplifier are based on using NMOS (n-channel metal oxide semiconductor) transistors, a DC (direct current) component of the first input signal is the same as a DC component of the third input signal, a DC component of the second input signal is the same as a DC component of the fourth input signal, an AC (alternating current) component of the first input signal is the same as an AC component of the fourth input signal, an AC component of the second input signal is the same as an AC component of the third input signal, and the AC component of the second input signal is an inversion of the AC component of the first input signal.

In an embodiment, a method comprises: receiving a first voltage and a second voltage, wherein an AC (alternating current) component of the first voltage is an inversion of an AC component of the second voltage; converting the first voltage into a first current using a first common-source amplifier comprising a first PMOS (p-channel metal oxide semiconductor) transistor; converting the second voltage into a second current using a second common-source amplifier comprising a first NMOS (n-channel metal oxide semiconductor) transistor, wherein the first common-source amplifier and the second common-source amplifier share a common source node; relaying the first current into a third current using a first common-gate amplifier comprising a second PMOS transistor; relaying the second current into a fourth current using a second common-gate amplifier comprising a second NMOS transistor; and terminating the third current and the fourth current with a load.

FIG. 1 shows a schematic diagram of a conventional differential amplifier.

FIG. 2A shows a schematic diagram of a hybrid differential amplifier in accordance with an embodiment of the present invention.

FIG. 2B shows a schematic diagram of a hybrid differential amplifier in accordance with an alternative embodiment of the present invention.

FIG. 3 shows a schematic diagram of a complementary hybrid differential amplifier in accordance with an embodiment of the present invention

FIG. 4A shows a schematic diagram of a power combining network.

FIG. 4B shows a schematic diagram of another power combining network.

FIG. 5 shows a flow diagram of a method in accordance with the present invention.

The present invention relates to differential amplifiers. While the specification describes several example embodiments of the invention considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “current,” “signal,” “differential signal,” “common mode,” “capacitor,” “inductor,” “resistor,” “transistor,” “MOS (metal-oxide semiconductor),” “PMOS (p-channel metal oxide semiconductor),” “NMOS (n-channel metal oxide semiconductor),” “AC (alternating current),” “DC (direct current),” “DC-coupled,” “AC coupled,” “source,” “gate,” “drain,” “node,” “ground node,” “power node,” “cascode,” “common-source amplifier,” “common-gate amplifier,” and “cascode amplifier.” Those of ordinary skill in the art can also readily recognize a symbol of a MOS transistor, and its associated “source,” “gate,” and “drain” terminals. Terms and basic concepts like these are apparent to those of ordinary skill in the art and thus will not be explained in detail here.

Throughout this disclosure, “DC” stands for direct current, and “AC” stands for alternating current. A DC node is a node of a substantially fixed electric potential. In particular, “V DD ” denotes a first DC node referred to as a power node, and “V SS ” denotes a second DC node referred to as a ground node. As well, a differential signal is a composite signal that comprises a first constituent signal and a second constituent signal. The first constituent signal is often referred to as a first end, while the second constituent signal is often referred to as a second end.

A schematic diagram of a hybrid differential amplifier 200 A, in accordance with an embodiment of the present invention, is shown in FIG. 2A . Hybrid differential amplifier 200 A comprises a core circuit 210 and a load 230 . The core circuit 210 comprises a hybrid differential pair 211 and a hybrid cascode pair 212 . The hybrid differential pair 211 comprises a first PMOS transistor 211 P and a first NMOS transistor 211 N embodying a pair of common-source amplifiers configured to receive an input signal comprising a first end V P+ and a second end V N− and output a first current I 2a and a second current I 2b . In an optional embodiment, the hybrid differential pair 211 further comprise a first neutralization capacitor CN 1 configured to couple the gate of the first PMOS transistor 211 P to the drain of the first NMOS transistor 211 N, and a second neutralization capacitor CN 2 configured to couple the gate of the first NMOS transistor 211 N to the drain of the first PMOS transistor 211 P. Neutralization capacitors CN 1 and CN 2 can alleviate a Miller effect of hybrid differential pair 211 . The Miller effect is well known to those of ordinary skill in the art and thus is not described herein.

The cascode pair 212 comprises a second PMOS transistor 212 P and a second NMOS transistor 212 N embodying a pair of common-gate amplifiers configured to receive the first current I 2d and the second current I 2b and output a third current I 2c and a fourth current I 2d , respectively. From another perspective, the first PMOS transistor 211 P and the second PMOS transistor 212 P form a first cascode amplifier configured to receive V P+ and output I 2c , while the first NMOS transistor 211 N and the second NMOS transistor 212 N form a second cascode amplifier configured to receive V N− and output I 2d . The load 230 comprises a first inductor 231 and a second inductor 232 configured to provide termination to the third current I 2c and the fourth current I 2d and establish an output signal comprising a first end V 2c and a second end V 2d . In an optional embodiment, the load 230 further includes a tuning capacitor 233 configured to tune an impedance of the load 230 . In FIG. 2A , “V BC1 ” denotes a bias voltage for PMOS transistors 212 P and “V BC2 ” denotes a bias voltage for NMOS transistors 212 N. Mathematically, V P+ and V N− can be expressed by

V P+ =V BP +v in ( t )  (3)

V N− =V BN −v in ( t )  (4)

Here, V BP is a DC component of V P+ that establishes a biasing for PMOS transistor 211 P, V BN is a DC component of V N− that establishes a biasing for NMOS transistor 211 N, and v in (t) represents an AC (alternating current) signal as a function of time t. Although V P+ and V N− have different DC components, they have the same AC component except for a polarity inversion. As far as the AC component is concerned, V P+ and V N− form a differential signal. Functionally, hybrid differential amplifier 200 A and conventional differential amplifier 100 are the same, as far as the AC component is concerned. However, instead of using devices of the same type to amplify a differential signal, hybrid differential amplifier 200 A uses devices of different types: PMOS transistors 211 P and 212 P are used to amplify V P+ , while NMOS transistors 211 N and 212 N are used to amplify V N− . Provided the first cascode amplifier (comprising PMOS transistors 211 P and 212 P) and the second cascode amplifier (comprising NMOS transistors 211 N and 212 N) are properly sized and biased to have substantially equal transconductance, the first current I 2a will be substantially equal to the second current I 2b , and the voltage V CS at the common source node 219 can be substantially fixed even though V P+ and V N− vary with v in (t). Therefore, a large v in (t) does not lead to a substantial “source degeneration” to PMOS transistor 211 P and NMOS transistor 211 N. Therefore, hybrid differential amplifier 200 A is by nature superior to the conventional differential amplifier 100 of FIG. 1 in that regard.

FIG. 2B shows a schematic diagram of a hybrid differential amplifier 200 B in accordance with an alternative embodiment of the present invention. Hybrid differential amplifier 200 B of FIG. 2B is the same as hybrid differential amplifier 200 A of FIG. 2A except that the core circuit 210 in FIG. 2A is replaced by an alternative core circuit 210 _ 1 in FIG. 2B , which is the same as the core circuit 210 in FIG. 2A except that the hybrid cascode pair 212 in the core circuit 210 is replaced by an alternative hybrid cascode pair 212 _ 1 in the alternative core circuit 210 _ 1 . The hybrid cascode pair 212 _ 1 is the same as the hybrid cascode pair 212 except that the sources and gates of PMOS transistor 212 P and NMOS transistor 212 N are cross coupled via a first capacitor C 1 and a second capacitor C 2 , while the drains and gates of PMOS transistor 212 P and NMOS transistor 212 N are cross coupled via a third capacitor C 3 and a fourth capacitor C 4 . More specifically, the source of NMOS transistor 212 N is coupled to the gate of PMOS transistor 212 P via capacitor C 1 ; the source of PMOS transistor 212 P is coupled to the gate of NMOS transistor 212 N via capacitor C 2 ; the drain of NMOS transistor 212 N is coupled to the gate of the PMOS transistor 212 P via capacitor C 3 ; and the drain of PMOS transistor 212 P is coupled to the gate of NMOS transistor 212 N via capacitor C 4 . Besides, a first resistor R 1 is inserted between the gate of PMOS transistor 212 P and “V BC1 ,” and a second resistor R 2 is inserted between the gate of NMOS transistor 212 N and “V BC2 ”.

This arrangement makes the biasing condition of the alternative hybrid differential amplifier 200 B the same as that of the hybrid differential amplifier 200 A. The cross-coupling of sources and gates between the PMOS transistor 212 P and the NMOS transistor 212 N via capacitors C 1 and C 2 can provide a first positive feedback that can effectively enhance a gain of the hybrid differential amplifier 200 B. The cross-coupling of drains and gates between the PMOS transistor 212 P and the NMOS transistor 212 N via capacitors C 3 and C 4 can provide a second positive feedback that can also effectively enhance a gain of the hybrid differential amplifier 200 B. In fact, the second positive feedback tends to be stronger and more effective than the first positive feedback, since a voltage signal at a drain tends to be stronger than a voltage signal at a source of a MOS transistor, and this applies to PMOS transistor 212 P and NMOS transistor 212 N. However, the second positive feedback may potentially lead to instability due to having a high gain and thus must be used with caution. In another embodiment, capacitors C 3 and C 4 are removed; that is, the second positive feedback is not used.

A schematic diagram of a complementary hybrid differential amplifier 300 in accordance with an embodiment of the present invention is depicted in FIG. 3 . The complementary hybrid differential amplifier 300 comprises a first hybrid differential amplifier 310 and a second hybrid differential amplifier 320 . The first hybrid differential amplifier 310 is the same as the hybrid differential amplifier 200 A in FIG. 2A . (Note that the optional embodiments including capacitors 233 , CN 1 , and CN 2 in FIG. 2A are not explicitly shown in FIG. 3 for brevity, but they can be applied at the discretion of circuit designers.) The second hybrid differential amplifier 320 is the same as the first hybrid differential amplifier 310 , except that the inputs to the second hybrid differential amplifier 320 are V P− and V N+ , instead of V P+ and V N− , wherein

V P− =V BP −v in ( t )  (5)

V N+ =V BN +v in ( t )  (6)

This way, the inputs to the second hybrid differential amplifier 320 are complementary to the inputs to the first hybrid differential amplifier 310 . The common-source nodes of the two hybrid differential amplifiers 310 and 320 are tied together, resulting in a common source voltage V CM . The first hybrid differential amplifier 310 has two inductors labeled as 311 and 312 ; the second hybrid differential amplifier 320 has two inductors labeled as 321 and 322 ; V 3a and V 3b denote voltages at output nodes N 311 and N 312 , respectively, of the first hybrid differential amplifier 310 ; V 3c and V 3d denote voltages at output nodes N 321 and N 322 , respectively, of the second hybrid differential amplifier 320 ; I 3a and I 3b denote currents of inductors 311 and 312 , respectively; and I 3c and I 3d denote currents of inductors 321 and 322 , respectively.

In an alternative embodiment not explicitly shown in figure but clear to those of ordinary skills in the art, the two hybrid differential amplifiers 310 and 320 are both replaced by the hybrid differential amplifier 200 B in FIG. 2B ; that is, a positive feedback is used to enhance a gain.

Outputs of the first hybrid differential amplifier 310 (i.e. V 3a and V 3b , or I 3a and I 3b ) and outputs of the second hybrid differential amplifiers 320 (i.e. V 3c and V 3d , or I 3c and I 3d ) can be combined using a power combining network 400 A shown in FIG. 4A . Power combining network 400 A comprises: inductor 411 configured to have an inductive coupling K 11 with inductor 311 ; inductor 412 configured to have an inductive coupling K 12 with inductor 312 ; inductor 421 configured to have an inductive coupling K 21 with inductor 321 ; and inductor 422 configured to have an inductive coupling K 22 with inductor 322 . Inductors 411 , 412 , 421 , and 422 are connected in a manner so that their respective voltages coupled from inductors 311 , 312 , 321 , and 322 can be effectively summed, resulting in voltages V 4a and V 4b at nodes N 412 and N 422 , respectively, that can represent a sum of V 3a , V 3b , V 3c , and V 3d . By way of example for explanation purpose: inductors 311 , 312 , 321 , 322 , 411 , 412 , 421 , and 422 all have the same inductance, and the inductive couplings K 11 , K 12 , K 21 , and K 22 all have a coupling coefficient that is approximately unity, then we have

V 4a −V 4b =V 3b −V 3a +V 3c −V 3d   (7)

Note that V 3b −V 3a represents an output of the first hybrid differential amplifier 310 , and V 3c −V 3d represents an output of the second hybrid differential amplifier 320 , therefore V 4a −V 4b represents a sum of outputs of the two hybrid differential amplifiers 310 and 320 .

In an alternative embodiment shown in FIG. 4B , inductors 411 , 412 , 421 , and 422 are connected in a manner so that their respective currents coupled from inductors 311 , 312 , 321 , and 322 can be effectively summed, resulting in currents I 4a and I 4b output to nodes N 411 and N 421 , respectively, that can represent a sum of I 3a , I 3b , I 3c and I 3d . Under the same condition stated earlier (i.e. inductors 311 , 312 , 321 , 322 , 411 , 412 , 421 , and 422 all have the same inductance, and the inductive couplings K 11 , K 12 , K 21 , and K 22 all have a coupling coefficient that is approximately unity), we have

I 4a −I 4b =I 3a +I 3b −I 3c −I 3d   (8)

Note that I 3a +I 3b represents an output of the first hybrid differential amplifier 310 , and I 3d represents an output of the second hybrid differential amplifier 320 , therefore I 4a −I 4b represents a sum of outputs of the two hybrid differential amplifiers 310 and 320 .

In comparison, power combining network 400 A of FIG. 4A is favorable for generating a high output voltage, while power combining network 400 B of FIG. 4B is favorable for generating a high output current.

As illustrated by a flow diagram shown in FIG. 5 , a method comprises: (step 510 ) receiving a first voltage and a second voltage, wherein an AC (alternating current) component of the first voltage is an inversion of an AC component of the second voltage; (step 520 ) converting the first voltage into a first current using a first common-source amplifier comprising a first PMOS (p-channel metal oxide semiconductor) transistor; (step 530 ) converting the second voltage into a second current using a second common-source amplifier comprising a first NMOS (n-channel metal oxide semiconductor) transistor, wherein the first common-source amplifier and the second common-source amplifier share a common source node; (step 540 ) relaying the first current into a third current using a first common-gate amplifier comprising a second PMOS transistor; (step 550 ) relaying the second current into a fourth current using a second common-gate amplifier comprising a second NMOS transistor; and (step 560 ) terminating the third current and the fourth current with a load.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.