Transmitting method including bit group interleaving

This application in a Continuation of application Ser. No. 15/807,144 filed Nov. 8, 2017, which is a Continuation of application Ser. No. 14/715,941 filed May 19, 2015 and patented as U.S. Pat. No. 9,847,794 on Dec. 19, 2017, the disclosures of which are incorporated herein by reference in their entirety.

1. Technical Field

Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes data and transmits the data, and an interleaving method thereof.

2. Description of the Related Art

In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, multi-channel, wideband, and high quality. In particular, as high quality digital televisions and portable multimedia player and portable broadcasting equipments are increasingly used in recent years, there is an increasing demand for methods for supporting various receiving methods of digital broadcasting services.

In order to meet such demand, standard groups are establishing various standards and are providing a variety of services to satisfy users' needs. Therefore, there is a need for a method for providing improved services to users with high decoding and receiving performance.

Exemplary embodiments may overcome the above disadvantages and other disadvantages not described above. However, it is understood that the exemplary embodiment are not required to overcome the disadvantages described above, and may not overcome any of the problems described above.

The exemplary embodiments provide a transmitting apparatus which can map a bit included in a predetermined bit group from among a plurality of bit groups of a low density parity check (LDPC) codeword onto a predetermined bit of a modulation symbol, and transmit the bit, and an interleaving method thereof.

According to an aspect of an exemplary embodiment, there is provided a transmitting apparatus which may include: an encoder configured to generate an LDPC codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Each of the plurality of bit groups may be formed of M number of bits, and M may be a common divisor of N ldpc and K ldpc and may be determined to satisfy Q ldpc =(N ldpc −K ldpc )/M. Q ldpc is a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, N ldpc is a length of the LDPC codeword, and K ldpc is a length of information word bits of the LDPC codeword.

The interleaver may include: a parity interleaver configured to interleave parity bits of the LDPC codeword; a group interleaver configured to divide the parity-interleaved LDPC codeword by the plurality of bit groups and rearrange an order of the plurality of bit groups in bit group wise; and a block interleaver configured to interleave the plurality of bit groups the order of which is rearranged.

The group interleaver may be configured to rearrange the order of the plurality of bit groups in bit group wise based on Equation 21.

π(j) in Equation 21 may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

When the LDPC codeword has a length of 16200, the modulation method is QPSK, and the code rate is 13/15, π(j) in Equation 21 may be defined as in Table 36.

The block interleaver may be configured to interleave by writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

The block interleaver may be configured to serially write, in the plurality of columns, at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then divide and write the other bit groups in an area which remains after the at least some bit groups are written in the plurality of columns in bit group wise.

According to an aspect of another exemplary embodiment, there is provided an interleaving method of a transmitting apparatus. The method may include: generating an LDPC codeword by LDPC encoding based on a parity check matrix; interleaving the LDPC codeword; and mapping the interleaved LDPC codeword onto a modulation symbol, wherein the mapping includes mapping a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Each of the plurality of bit groups may be formed of M number of bits, and M may be a common divisor of N ldpc and K ldpc and may be determined to satisfy Q ldpc =(N ldpc −K ldpc )/M. Q ldpc is a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, N ldpc is a length of the LDPC codeword, and K ldpc is a length of information word bits of the LDPC codeword.

The interleaving may include: interleaving parity bits of the LDPC codeword; dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging an order of the plurality of bit groups in bit group wise; and interleaving the plurality of bit groups the order of which is rearranged.

The rearranging in bit group wise may include rearranging the order of the plurality of bit groups in bit group wise based on Equation 21.

π(j) in Equation 21 may be determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

When the LDPC codeword has a length of 16200, the modulation method is QPSK, and the code rate is 13/15, π(j) in Equation 21 may be defined as in Table 36.

The interleaving the plurality of bit groups may include interleaving by writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

The interleaving the plurality of bit groups may include serially writing, in the plurality of columns, at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then dividing and writing the other bit groups in an area which remains after the at least some bit groups are written in the plurality of columns in bit group wise.

According to various exemplary embodiments, improved decoding and receiving performance can be provided.

The above and/or other aspects will be more apparent by describing in detail exemplary embodiments, with reference to the accompanying drawings, in which:

FIGS. 1A to 12 are views to illustrate a transmitting apparatus according to exemplary embodiments;

FIGS. 13 to 18 are views to illustrate a receiving apparatus according to exemplary embodiments;

FIG. 19 is a block diagram to illustrate a configuration of a transmitting apparatus according to an exemplary embodiment;

FIGS. 20 to 22 illustrate a configuration of a parity check matrix according to various exemplary embodiments;

FIG. 23 is a block diagram to illustrate a configuration of an interleaver according to an exemplary embodiment;

FIGS. 24 to 26 illustrate an interleaving method according to exemplary embodiments;

FIGS. 27 to 33 illustrate an interleaving method of a block interleaver according to exemplary embodiments;

FIG. 34 illustrates an operation of a demultiplexer according to an exemplary embodiment;

FIGS. 35 to 37 illustrate a method for extracting interleaving parameters according to exemplary embodiments;

FIG. 38 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment;

FIG. 39 is a block diagram to illustrate a configuration of a deinterleaver according to an exemplary embodiment;

FIG. 40 illustrates a deinterleaving method of a block deinterleaver according to an exemplary embodiment;

FIG. 41 is a flowchart to illustrate an interleaving method according to an exemplary embodiment;

FIG. 42 is a block diagram illustrating a configuration of a receiving apparatus according to an exemplary embodiment;

FIG. 43 is a block diagram illustrating a demodulator according to an exemplary embodiment; and

FIG. 44 is a flowchart provided to illustrate an operation of a receiving apparatus from a moment when a user selects a service until the selected service is reproduced, according to an exemplary embodiment.

Hereinafter, various exemplary embodiments will be described in greater detail with reference to the accompanying drawings.

In the following description, same reference numerals are used for the same elements when they are depicted in different drawings. The matters defined in the description, such as detailed construction and elements, are provided to assist in a comprehensive understanding of the exemplary embodiments. Thus, it is apparent that the exemplary embodiments can be carried out without those specifically defined matters. Also, functions or elements known in the related art are not described in detail since they would obscure the exemplary embodiments with unnecessary detail.

FIG. 1A is provided to explain transmitting apparatus according to an exemplary embodiment.

According to FIG. 1A , a transmitting apparatus 10000 according to an exemplary embodiment may include an Input Formatting Block(or part) 11000 , 11000 - 1 , a BIT Interleaved and Coded Modulation (BICM) block 12000 , 12000 - 1 , a Framing/Interleaving block 13000 , 13000 - 1 and a Waveform Generation block 14000 , 14000 - 1 .

The transmitting apparatus 10000 according to an exemplary embodiment illustrated in FIG. 1A includes normative blocks shown by solid lines and informative blocks shown by dotted lines. Here, the blocks shown by solid lines are normal blocks, and the blocks shown by dotted lines are blocks which may be used when implementing an informative MIMO.

The Input Formatting block 11000 , 11000 - 1 generates a baseband frame (BBFRAME) from an input stream of data to be serviced. Herein, the input stream may be a transport stream (TS), Internet protocol (IP) stream, a generic stream (GS), a generic stream encapsulation (GSE), etc.

The BICM block 12000 , 12000 - 1 determines a forward error correction (FEC) coding rate and a constellation order depending on a region where the data to be serviced will be transmitted (e.g., a fixed PHY frame or mobile PHY frame), and then, performs encoding. Signaling information on the data to be serviced may be encoded through a separate BICM encoder (not illustrated) or encoded by sharing the BICM encoder 12000 , 12000 - 1 with the data to be serviced, depending on a system implementation.

The Framing/Interleaving block 13000 , 13000 - 1 combines time interleaved data with signaling information to generate a transmission frame.

The Waveform Generation block 14000 , 14000 - 1 generates an OFDM signal in the time domain on the generated transmission frame, modulates the generated OFDM signal to a radio frequency (RF) signal and transmits the modulated RF signal to a receiver.

FIGS. 1B and 1C are provided to explain methods of multiplexing according to an exemplary embodiment.

FIG. 1B illustrates a block diagram to implement a Time Division Multiplexing according to an exemplary embodiment.

In the TDM system architecture, there are four main blocks(or parts): the Input Formatting block 11000 , the BICM block 12000 , the Framing/Interleaving block 13000 , and the Waveform Generation block 14000 .

Data is input and formatted in the Input Formatting block, and forward error correction applied and mapped to constellations in the BICM block 12000 . Interleaving, both time and frequency, and frame creation done in the Framing/Interleaving block 13000 . Subsequently, the output waveform is created in the Waveform Generation block 14000 .

FIG. 2B illustrates a block diagram to implement a Layered Division Multiplexing (LDM) according to another exemplary embodiment.

In the LDM system architecture, there are several different blocks compared with the TDM system architecture. Specifically, there are two separate Input Formatting blocks 11000 , 11000 - 1 and BICM blocks 12000 , 12000 - 1 , one for each of the layers in LDM. These are combined before the Framing/Interleaving block 13000 in the LDM Injection block. The Waveform Generation block 14000 is similar to TDM.

FIG. 2 is a block diagram which illustrates detailed configuration of the Input Formatting block illustrated in FIG. 1A .

As illustrated in FIG. 2 , the Input Formatting block 11000 consists of three blocks which control packets distributed into PLPs. Specifically, the Input Formatting block 11000 includes a packet encapsulation and compression block 11100 , a baseband framing block 11200 and a scheduler block 11300 .

Input data packets input to the Input Formatting block 11000 can consist of various types, but at the encapsulation operation these different types of packets become generic packets which configure baseband frames. Here, the format of generic packets is variable. It is possible to easily extract the length of the generic packet from the packet itself without additional information. The maximum length of the generic packet is 64 kB. The maximum length of the generic packet, including header, is four bytes. Generic packets must be of integer byte length.

The scheduler 11200 receives an input stream of encapsulated generic packets and forms them into physical layer pipes (PLPs), in the form of baseband frames. In the above-mentioned TDM system there may be only one PLP, called single PLP or S-PLP, or there may be multiple PLPs, called M-PLP. One service cannot use more than four PLPs. In the case of an LDM system consisting of two layers, two PLPs are used, one for each layer.

The scheduler 11200 receives encapsulated input packet streams and directs how these packets are allocated to physical layer resources. Specifically, the scheduler 11200 directs how the baseband framing block will output baseband frames.

The functional assets of the Scheduler 11200 are defined by data size(s) and time(s). The physical layer can deliver portions of data at these discrete times. The scheduler 11200 uses the inputs and information including encapsulated data packets, quality of service metadata for the encapsulated data packets, a system buffer model, constraints and configuration from system management, and creates a conforming solution in terms of configuration of the physical layer parameters. The corresponding solution is subject to the configuration and control parameters and the aggregate spectrum available.

Meanwhile, the operation of the Scheduler 11200 is constrained by combination of dynamic, quasi-static, and static configurations. The definition of these constraints is left to implementation.

In addition, for each service a maximum of four PLPs shall be used. Multiple services consisting of multiple time interleaving blocks may be constructed, up to a total maximum of 64 PLPs for bandwidths of 6, 7 or 8 MHz. The baseband framing block 11300 , as illustrated in FIG. 3A , consists of three blocks, baseband frame construction 3100 , 3100 - 1 , . . . 3100 - n , baseband frame header construction block 3200 , 3200 - 1 , . . . 3200 - n , and the baseband frame scrambling block 3300 , 3300 - 1 , . . . 3300 - n . In a M-PLP operation, the baseband framing block creates multiple PLPs as necessary.

A baseband frame 3500 , as illustrated in FIG. 3B , consists of a baseband frame header 3500 - 1 and payload 3500 - 2 consisting of generic packets. Baseband frames have fixed length K payload . Generic packets 3610 - 3650 shall be mapped to baseband frames 3500 in order. If generic packets 3610 - 3650 do not completely fit within a baseband frame, packets are split between the current baseband frame and the next baseband frame. Packet splits shall be in byte units only.

The baseband frame header construction block 3200 , 3200 - 1 , . . . 3200 - n configures the baseband frame header. The baseband frame header 3500 - 1 , as illustrated in FIG. 3 B, is composed of three parts, including the base header 3710 , the optional header(or option field 3720 ) and the extension field 3730 . Here, the base header 3710 appears in every baseband frame, and the optional header 3720 and the extension field 3730 may not be present in every time.

The main feature of the base header 3710 is to provide a pointer including an offset value in bytes as an initiation of the next generic packet within the baseband frame. When the generic packet initiates the baseband frame, the pointer value becomes zero. If there is no generic packet which is initiated within the baseband frame, the pointer value is 8191, and a 2-byte base header may be used.

The extension field (or extension header) 3730 may be used later, for example, for the baseband frame packet counter, baseband frame time stamping, and additional signaling, etc.

The baseband frame scrambling block 3300 , 3300 - 1 , . . . 3300 - n scrambles the baseband frame.

In order to ensure that the payload data when mapped to constellations does not always map to the same point, such as when the payload mapped to constellations consists of a repetitive sequence, the payload data shall always be scrambled before forward error correction encoding.

The scrambling sequences shall be generated by a 16-bit shift register that has 9 feedback taps. Eight of the shift register outputs are selected as a fixed randomizing byte, where each bit from t his byte is used to individually XOR the corresponding input data. The data bits are XORed MSB to MSB and so on until LSB to LSB. The generator polynomial is G(x)=I+X+X 3 +X 6 +X 7 +X 11 +X 12 +X 13 +X 16 .

FIG. 4 illustrates a shift register of a PRBS encoder for scrambling a baseband according to an exemplary embodiment, wherein loading of the sequence into the PRBS register, as illustrated in FIG. 4 and shall be initiated at the start of every baseband frame.

FIG. 5 is a block diagram provided to explain detailed configuration of the BICM block illustrated in FIG. 1A .

As illustrated in FIG. 5 , the BICM block includes the FEC block 14100 , 14100 - 1 , . . . , 14100 - n , Bit Interleaver block 14200 , 14200 - 1 , . . . , 14200 - n and Mapper blocks 14300 , 14300 - 1 , . . . , 14300 - n.

The input to the FEC block 1400 , 14100 - 1 , . . . , 14100 - n is a Baseband frame, of length K payload , and the output from the FEC block is a FEC frame. The FEC block 14100 , 14100 - 1 , . . . , 14100 - n is implemented by concatenation of an outer code and an inner code with the information part. The FEC frame has length N inner . There are two different lengths of LDPC code defined: N inner =64800 bits and N inner =16200 bits

The outer code is realized as one of either Bose, Ray-Chaudhuri and Hocquenghem (BCH) outer code, a Cyclic Redundancy Check (CRC) or other code. The inner code is realized as a Low Density Parity Check (LDPC) code. Both BCH and LDPC FEC codes are systematic codes where the information part I contained within the codeword. The resulting codeword is thus a concatenation of information or payload part, BCH or CRC parities and LDPC parities, as shown in FIG. 6A .

The use of LDPC code is mandatory and is used to provide the redundancy needed for the code detection. There are two different LDPC structures that are defined, these are called Type A and Type B. Type A has a code structure that shows better performance at low code rates while Type B code structure shows better performance at high code rates. In general N inner =64800 bit codes are expected to be employed. However, for applications where latency is critical, or a simpler encoder/decoder structure is preferred, N inner =16200 bit codes may also be used.

The outer code and CRC consist of adding M outer bits to the input baseband frame. The outer BCH code is used to lower the inherent LDPC error floor by correcting a predefined number of bit errors. When using BCH codes the length of M outer is 192 bits (N inner =64800 bit codes) and 168 bits (for N inner =16200 bit codes). When using CRC the length of M outer is 32 bits. When neither BCH nor CRC are used the length of M outer is zero. The outer code may be omitted if it is determined that the error correcting capability of the inner code is sufficient for the application. When there is no outer code the structure of the FEC frame is as shown in FIG. 6B .

FIG. 7 is a block diagram provided to explain detailed configuration of the Bit Interleaver block illustrated in FIG. 6 .

The LDPC codeword of the LDPC encoder, i.e., a FEC Frame, shall be bit interleaved by a Bit Interleaver block 14200 . The Bit Interleaver block 14200 includes a parity interleaver 14210 , a group-wise interleaver 14220 and a block interleaver 14230 . Here, the parity interleaver is not used for Type A and is only used for Type B codes.

The parity interleaver 14210 converts the staircase structure of the parity-part of the LDPC parity-check matrix into a quasi-cyclic structure similar to the information-part of the matrix.

Meanwhile, the parity interleaved LDPC coded bits are split into N group =N inner /360 bit groups, and the group-wise interleaver 14220 rearranges the bit groups.

The block interleaver 14230 block interleaves the group-wise interleaved LDPC codeword.

Specifically, the block interleaver 14230 divides a plurality of columns into part 1 and part 2 based on the number of columns of the block interleaver 14230 and the number of bits of the bit groups. In addition, the block interleaver 14230 writes the bits into each column configuring part 1 column wise, and subsequently writes the bits into each column configuring part 2 column wise, and then reads out row wise the bits written in each column.

In this case, the bits constituting the bit groups in the part 1 may be written into the same column, and the bits constituting the bit groups in the part 2 may be written into at least two columns.

Back to FIG. 5 , the Mapper block 14300 , 14300 - 1 , . . . , 14300 - n maps FEC encoded and bit interleaved bits to complex valued quadrature amplitude modulation (QAM) constellation points. For the highest robustness level, quaternary phase shift keying (QPSK) is used. For higher order constellations (16-QAM up to 4096-QAM), non-uniform constellations are defined and the constellations are customized for each code rate.

Each FEC frame shall be mapped to a FEC block by first de-multiplexing the input bits into parallel data cell words and then mapping these cell words into constellation values.

FIG. 8 is a block diagram provided to explain detailed configuration of a Framing/Interleaving block illustrated in FIG. 1A .

As illustrated in FIG. 8 , the Framing/Interleaving block 14300 includes a time interleaving block 14310 , a framing block 14320 and a frequency interleaving block 14330 .

The input to the time interleaving block 14310 and the framing block 14320 may consist of M-PLPs however the output of the framing block 14320 is OFDM symbols, which are arranged in frames. The frequency interleaver included in the frequency interleaving block 14330 operates an OFDM symbols.

The time interleaver (TI) configuration included in the time interleaving block 14310 depends on the number of PLPs used. When there is only a single PLP or when LDM is used, a sheer convolutional interleaver is used, while for multiple PLP a hybrid interleaver consisting of a cell interleaver, a block interleaver and a convolutional interleaver is used. The input to the time interleaving block 14310 is a stream of cells output from the mapper block ( FIG. 5, 14300, 14300-1 , . . . , 14300 - n ), and the output of the time interleaving block 14310 is also a stream of time-interleaved cells.

FIG. 9A illustrates the time interleaving block for a single PLP (S-PLP), and it consists of a convolutional interleaver only.

FIG. 9B illustrates the time interleaving block for a plurality of PLPs (M-PLP), and it can be divided in several sub-blocks as illustrated.

The framing block 14320 maps the interleaved frames onto at least one transmitter frame. The framing block 14320 , specifically, receives inputs (e.g. data cell) from at least one physical layer pipes and outputs symbols.

In addition, the framing block 14320 creates at least one special symbol known as preamble symbols. These symbols undergo the same processing in the waveform block mentioned later.

FIG. 10 is a view illustrating an example of a transmission frame according to an exemplary embodiment.

As illustrated in FIG. 10 , the transmission frame consists of three parts, the bootstrap, preamble and data payload. Each of the three parts consists of at least one symbol.

Meanwhile, the purpose of the frequency interleaving block 14330 is to ensure that sustained interference in one part of the spectrum will not degrade the performance of a particular PLP disproportionately compared to other PLPs. The frequency interleaver 14330 , operating on the all the data cells of one OFDM symbol, maps the data cells from the framing block 14320 onto the N data carriers.

FIG. 11 is a block diagram provided to explain detailed configuration of a Waveform Generation block illustrated in FIG. 1A .

As illustrated in FIG. 11 , the Waveform Generation block 14000 includes a pilot inserting block 14100 , a MISO block 14200 , an IFFT block 14300 , a PAPR block 14400 , a GI inserting block 14500 and a bootstrap block 14600 .

The pilot inserting block 14100 inserts a pilot to various cells within the OFDM frame.

Various cells within the OFDM frame are modulated with reference information whose transmitted value is known to the receiver.

Cells containing the reference information are transmitted at a boosted power level. The cells are called scattered, continual, edge, preamble or frame-closing pilot cells. The value of the pilot information is derived from a reference sequence, which is a series of values, one for each transmitted carrier on any given symbol.

The pilots can be used for frame synchronization, frequency synchronization, time synchronization, channel estimation, transmission mode identification and can also be used to follow the phase noise.

The pilots are modulated according to reference information, and the reference sequence is applied to all the pilots (e.g. scattered, continual edge, preamble and frame closing pilots) in every symbol including preamble and the frame-closing symbol of the frame.

The reference information, taken from the reference sequence, is transmitted in scattered pilot cells in every symbol except the preamble and the frame-closing symbol of the frame.

In addition to the scattered pilots described above, a number of continual pilots are inserted in every symbol of the frame except for Preamble and the frame-closing symbol. The number and location of continual pilots depends on both the FFT size and scattered pilot pattern in use.

The MISO block 14200 applies a MISO processing.

The Transmit Diversity Code Filter Set is a MISO pre-distortion technique that artificially decorrelates signals from multiple transmitters in a Single Frequency Network in order to minimize potential destructive interference. Linear frequency domain filters are used so that the compensation in the receiver can be implemented as part of the equalizer process. The filter design is based on creating all-pass filters with minimized cross-correlation over all filter pairs under the constraints of the number of transmitters M∈{2,3,4} and the time domain span of the filters N∈{64,256}. The longer time domain span filters will increase the decorrelation level, but the effective guard interval length will be decreased by the filter time domain span and this should be taken into consideration when choosing a filter set for a particular network topology.

The IFFT block 14300 specifies the OFDM structure to use for each transmission mode. The transmitted signal is organized in frames. Each frame has a duration of T F , and consists of L F OFDM symbols. N frames constitute one super-frame. Each symbol is constituted by a set of K total carriers transmitted with a duration T S . Each symbol is composed of a useful part with duration T U and a guard interval with a duration Δ. The guard interval consists of a cyclic continuation of the useful part, T U , and is inserted before it.

The PAPR block 14400 applies the Peak to Average Power Reduction technique.

The GI inserting block 14500 inserts the guard interval into each frame.

The bootstrap block 14600 prefixes the bootstrap signal to the front of each frame.

FIG. 12 is a block diagram provided to explain a configuration of signaling information according to an exemplary embodiment.

The input processing block 11000 includes a scheduler 11200 . The BICM block 15000 includes an L1 signaling generator 15100 , an FEC encoder 15200 - 1 and 15200 - 2 , a bit interleaver 15300 - 2 , a demux 15400 - 2 , constellation mappers 15500 - 1 and 15500 - 2 . The L1 signaling generator 15100 may be included in the input processing block 11000 , according to an exemplary embodiment.

An n number of service data are mapped to a PLP0 to a PLPn respectively. The scheduler 11200 determines a position, modulation and coding rate for each PLP in order to map a plurality of PLPs to a physical layer of T2. In other words, the scheduler 11200 generates L1 signaling information. The scheduler 11200 may output dynamic field information among L1 post signaling information of a current frame, using the framing/Interleaving block 13000 ( FIG. 1 ) which may be referred to as a frame builder. Further, the scheduler 11200 may transmit the L1 signaling information to the BICM block 15000 . The L1 signaling information includes L1 pre signaling information and L1 post signaling information.

The L1 signaling generator 15100 may differentiate the L1 pre signaling information from the L1 post signaling information to output them. The FEC encoders 15200 - 1 and 15200 - 2 perform respective encoding operations which include shortening and puncturing for the L1 pre signaling information and the L1 post signaling information. The bit interleaver 15300 - 2 performs interleaving by bit for the encoded L1 post signaling information. The demux 15400 - 2 controls robustness of bits by modifying an order of bits constituting cells and outputs the cells which include bits. Two constellation mappers 15500 - 1 and 15500 - 2 map the L1 pre signaling information and the L1 post signaling information to constellations, respectively. The L1 pre signaling information and the L1 post signaling information processed through the above described processes are output to be included in each frame by the Framing/Interleaving block 13000 ( FIG. 1 ).

FIG. 13 illustrates a structure of an receiving apparatus according to an embodiment of the present invention.

The apparatus 20000 for receiving broadcast signals according to an embodiment of the present invention can correspond to the apparatus 10000 for transmitting broadcast signals, described with reference to FIG. 1 . The apparatus 20000 for receiving broadcast signals according to an embodiment of the present invention can include a synchronization & demodulation module 21000 , a frame parsing module 22000 , a demapping & decoding module 23000 , an output processor 24000 and a signaling decoding module 25000 . A description will be given of operation of each module of the apparatus 20000 for receiving broadcast signals.

The synchronization & demodulation module 21000 can receive input signals through m Rx antennas, perform signal detection and synchronization with respect to a system corresponding to the apparatus 20000 for receiving broadcast signals and carry out demodulation corresponding to a reverse procedure of the procedure performed by the apparatus 10000 for transmitting broadcast signals.

The frame parsing module 22000 can parse input signal frames and extract data through which a service selected by a user is transmitted. If the apparatus 10000 for transmitting broadcast signals performs interleaving, the frame parsing module 22000 can carry out deinterleaving corresponding to a reverse procedure of interleaving. In this case, the positions of a signal and data that need to be extracted can be obtained by decoding data output from the signaling decoding module 25200 to restore scheduling information generated by the apparatus 10000 for transmitting broadcast signals.

The demapping & decoding module 23000 can convert the input signals into bit domain data and then deinterleave the same as necessary. The demapping & decoding module 23000 can perform demapping for mapping applied for transmission efficiency and correct an error generated on a transmission channel through decoding. In this case, the demapping & decoding module 23000 can obtain transmission parameters necessary for demapping and decoding by decoding the data output from the signaling decoding module 25000 .

The output processor 24000 can perform reverse procedures of various compression/signal processing procedures which are applied by the apparatus 10000 for transmitting broadcast signals to improve transmission efficiency. In this case, the output processor 24000 can acquire necessary control information from data output from the signaling decoding module 25000 . The output of the output processor 24000 corresponds to a signal input to the apparatus 10000 for transmitting broadcast signals and may be MPEG-TSs, IP streams (v4 or v6) and generic streams.

The signaling decoding module 25000 can obtain PLS information from the signal demodulated by the synchronization & demodulation module 21000 . As described above, the frame parsing module 22000 , demapping & decoding module 23000 and output processor 24000 can execute functions thereof using the data output from the signaling decoding module 25000 .

FIG. 14 illustrates a synchronization & demodulation module according to an embodiment of the present invention.

As shown in FIG. 14 , the synchronization & demodulation module 21000 according to an embodiment of the present invention corresponds to a synchronization & demodulation module of an apparatus 20000 for receiving broadcast signals using m Rx antennas and can include m processing blocks for demodulating signals respectively input through m paths. The m processing blocks can perform the same processing procedure. A description will be given of operation of the first processing block 21000 from among the m processing blocks.

The first processing block 21000 can include a tuner 21100 , an ADC block 21200 , a preamble detector 21300 , a guard sequence detector 21400 , a waveform transform block 21500 , a time/frequency synchronization block 21600 , a reference signal detector 21700 , a channel equalizer 21800 and an inverse waveform transform block 21900 .

The tuner 21100 can select a desired frequency band, compensate for the magnitude of a received signal and output the compensated signal to the ADC block 21200 .

The ADC block 21200 can convert the signal output from the tuner 21100 into a digital signal.

The preamble detector 21300 can detect a preamble (or preamble signal or preamble symbol) in order to check whether or not the digital signal is a signal of the system corresponding to the apparatus 20000 for receiving broadcast signals. In this case, the preamble detector 21300 can decode basic transmission parameters received through the preamble.

The guard sequence detector 21400 can detect a guard sequence in the digital signal. The time/frequency synchronization block 21600 can perform time/frequency synchronization using the detected guard sequence and the channel equalizer 21800 can estimate a channel through a received/restored sequence using the detected guard sequence.

The waveform transform block 21500 can perform a reverse operation of inverse waveform transform when the apparatus 10000 for transmitting broadcast signals has performed inverse waveform transform. When the broadcast transmission/reception system according to one embodiment of the present invention is a multi-carrier system, the waveform transform block 21500 can perform FFT. Furthermore, when the broadcast transmission/reception system according to an embodiment of the present invention is a single carrier system, the waveform transform block 21500 may not be used if a received time domain signal is processed in the frequency domain or processed in the time domain.

The time/frequency synchronization block 21600 can receive output data of the preamble detector 21300 , guard sequence detector 21400 and reference signal detector 21700 and perform time synchronization and carrier frequency synchronization including guard sequence detection and block window positioning on a detected signal. Here, the time/frequency synchronization block 21600 can feed back the output signal of the waveform transform block 21500 for frequency synchronization.

The reference signal detector 21700 can detect a received reference signal. Accordingly, the apparatus 20000 for receiving broadcast signals according to an embodiment of the present invention can perform synchronization or channel estimation.

The channel equalizer 21800 can estimate a transmission channel from each Tx antenna to each Rx antenna from the guard sequence or reference signal and perform channel equalization for received data using the estimated channel.

The inverse waveform transform block 21900 may restore the original received data domain when the waveform transform block 21500 performs waveform transform for efficient synchronization and channel estimation/equalization. If the broadcast transmission/reception system according to an embodiment of the present invention is a single carrier system, the waveform transform block 21500 can perform FFT in order to carry out synchronization/channel estimation/equalization in the frequency domain and the inverse waveform transform block 21900 can perform IFFT on the channel-equalized signal to restore transmitted data symbols. If the broadcast transmission/reception system according to an embodiment of the present invention is a multi-carrier system, the inverse waveform transform block 21900 may not be used.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.

FIG. 15 illustrates a frame parsing module according to an embodiment of the present invention.

As shown in FIG. 15 , the frame parsing module 22000 according to an embodiment of the present invention can include at least one block interleaver 22100 and at least one cell demapper 22200 .

The block interleaver 22100 can deinterleave data input through data paths of the m Rx antennas and processed by the synchronization & demodulation module 21000 on a signal block basis. In this case, if the apparatus 10000 for transmitting broadcast signals performs pair-wise interleaving, the block interleaver 22100 can process two consecutive pieces of data as a pair for each input path. Accordingly, the block interleaver 22100 can output two consecutive pieces of data even when deinterleaving has been performed. Furthermore, the block interleaver 22100 can perform a reverse operation of the interleaving operation performed by the apparatus 10000 for transmitting broadcast signals to output data in the original order.

The cell demapper 22200 can extract cells corresponding to common data, cells corresponding to data pipes and cells corresponding to PLS data from received signal frames. The cell demapper 22200 can merge data distributed and transmitted and output the same as a stream as necessary. When two consecutive pieces of cell input data are processed as a pair and mapped in the apparatus 10000 for transmitting broadcast signals, the cell demapper 22200 can perform pair-wise cell demapping for processing two consecutive input cells as one unit as a reverse procedure of the mapping operation of the apparatus 10000 for transmitting broadcast signals.

In addition, the cell demapper 22200 can extract PLS signaling data received through the current frame as PLS-pre & PLS-post data and output the PLS-pre & PLS-post data.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.

FIG. 16 illustrates a demapping & decoding module according to an embodiment of the present invention.

The demapping & decoding module 23000 shown in FIG. 16 can perform a reverse operation of the operation of the bit interleaved and coded & modulation module illustrated in FIG. 1 .

The bit interleaved and coded & modulation module of the apparatus 10000 for transmitting broadcast signals according to an embodiment of the present invention can process input data pipes by independently applying SISO, MISO and MIMO thereto for respective paths, as described above. Accordingly, the demapping & decoding module 23000 illustrated in FIG. 16 can include blocks for processing data output from the frame parsing module according to SISO, MISO and MIMO in response to the apparatus 10000 for transmitting broadcast signals.

As shown in FIG. 16 , the demapping & decoding module 23000 according to an embodiment of the present invention can include a first block 23100 for SISO, a second block 23200 for MISO, a third block 23300 for MIMO and a fourth block 23400 for processing the PLS-pre/PLS-post information. The demapping & decoding module 23000 shown in FIG. 16 is exemplary and may include only the first block 23100 and the fourth block 23400 , only the second block 23200 and the fourth block 23400 or only the third block 23300 and the fourth block 23400 according to design. That is, the demapping & decoding module 23000 can include blocks for processing data pipes equally or differently according to design.

A description will be given of each block of the demapping & decoding module 23000 .

The first block 23100 processes an input data pipe according to SISO and can include a time deinterleaver block 23110 , a cell deinterleaver block 23120 , a constellation demapper block 23130 , a cell-to-bit mux block 23140 , a bit deinterleaver block 23150 and an FEC decoder block 23160 .

The time deinterleaver block 23110 can perform a reverse process of the process performed by the time interleaving block 14310 illustrated in FIG. 8 . That is, the time deinterleaver block 23110 can deinterleave input symbols interleaved in the time domain into original positions thereof.

The cell deinterleaver block 23120 can perform a reverse process of the process performed by the cell interleaver block illustrated in FIG. 9 a . That is, the cell deinterleaver block 23120 can deinterleave positions of cells spread in one FEC block into original positions thereof. The cell deinterleaver block 23120 may be omitted.

The constellation demapper block 23130 can perform a reverse process of the process performed by the mapper 12300 illustrated in FIG. 5 . That is, the constellation demapper block 23130 can demap a symbol domain input signal to bit domain data. In addition, the constellation demapper block 23130 may perform hard decision and output decided bit data. Furthermore, the constellation demapper block 23130 may output a log-likelihood ratio (LLR) of each bit, which corresponds to a soft decision value or probability value. If the apparatus 10000 for transmitting broadcast signals applies a rotated constellation in order to obtain additional diversity gain, the constellation demapper block 23130 can perform 2-dimensional LLR demapping corresponding to the rotated constellation. Here, the constellation demapper block 23130 can calculate the LLR such that a delay applied by the apparatus 10000 for transmitting broadcast signals to the I or Q component can be compensated.

The cell-to-bit mux block 23140 can perform a reverse process of the process performed by the mapper 12300 illustrated in FIG. 5 . That is, the cell-to-bit mux block 23140 can restore bit data mapped to the original bit streams.

The bit deinterleaver block 23150 can perform a reverse process of the process performed by the bit interleaver 12200 illustrated in FIG. 5 . That is, the bit deinterleaver block 23150 can deinterleave the bit streams output from the cell-to-bit mux block 23140 in the original order.

The FEC decoder block 23460 can perform a reverse process of the process performed by the FEC encoder 12100 illustrated in FIG. 5 . That is, the FEC decoder block 23460 can correct an error generated on a transmission channel by performing LDPC decoding and BCH decoding.

The second block 23200 processes an input data pipe according to MISO and can include the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block, bit deinterleaver block and FEC decoder block in the same manner as the first block 23100 , as shown in FIG. 16 . However, the second block 23200 is distinguished from the first block 23100 in that the second block 23200 further includes a MISO decoding block 23210 . The second block 23200 performs the same procedure including time deinterleaving operation to outputting operation as the first block 23100 and thus description of the corresponding blocks is omitted.

The MISO decoding block 11110 can perform a reverse operation of the operation of the MISO processing in the apparatus 10000 for transmitting broadcast signals. If the broadcast transmission/reception system according to an embodiment of the present invention uses STBC, the MISO decoding block 11110 can perform Alamouti decoding.

The third block 23300 processes an input data pipe according to MIMO and can include the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block, bit deinterleaver block and FEC decoder block in the same manner as the second block 23200 , as shown in FIG. 16 . However, the third block 23300 is distinguished from the second block 23200 in that the third block 23300 further includes a MIMO decoding block 23310 . The basic roles of the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block and bit deinterleaver block included in the third block 23300 are identical to those of the corresponding blocks included in the first and second blocks 23100 and 23200 although functions thereof may be different from the first and second blocks 23100 and 23200 .

The MIMO decoding block 23310 can receive output data of the cell deinterleaver for input signals of the m Rx antennas and perform MIMO decoding as a reverse operation of the operation of the MIMO processing in the apparatus 10000 for transmitting broadcast signals. The MIMO decoding block 23310 can perform maximum likelihood decoding to obtain optimal decoding performance or carry out sphere decoding with reduced complexity. Otherwise, the MIMO decoding block 23310 can achieve improved decoding performance by performing MMSE detection or carrying out iterative decoding with MMSE detection.

The fourth block 23400 processes the PLS-pre/PLS-post information and can perform SISO or MISO decoding.

The basic roles of the time deinterleaver block, cell deinterleaver block, constellation demapper block, cell-to-bit mux block and bit deinterleaver block included in the fourth block 23400 are identical to those of the corresponding blocks of the first, second and third blocks 23100 , 23200 and 23300 although functions thereof may be different from the first, second and third blocks 23100 , 23200 and 23300 .

The shortened/punctured FEC decoder 23410 can perform de-shortening and de-puncturing on data shortened/punctured according to PLS data length and then carry out FEC decoding thereon. In this case, the FEC decoder used for data pipes can also be used for PLS. Accordingly, additional FEC decoder hardware for the PLS only is not needed and thus system design is simplified and efficient coding is achieved.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.

The demapping & decoding module according to an embodiment of the present invention can output data pipes and PLS information processed for the respective paths to the output processor, as illustrated in FIG. 16 .

FIGS. 17 and 18 illustrate output processors according to embodiments of the present invention.

FIG. 17 illustrates an output processor 24000 according to an embodiment of the present invention. The output processor 24000 illustrated in FIG. 17 receives a single data pipe output from the demapping & decoding module and outputs a single output stream.

The output processor 24000 shown in FIG. 17 can include a BB scrambler block 24100 , a padding removal block 24200 , a CRC-8 decoder block 24300 and a BB frame processor block 24400 .

The BB scrambler block 24100 can descramble an input bit stream by generating the same PRBS as that used in the apparatus for transmitting broadcast signals for the input bit stream and carrying out an XOR operation on the PRBS and the bit stream.

The padding removal block 24200 can remove padding bits inserted by the apparatus for transmitting broadcast signals as necessary.

The CRC-8 decoder block 24300 can check a block error by performing CRC decoding on the bit stream received from the padding removal block 24200 .

The BB frame processor block 24400 can decode information transmitted through a BB frame header and restore MPEG-TSs, IP streams (v4 or v6) or generic streams using the decoded information.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.

FIG. 18 illustrates an output processor according to another embodiment of the present invention. The output processor 24000 shown in FIG. 18 receives multiple data pipes output from the demapping & decoding module. Decoding multiple data pipes can include a process of merging common data commonly applicable to a plurality of data pipes and data pipes related thereto and decoding the same or a process of simultaneously decoding a plurality of services or service components (including a scalable video service) by the apparatus for receiving broadcast signals.

The output processor 24000 shown in FIG. 18 can include a BB descrambler block, a padding removal block, a CRC-8 decoder block and a BB frame processor block as the output processor illustrated in FIG. 17 . The basic roles of these blocks correspond to those of the blocks described with reference to FIG. 17 although operations thereof may differ from those of the blocks illustrated in FIG. 17 .

A de-jitter buffer block 24500 included in the output processor shown in FIG. 18 can compensate for a delay, inserted by the apparatus for transmitting broadcast signals for synchronization of multiple data pipes, according to a restored TTO (time to output) parameter.

A null packet insertion block 24600 can restore a null packet removed from a stream with reference to a restored DNP (deleted null packet) and output common data.

A TS clock regeneration block 24700 can restore time synchronization of output packets based on ISCR (input stream time reference) information.

A TS recombining block 24800 can recombine the common data and data pipes related thereto, output from the null packet insertion block 24600 , to restore the original MPEG-TSs, IP streams (v4 or v6) or generic streams. The TTO, DNT and ISCR information can be obtained through the BB frame header.

An in-band signaling decoding block 24900 can decode and output in-band physical layer signaling information transmitted through a padding bit field in each FEC frame of a data pipe.

The output processor shown in FIG. 18 can BB-descramble the PLS-pre information and PLS-post information respectively input through a PLS-pre path and a PLS-post path and decode the descrambled data to restore the original PLS data. The restored PLS data is delivered to a system controller included in the apparatus for receiving broadcast signals. The system controller can provide parameters necessary for the synchronization & demodulation module, frame parsing module, demapping & decoding module and output processor module of the apparatus for receiving broadcast signals.

The above-described blocks may be omitted or replaced by blocks having similar r identical functions according to design.

FIG. 19 is a block diagram to illustrate a configuration of a transmitting apparatus according to an exemplary embodiment. Referring to FIG. 19 , the transmitting apparatus 100 includes an encoder 110 , an interleaver 120 , and a modulator 130 (or a constellation mapper).

The encoder 110 generates a low density parity check (LDPC) codeword by performing LDPC encoding based on a parity check matrix. To achieve this, the encoder 110 may include an LDPC encoder (not shown) to perform the LDPC encoding.

Specifically, the encoder 110 LDPC-encodes information word(or information) bits to generate the LDPC codeword which is formed of the information word bits and parity bits (that is, LDPC parity bits). Here, bits input to the encoder 110 may be used to the information word bits. Also, since an LDPC code is a systematic code, the information word bits may be included in the LDPC codeword as they are.

The LDPC codeword is formed of the information word bits and the parity bits. For example, the LDPC codeword is formed of N ldpc number of bits, and includes K ldpc number of information word bits and N parity =N ldpc −K ldpc number of parity bits.

In this case, the encoder 110 may generate the LDPC codeword by performing the LDPC encoding based on the parity check matrix. That is, since the LDPC encoding is a process for generating an LDPC codeword to satisfy H·C T =0, the encoder 110 may use the parity check matrix when performing the LDPC encoding. Herein, H is a parity check matrix and C is an LDPC codeword.

For the LDPC encoding, the transmitting apparatus 100 may include a memory and may pre-store parity check matrices of various formats.

For example, the transmitting apparatus 100 may pre-store parity check matrices which are defined in Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video Broadcasting-Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second Generation Terrestrial (DVB-T2), etc., or may pre-store parity check matrices which are defined in the North America digital broadcasting standard system Advanced Television System Committee (ATSC) 3.0 standards, which are currently being established. However, this is merely an example and the transmitting apparatus 100 may pre-store parity check matrices of other formats in addition to these parity check matrices.

Hereinafter, a parity check matrix according to various exemplary embodiments will be explained in detail with reference to the drawings. In the parity check matrix, elements other than elements having 1 have 0.

For example, the parity check matrix according to an exemplary embodiment may have a configuration of FIG. 20 .

Referring to FIG. 20 , a parity check matrix 200 is formed of an information word submatrix (or an information submatrix) 210 corresponding to information word bits, and a parity submatrix 220 corresponding to parity bits.

The information word submatrix 210 includes K ldpc number of columns and the parity submatrix 220 includes N parity =N ldpc −K ldpc number of columns. The number of rows of the parity check matrix 200 is identical to the number of columns of the parity submatrix 220 , N parity =N ldpc −K ldpc .

In addition, in the parity check matrix 200 , N ldpc is a length of an LDPC codeword, K ldpc is a length of information word bits, and N parity =N ldpc −K ldpc is a length of parity bits. The length of the LDPC codeword, the information word bits, and the parity bits mean the number of bits included in each of the LDPC codeword, the information word bits, and the parity bits.

Hereinafter, the configuration of the information word submatrix 210 and the parity submatrix 220 will be explained in detail.

The information word submatrix 210 includes K ldpc number of columns (that is, 0 th column to (K ldpc −1) th column), and follows the following rules:

First, M number of columns from among K ldpc number of columns of the information word submatrix 210 belong to the same group, and K ldpc number of columns is divided into K ldpc /M number of column groups. In each column group, a column is cyclic-shifted from an immediately previous column by Q ldpc . That is, Q ldpc may be a cyclic shift parameter value regarding columns in a column group of the information word submatrix 210 of the parity check matrix 200 .

Herein, M is an interval at which a pattern of a column group, which includes a plurality of columns, is repeated in the information word submatrix 210 (e.g., M=360), and Q ldpc is a size by which one column is cyclic-shifted from an immediately previous column in a same column group in the information word submatrix 210 . Also, M is a common divisor of N ldpc and K ldpc and is determined to satisfy Q ldpc =(N ldpc −K ldpc )/M. Here, M and Q ldpc are integers and K ldpc /M is also an integer. M and Q ldpc may have various values according to a length of the LDPC codeword and a code rate (CR)(or, coding rate).

For example, when M=360 and the length of the LDPC codeword, N ldpc , is 64800, Q ldpc may be defined as in Table 1 presented below, and, when M=360 and the length N ldpc of the LDPC codeword is 16200, Q ldpc may be defined as in Table 2 presented below.

Second, when the degree of the 0 th column of the i th column group (i=0, 1, . . . , K ldpc /M−1) is D i (herein, the degree is the number of value 1 existing in each column and all columns belonging to the same column group have the same degree), and a position (or an index) of each row where 1 exists in the 0 th column of the i th column group is R i,0 (0) R i,0 (1) , . . . , R i,0 (D i -1) , an index R i,j (k) of a row where k th 1 is located in the j th column in the i th column group is determined by following Equation 1:

R i,j (k) =R i,(j-1) (k) +Q ldpc mod( N ldpc −K ldpc )  (1),

where k=0, 1, 2, . . . D i −1; i=0, 1, . . . , K ldpc /M−1; and j=1, 2, . . . , M−1.

Equation 1 can be expressed as following Equation 2:

R i,j (k) ={R i,0 (k) +( j mod M )× Q ldpc } mod( N ldpc −K ldpc )  (2),

where k=0, 1, 2, . . . D i −1; i=0, 1, . . . , K ldpc /M−1; and j=1, 2, . . . , M−1. Since j=1, 2, . . . , M−1, (j mod M) of Equation 2 may be regarded as j.

In the above equations, R i,j (k) is an index of a row where k th 1 is located in the j th column in the i th column group, N ldpc is a length of an LDPC codeword, K ldpc is a length of information word bits, D i is a degree of columns belonging to the i th column group, M is the number of columns belonging to a single column group, and Q ldpc is a size by which each column in the column group is cyclic-shifted.

As a result, referring to these equations, when only R i,0 (k) is known, the index R i,j (k) of the row where the k th 1 is located in the j th column in the i th column group can be known. Therefore, when the index value of the row where the k th 1 is located in the 0 th column of each column group is stored, a position of column and row where 1 is located in the parity check matrix 200 having the configuration of FIG. 20 (that is, in the information word submatrix 210 of the parity check matrix 200 ) can be known.

According to the above-described rules, all of the columns belonging to the i th column group have the same degree D i . Accordingly, the LDPC codeword which stores information on the parity check matrix according to the above-described rules may be briefly expressed as follows.

For example, when N ldpc is 30, K ldpc is 15, and Q ldpc is 3, position information of the row where 1 is located in the 0 th column of the three column groups may be expressed by a sequence of Equations 3 and may be referred to as “weight-1 position sequence”.

R 1,0 (1) =1, R 1,0 (2) =2, R 1,0 (3) =8, R 1,0 (4) =10,

R 2,0 (1) =0, R 2,0 (2) =9, R 2,0 (3) =13,

R 3,0 (1) =0, R 3,0 (2) =14.  (3),

where R i,j (k) is an index of a row where k th 1 is located in the j th column in the i th column group.

The weight-1 position sequence like Equation 3 which expresses an index of a row where 1 is located in the 0 th column of each column group may be briefly expressed as in Table 3 presented below:

Table 3 shows positions of elements having value 1 in the parity check matrix, and the i th weight-1 position sequence is expressed by indexes of rows where 1 is located in the 0 th column belonging to the i th column group.

The information word submatrix 210 of the parity check matrix according to an exemplary embodiment may be defined as in Tables 4 to 21 presented below, based on the above descriptions.

Specifically, Tables 4 to 21 show indexes of rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 . That is, the information word submatrix 210 is formed of a plurality of column groups each including M number of columns, and positions of 1 in the 0 th column of each of the plurality of column groups may be defined by Tables 4 to 21.

Herein, the indexes of the rows where 1 is located in the 0 th column of the i th column group mean “addresses of parity bit accumulators”. The “addresses of parity bit accumulators” have the same meaning as defined in the DVB-C2/S2/T2 standards or the ATSC 3.0 standards which are currently being established, and thus, a detailed explanation thereof is omitted.

For example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 5/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 4 presented below:

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 7/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 5 or 6 presented below:

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 9/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 7 or 8 presented below:

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 11/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 9 or 10 presented below:

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 13/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 11 or 12 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 13 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 7/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 14 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 8/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 15 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 9/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 16 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 17 or 18 below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 11/15, and M is 360, the indexes of rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 19 below.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 12/15, and M is 360, the indexes of rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 20 below.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 13/15, and M is 360, the indexes of rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 21 below:

According to an exemplary embodiment, even when the order of numbers in a sequence corresponding to the i th column group of the parity check matrix 200 as shown in the above-described Tables 4 to 21 is changed, the changed parity check matrix is a parity check matrix used for the same code. Therefore, a case in which the order of numbers in the sequence corresponding to the i th column group in Tables 4 to 21 is changed is covered by the inventive concept.

According to an exemplary embodiment, even when the arrangement order of sequences corresponding to each column group is changed in Tables 4 to 21, cycle characteristics on a graph of a code and algebraic characteristics such as degree distribution are not changed. Therefore, a case in which the arrangement order of the sequences shown in Tables 4 to 21 is changed is also covered by the inventive concept.

In addition, even when a multiple of Q ldpc is equally added to all sequences corresponding to a certain column group in Tables 4 to 21, the cycle characteristics on the graph of the code or the algebraic characteristics such as degree distribution are not changed. Therefore, a result of equally adding a multiple of Q ldpc to the sequences shown in Tables 4 to 21 is also covered by the inventive concept. However, it should be noted that, when the resulting value obtained by adding the multiple of Q ldpc to a given sequence is greater than or equal to (N ldpc −K ldpc ), a value obtained by applying a modulo operation for (N ldpc −K ldpc ) to the resulting value should be applied instead.

Once positions of the rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Tables 4 to 21, positions of rows where 1 exists in another column of each column group may be defined since the positions of the rows where 1 exists in the 0 th column are cyclic-shifted by Q ldpc in the next column.

For example, in the case of Table 4, in the 0 th column of the 0 th column group of the information word submatrix 210 , 1 exists in the 245 th row, 449 th row, 491 st row, . . . .

In this case, since Q ldpc =(N ldpc −K ldpc )/M=(16200−5400)/360=30, the indexes of the rows where 1 is located in the 1 st column of the 0 th column group may be 275(=245+30), 479(=449+30), 521(=491+30), . . . , and the indexes of the rows where 1 is located in the 2 nd column of the 0 th column group may be 305(=275+30), 509(=479+30), 551(=521+30), . . . .

In the above-described method, the indexes of the rows where 1 is located in all rows of each column group may be defined.

The parity submatrix 220 of the parity check matrix 200 shown in FIG. 20 may be defined as follows:

The parity submatrix 220 includes N ldpc −K ldpc number of columns (that is, K ldpc th column to (N lpd −1) th column), and has a dual diagonal or staircase configuration. Accordingly, the degree of columns except the last column (that is, (N ldpc −1) th column) from among the columns included in the parity submatrix 220 is 2, and the degree of the last column is 1.

As a result, the information word submatrix 210 of the parity check matrix 200 may be defined by Tables 4 to 21, and the parity submatrix 220 of the parity check matrix 200 may have a dual diagonal configuration.

When the columns and rows of the parity check matrix 200 shown in FIG. 20 are permutated based on Equation 4 and Equation 5, the parity check matrix shown in FIG. 20 may be changed to a parity check matrix 300 shown in FIG. 21 .

Q ldpc ·i+j M·j+i (0≤ i<M, 0≤ j<Q ldpc )  (4)

K ldpc +Q ldpc ·k+l K ldpc +M·l+k (0≤ k<M, 0≤ l<Q ldpc )  (5)

The method for permutating based on Equation 4 and Equation 5 will be explained below. Since row permutation and column permutation apply the same principle, the row permutation will be explained by the way of an example.

In the case of the row permutation, regarding the X th row, i and j satisfying X=Q ldpc ×i+j are calculated and the X th row is permutated by assigning the calculated i and j to M×j+i. For example, regarding the 7 th row, i and j satisfying 7=2×i+j are 3 and 1, respectively. Therefore, the 7 th row is permutated to the 13 th row (10×1+3=13).

When the row permutation and the column permutation are performed in the above-described method, the parity check matrix of FIG. 20 may be converted into the parity check matrix of FIG. 21 .

Referring to FIG. 21 , the parity check matrix 300 is divided into a plurality of partial blocks, and a quasi-cyclic matrix of M×M corresponds to each partial block.

Accordingly, the parity check matrix 300 having the configuration of FIG. 21 is formed of matrix units of MxM. That is, the submatrices of M×M are arranged in the plurality of partial blocks, constituting the parity check matrix 300 .

Since the parity check matrix 300 is formed of the quasi-cyclic matrices of M×M, M number of columns may be referred to as a column block and M number of rows may be referred to as a row block. Accordingly, the parity check matrix 300 having the configuration of FIG. 21 is formed of N qc _ column =N ldpc /M number of column blocks and N qc _ row =N parity /M number of row blocks.

Hereinafter, the submatrix of M×M will be explained.

First, the (N qc _ column −1) th column block of the 0 th row block has a form shown in Equation 6 presented below:

As described above, A 330 is an M×M matrix, values of the 0 th row and the (M−1) th column are all “0”, and, regarding 0≤i≤(M−2), the (i+1) th row of the i th column is “1” and the other values are “0”.

Second, regarding 0≤i≤(N ldpc −K ldpc )/M−1 in the parity submatrix 320 , the i th row block of the (K ldpc /M+i) th column block is configured by a unit matrix I M×M 340 . In addition, regarding 0<i<(N ldpc −K ldpc )/M−2, the (i+l) th row block of the (K ldpc /M+i) th column block is configured by a unit matrix I M×M 340 .

Third, a block 350 constituting the information word submatrix 310 may have a cyclic-shifted format of a cyclic matrix P, P a ij , or an added format of the cyclic-shifted matrix P a ij of the cyclic matrix P (or an overlapping format).

For example, a format in which the cyclic matrix P is cyclic-shifted to the right by 1 may be expressed by Equation 7 presented below:

The cyclic matrix P is a square matrix having an M×M size and is a matrix in which a weight of each of M number of rows is 1 and a weight of each of M number of columns is 1. When a ij is 0, the cyclic matrix P, that is, P 0 indicates a unit matrix I M×M , and when a ij is ∞, P ∞ is a zero matrix.

A submatrix existing where the i th row block and the j th column block intersect in the parity check matrix 300 of FIG. 21 may be P a ij . Accordingly, i and j indicate the number of row blocks and the number of column blocks in the partial blocks corresponding to the information word. Accordingly, in the parity check matrix 300 , the total number of columns is N ldpc =M×N qc _ column , and the total number of rows is N parity =M×N qc _ row . That is, the parity check matrix 300 is formed of N qc _ column number of “column blocks” and N qc _ row number of “row blocks”.

Hereinafter, a method for performing LDPC encoding based on the parity check matrix 200 as shown in FIG. 20 will be explained. An LDPC encoding process when the parity check matrix 200 is defined as shown in Table 10 by way of an example will be explained for the convenience of explanation.

First, when information word bits having a length of K ldpc are [i 0 , i 1 , i 2 , . . . , i K ldp −1 ], and parity bits having a length of N ldpc −K ldpc are [p 0 , p 1 , p 2 , . . . P N ldpc −K dpc −1 ], the LDPC encoding is performed by the following process.

Step 1) Parity bits are initialized as ‘0’. That is, p 0 =p 1 =p 2 = . . . =p N ldpc −K ldpc −1 =0.

Step 2) The 0 th information word bit i 0 is accumulated in a parity bit having the address of the parity bit defined in the first row (that is, the row of i=0) of Table 10 as the index of the parity bit. This may be expressed by Equation 8 presented below:

P 49 =P 49 ⊕i 0 P 2685 =P 2685 ⊕i 0

P 719 =P 719 ⊕i 0 P 2873 =P 2873 ⊕i 0

P 784 =P 784 ⊕i 0 P 2974 =P 2974 ⊕i 0

P 794 =P 794 ⊕i 0 P 2995 =P 2995 ⊕i 0

P 968 =P 968 ⊕i 0 P 3540 =P 3540 ⊕i 0

P 2382 =P 2382 ⊕i 0 P 4179 =P 4179 ⊕i 0   (8)

Herein, i 0 is a 0 th information word bit, p i is an ith parity bit, and ⊕ is a binary operation. According to the binary operation, 1⊕1 equals 0, 1⊕0 equals 1, 0⊕1 equals 1, 0⊕0 equals 0.

Step 3) The other 359 information word bits i m (m=1, 2, . . . , 359) are accumulated in the parity bit. The other information word bits may belong to the same column group as that of i 0 . In this case, the address of the parity bit may be determined based on Equation 9 presented below:

( x +( m mod 360)× Q ldpc )mod( N ldpc −K ldpc )  (9)

Herein, x is an address of a parity bit accumulator corresponding to the information word bit i 0 , and Q ldpc is a size by which each column is cyclic-shifted in the information word submatrix, and may be 12 in the case of Table 10. In addition, since m=1, 2, . . . , 359, (m mod 360) in Equation 9 may be regarded as m.

As a result, information word bits i m (m=1,2, . . . , 359) are accumulated in the parity bits having the address of the parity bit calculated based on Equation 9 as the index. For example, an operation as shown in Equation 10 presented below may be performed for the information word bit i 1 :

P 61 =P 61 ⊕i 1 P 2697 =P 2697 ⊕i 1

P 731 =P 731 ⊕i 1 P 2885 =P 2885 ⊕i 1

P 796 =P 796 ⊕i 1 P 2986 =P 2986 ⊕i 1

P 806 =P 806 ⊕i 1 P 3007 =P 3007 ⊕i 1

P 980 =P 980 ⊕i 1 P 3552 =P 3552 ⊕i 1

P 2394 =P 2394 ⊕i 1 P 4191 =P 4191 ⊕i 1   (10)

Herein, i 1 is a 1 st information word bit, p i is an ith parity bit, and ⊕ is a binary operation. According to the binary operation, 1⊕1 equals 0, 1⊕0 equals 1, 0⊕1 equals 1, 0⊕0 equals 0.

Step 4) The 360 th information word bits i 360 is accumulated in a parity bit having the address of the parity bit defined in the 2 nd row (that is, the row of i=1) of Table 10 as the index of the parity bit.

Step 5) The other 359 information word bits belonging to the same group as that of the information word bit i 360 are accumulated in the parity bit. In this case, the address of the parity bit may be determined based on Equation 9. However, in this case, x is the address of the parity bit accumulator corresponding to the information word bit i 360 .

Step 6) Steps 4 and 5 described above are repeated for all of the column groups of Table 10.

Step 7) As a result, a parity bit p i is calculated based on Equation 11 presented below. In this case, i is initialized as 1.

p i =p i ⊕p i-1 i= 1,2, . . . , N ldpc −K ldpc −1  (11)

In Equation 11, p i is an ith parity bit, N ldpc is a length of an LDPC codeword, K ldpc is a length of an information word of the LDPC codeword, and ⊕ is a binary operation.

As a result, the encoder 110 may calculate the parity bits according to the above-described method.

In another example, a parity check matrix according to an exemplary embodiment may have a configuration as shown in FIG. 22 .

Referring to FIG. 22 , the parity check matrix 400 may be formed of 5 matrices A, B, C, Z, and D. Hereinafter, the configuration of each matrix will be explained to explain the configuration of the parity check matrix 400 .

First, M 1 , M 2 , Q 1 , and Q 2 , which are parameter values related to the parity check matrix 400 as shown in FIG. 22 , may be defined as shown in Table 22 presented below according to the length and the code rate of the LDPC codeword.

The matrix A is formed of K number of columns and g number of rows, and the matrix C is formed of K+g number of columns and N−K−g number of rows. Herein, K is a length of information word bits, and N is a length of the LDPC codeword.

Indexes of rows where 1 is located in the 0 th column of the ith column group in the matrix A and the matrix C may be defined based on Tables 23 to 31 according to the length and the code rate of the LDPC codeword. In this case, an interval at which a pattern of a column is repeated in each of the matrix A and the matrix C, that is, the number of columns belonging to the same group, may be 360.

For example, when the length N of the LDPC codeword is 64800 and the code rate is 3/15, the indexes of rows where 1 is located in the 0 th column of the ith column group in the matrix A and the matrix C are defined as shown in Table 23 presented below:

In another example, when the length N of the LDPC codeword is 16200 and the code rate is 4/15, the indexes of rows where 1 is located in the 0 th column of the ith column group in the matrix A and the matrix C are defined as shown in Table 24 presented below:

In another example, when the length N of the LDPC codeword is 64800 and the code rate is 4/15, the indexes of rows where 1 is located in the 0 th column of the ith column group in the matrix A and the matrix C are defined as shown in Table 25 presented below:

In another example, when the length N of the LDPC codeword is 16200 and the code rate is 5/15, the indexes of rows where 1 is located in the 0 th column of the ith column group in the matrix A and the matrix C are defined as shown in Table 26 presented below:

In another example, when the length N of the LDPC codeword is 64800 and the code rate is 6/15, the indexes of rows where 1 is located in the 0 th column of the ith column group in the matrix A and the matrix C are defined as shown in Table 27 presented below:

In another example, when the length N of the LDPC codeword is 16200 and the code rate is 6/15, the indexes of rows where 1 is located in the 0th column of the ith column group in the matrix A and the matrix C are defined as shown in Table 28 presented below:

In another example, when the length N of the LDPC codeword is 64800 and the code rate is 6/15, the indexes of rows where 1 is located in the 0 th column of the ith column group in the matrix A and the matrix C are defined as shown in Table 29 presented below:

In another example, when the length N of the LDPC codeword is 16200 and the code rate is 7/15, the indexes of rows where 1 is located in the 0 th column of the ith column group in the matrix A and the matrix C are defined as shown in Table 30 presented below:

In another example, when the length N of the LDPC codeword is 64800 and the code rate is 7/15, the indexes of rows where 1 is located in the 0 th column of the ith column group in the matrix A and the matrix C are defined as shown in Table 31 presented below:

Hereinafter, positions of rows where 1 exists in the matrix A and the matrix C will be explained with reference to Table 24 by way of an example.

Since the length N of the LDPC codeword is 16200 and the code rate is 4/15 in Table 24, M 1 =1080, M 2 =10800, Q 1 =3, and Q 2 =30 in the parity check matrix 400 defined by Table 24 with reference to Table 22.

Herein, Q 1 is a size by which columns of the same column group are cyclic-shifted in the matrix A, and Q 2 is a size by which columns of the same column group are cyclic-shifted in the matrix C.

In addition, Q 1 =M 1 /L, Q 2 =M 2 /L, M 1 =g, and M 2 =N−K-g, and L is an interval at which a pattern of a column is repeated in the matrix A and the matrix C, and for example, may be 360.

The index of the row where 1 is located in the matrix A and the matrix C may be determined based on the M 1 value.

For example, since M 1 =1080 in the case of Table 24, the positions of the rows where 1 exists in the 0 th column of the ith column group in the matrix A may be determined based on values smaller than 1080 from among the index values of Table 24, and the positions of the rows where 1 exists in the 0 th column of the ith column group in the matrix C may be determined based on values greater than or equal to 1080 from among the index values of Table 24.

Specifically, in Table 24, the sequence corresponding to the 0 th column group is “19, 585, 710, 3241, 3276, 3648, 6345, 9224, 9890, and 10841”. Accordingly, in the case of the 0 th column of the 0 th column group of the matrix A, 1 may be located in the 19 th row, 585 th row, and 710 th row, and, in the case of the 0 th column of the 0 th column group of the matrix C, 1 may be located in the 3241 st row, 3276 th row, 3648 th row, 6345 th row, 9224 th row, 9890 th row, and 10841 st row.

Once positions of 1 in the 0 th column of each column group of the matrix A are defined, positions of rows where 1 exists in another column of each column group may be defined by cyclic-shifting from the previous column by Q 1 . Once positions of 1 in the 0 th column of each column group of the matrix C are defined, position of rows where 1 exists in another column of each column group may be defined by cyclic-shifting from the previous column by Q 2 .

In the above-described example, in the case of the 0 th column of the 0 th column group of the matrix A, 1 exists in the 19 th row, 585 th row, and 710 th row. In this case, since Q 1 =3, the indexes of rows where 1 exists in the 1 st column of the 0 th column group are 22(=19+3), 588(=585+3), and 713(=710+3), and the index of rows where 1 exists in the 2 nd column of the 0 th column group are 25(=22+3), 591 (=588+3), and 716(=713+3).

In the case of the 0 th column of the 0 th column group of the matrix C, 1 exists in the 3241 st row, 3276 th row, 3648 th row, 6345 th row, 9224 th row, 9890 th row, and 10841 st row. In this case, since Q 2 =30, the index of rows where 1 exists in the 1 st column of the 0 th column group are 3271 (=3241+30), 3306(=3276+30), 3678 (=3648+30), 6375 (=6345+30), 9254 (=9224+30), 9920 (=9890+30), and 10871 (=10841+30), and the indexes of rows where 1 exists in the 2 nd column of the 0 th column group are 3301 (=3271+30), 3336(=3306+30), 3708 (=3678+30), 6405 (=6375+30), 9284 (=9254+30), 9950 (=9920+30), 10901 (=10871+30).

In this method, the positions of rows where 1 exists in all column groups of the matrix A and the matrix C are defined.

The matrix B may have a dual diagonal configuration, the matrix D may have a diagonal configuration (that is, the matrix D is an identity matrix), and the matrix Z may be a zero matrix.

As a result, the parity check matrix 400 shown in FIG. 22 may be defined by the matrices A, B, C, D, and Zhaving the above-described configurations.

Hereinafter, a method for performing LDPC encoding based on the parity check matrix 400 shown in FIG. 22 will be explained. An LDPC encoding process when the parity check matrix 400 is defined as shown in Table 24 by way of an example will be explained for the convenience of explanation.

For example, when an information word block S=(s 0 , s 1 , . . . , S K−1 ) is LDPC-encoded, an LDPC codeword Λ=(λ 0 , λ 1 , . . . , λ N-1 )=(s 0 , s 1 , . . . , S K−1 , p 0 , p 1 , . . . , P M 1 +M 2 −1 ) including a parity bit P=(p 0 , p 1 , . . . , P M 1 +M 2 −1 )

M 1 and M 2 indicate the size of the matrix B having the dual diagonal configuration and the size of the matrix C having the diagonal configuration, respectively, and M 1 =g, M 2 =N−K−g.

A process of calculating a parity bit is as follows. In the following explanation, the parity check matrix 400 is defined as shown in Table 24 by way of an example, for the convenience of explanation.

Step 1) λ and p are initialized as λ i =s i (i=0, 1, . . . , K−1), p j =0 (j=0, 1, . . . , M 1 +M 2 −1).

Step 2) The 0 th information word bit λ 0 is accumulated in the address of the parity bit defined in the first row (that is, the row of i=0) of Table 24. This may be expressed by Equation 12 presented below:

P 19 =P 19 ⊕λ 0 P 6345 =P 6345 ⊕λ 0

P 585 =P 585 ⊕λ 0 P 9224 =P 9224 ⊕λ 0

P 710 =P 710 ⊕λ 0 P 9890 =P 9890 ⊕λ 0

P 3241 =P 3241 ⊕λ 0 P 10841 =P 10841 ⊕λ 0

P 3276 =P 3276 ⊕λ 0

P 3648 =P 3648 ⊕λ 0   (12)

Step 3) Regarding the next L−1 number of information word bits X, (m=1, 2, . . . , L−1), λ m is accumulated in the parity bit address calculated based on Equation 13 presented below:

(χ+ m×Q 1 )mod M 1 (if χ< M 1 )

M 1 +{(χ− M 1 +m×Q 2 )mod M 2 } (if χ≥ M 1 )  (13)

Herein, x is an address of a parity bit accumulator corresponding to the 0 th information word bit λ 0 .

In addition, Q 1 =M 1 /L and Q 2 =M 2 /L. In addition, since the length N of the LDPC codeword is 16200 and the code rate is 4/15 in Table 24, M 1 =1080, M 2 =10080, Q 1 =3, Q 2 =30, and L=360 with reference to Table 22.

Accordingly, an operation as shown in Equation 14 presented below may be performed for the 1 st information word bit λ 1 :

P 22 =P 22 ⊕λ 1 P 6375 =P 6375 ⊕λ 1

P 588 =P 588 ⊕λ 1 P 9254 =P 9254 ⊕λ 1

P 713 =P 713 ⊕λ 1 P 9920 =P 9920 ⊕λ 1

P 3271 =P 3271 ⊕λ 1 P 10871 =P 10871 ⊕λ 1

P 3306 =P 3306 ⊕λ 1

P 3678 =P 3678 ⊕λ 1   (14)

Step 4) Since the same address of the parity bit as in the second row (that is the row of i=1) of Table 24 is given to the Lth information word bit λ L , in a similar method to the above-described method, the address of the parity bit regarding the next L−1 number of information word bits λ m (m=L+1, L+2, . . . , 2L−1) is calculated based on Equation 13. In this case, x is the address of the parity bit accumulator corresponding to the information word bit λ L , and may be obtained based on the second row of Table 24.

Step 5) The above-described processes are repeated for L number of new information word bits of each group by considering new rows of Table 24 as the address of the parity bit accumulator.

Step 6) After the above-described processes are repeated for the codeword bits λ 0 to λ K−1 , values regarding Equation 15 presented below are calculated in sequence from i=1:

P i =P i ⊕P i-1 ( i= 1,2, . . . , M 1 −1)  (15)

Step 7) Parity bits λ K to λ K+M 1 −1 corresponding to the matrix B having the dual diagonal configuration are calculated based on Equation 16 presented below:

λ K+L×t+s =P Q 1 ×S+t (0≤ s<L, 0≤ t<Q 1 )  (16)

Step 8) The address of the parity bit accumulator regarding L number of new codeword bits λ K to λ K+M 1 −1 of each group is calculated based on Table 24 and Equation 13.

Step 9) After the codeword bits λ K to λ K+M 1 −1 are calculated, parity bits λ K+M 1 to λ K+M 1 +M 2 −1 corresponding to the matrix C having the diagonal configuration are calculated based on Equation 17 presented below:

λ K+M 1 +L×t+s =p M 1 +Q 2 ×S+t (0≤ s<L, 0≤ t<Q 2 )  (17)

As a result, the parity bits may be calculated in the above-described method.

Referring back to FIG. 19 , the encoder 110 may perform the LDPC encoding by using various code rates such as 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, etc. In addition, the encoder 110 may generate an LDPC codeword having various lengths such as 16200, 64800, etc., based on the length of the information word bits and the code rate.

In this case, the encoder 110 may perform the LDPC encoding by using the parity check matrix, and the parity check matrix is configured as shown in FIGS. 20 to 22 .

In addition, the encoder 110 may perform Bose, Chaudhuri, Hocquenghem (BCH) encoding as well as LDPC encoding. To achieve this, the encoder 110 may further include a BCH encoder (not shown) to perform BCH encoding.

In this case, the encoder 110 may perform encoding in an order of BCH encoding and LDPC encoding. Specifically, the encoder 110 may add BCH parity bits to input bits by performing BCH encoding and LDPC-encodes the information word bits including the input bits and the BCH parity bits, thereby generating the LDPC codeword.

The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoder 110 , and interleaves the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 may interleave the LDPC codeword such that a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword (that is, a plurality of groups or a plurality of blocks) is mapped onto a predetermined bit of a modulation symbol.

In this case, the interleaver 120 may interleave the LDPC codeword such that bits included in continuous bit groups from among the plurality of bit groups of the LDPC codeword are mapped onto the same modulation symbol.

In addition, when check nodes connected only to a single parity bit in the parity check matrix of the LDPC code exists in plurality number, the interleaver 120 may interleave the LDPC codeword such that bits included in the bit groups corresponding to the parity bit to which the check nodes are connected are selectively mapped onto the modulation symbol.

Accordingly, the modulator 130 may map the bit included in the predetermined bit group from among the plurality of bit groups of the LDPC codeword onto a predetermined bit of the modulation symbol.

That is, the modulator 130 may map the bits included in the continuous bit groups from among the plurality of bit groups of the LDPC codeword onto the same modulation symbol. In addition, when the check nodes connected only to a single parity bit in the parity check matrix of the LDPC code exists in plurality number, the modulator 130 may selectively map the bits included in the bit groups corresponding to the parity bit to which the check nodes are connected onto the same modulation symbol.

To achieve this, as shown in FIG. 23 , the interleaver 120 may include a parity interleaver 121 , a group interleaver (or a group-wise interleaver 122 ), a group twist interleaver 123 and a block interleaver 124 .

The parity interleaver 121 interleaves the parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the configuration of FIG. 20 , the parity interleaver 121 may interleave only the parity bits of the LDPC codeword by using Equations 18 presented below:

u i =c i for 0≤ i<K ldpc , and

u K ldpc +M·t+s =c K ldpc +Q ldpc ·s+t for 0≤ s<M, 0≤ t<Q ldpc   (18),

where M is an interval at which a pattern of a column group is repeated in the information word submatrix 210 , that is, the number of columns included in a column group (for example, M=360), and Q ldpc is a size by which each column is cyclic-shifted in the information word submatrix 210 . That is, the parity interleaver 121 performs parity interleaving with respect to the LDPC codeword c=(c 0 , c 1 , . . . , c N ldpc −1 ), and outputs U=(u 0 , u 1 , . . . , u N ldpc −1 ).

The LDPC codeword parity-interleaved in the above-described method may be configured such that a predetermined number of continuous bits of the LDPC codeword have similar decoding characteristics (cycle distribution, a degree of a column, etc.).

For example, the LDPC codeword may have the same characteristics on the basis of M number of continuous bits. Herein, M is an interval at which a pattern of a column group is repeated in the information word submatrix 210 and, for example, may be 360.

Specifically, a product of the LDPC codeword bits and the parity check matrix should be “0”. This means that a sum of products of the i th LDPC codeword bit, c i (i=0, 1, . . . , N ldpc −1) and the i th column of the parity check matrix should be a “0” vector. Accordingly, the i th LDPC codeword bit may be regarded as corresponding to the i th column of the parity check matrix.

In the case of the parity check matrix 200 of FIG. 20 , M number of columns in the information word submatrix 210 belong to the same group and the information word submatrix 210 has the same characteristics on the basis of a column group (for example, the columns belonging to the same column group have the same degree distribution and the same cycle characteristic).

In this case, since M number of continuous bits in the information word bits correspond to the same column group of the information word submatrix 210 , the information word bits may be formed of M number of continuous bits having the same codeword characteristics. When the parity bits of the LDPC codeword are interleaved by the parity interleaver 121 , the parity bits of the LDPC codeword may be formed of M number of continuous bits having the same codeword characteristics.

However, regarding the LDPC codeword encoded based on the parity check matrix 300 of FIG. 21 and the parity check matrix 400 of FIG. 22 , parity interleaving may not be performed. In this case, the parity interleaver 121 may be omitted.

The group interleaver 122 may divide the parity-interleaved LDPC codeword into a plurality of bit groups and rearrange the order of the plurality of bit groups in bit group wise (or bit group unit). That is, the group interleaver 122 may interleave the plurality of bit groups in bit group wise.

According to an exemplary embodiment, when the parity interleaver 121 is omitted, the group interleaver 122 may divide the LDPC codeword into a plurality of bit groups and rearrange the order of the plurality of bit groups in bit group wise.

To achieve this, the group interleaver 122 divides the parity-interleaved LDPC codeword into a plurality of bit groups by using Equation 19 or Equation 20 presented below.

⁢ X j = { u k ❘ j = ⌊ k 360 ⌋ , 0 ≤ k < N ldpc } ⁢ ⁢ for ⁢ ⁢ 0 ≤ j < N group ( 19 ) X j = { u k ❘ 360 × j ≤ k < 360 × ( j + 1 ) , 0 ≤ k < N ldpc } ⁢ ⁢ for ⁢ ⁢ 0 ≤ j < N group , ( 20 )

where N group is the total number of bit groups, X j is the j th bit group, and u k is the k th codeword bit input to the group interleaver 122 . In addition,

⌊ k 360 ⌋

is the largest integer below k/360.

Since 360 in these equations indicates an example of the interval M at which the pattern of a column group is repeated in the information word submatrix, 360 in these equations can be changed to M.

The LDPC codeword which is divided into the plurality of bit groups may be as shown in FIG. 24 .

Referring to FIG. 24 , the LDPC codeword is divided into the plurality of bit groups and each bit group is formed of M number of continuous bits. When M is 360, each of the plurality of bit groups may be formed of 360 bits. Accordingly, the bit groups may be formed of bits corresponding to the column groups of the parity check matrix.

Specifically, since the LDPC codeword is divided by M number of continuous bits, K ldpc number of information word bits are divided into (K ldpc /M) number of bit groups and N ldpc −K ldpc number of parity bits are divided into (N ldpc −K ldpc )/M number of bit groups. Accordingly, the LDPC codeword may be divided into (N ldpc /M) number of bit groups in total.

For example, when M=360 and the length N ldpc of the LDPC codeword is 64800, the number of bit groups N groups is 180(=64800/360), and, when the M=360 and the length N ldpc of the LDPC codeword is 16200, the number of bit groups N group is 45(=16200/360).

As described above, the group interleaver 122 divides the LDPC codeword such that M number of continuous bits are included in a same group since the LDPC codeword has the same codeword characteristics on the basis of M number of continuous bits. Accordingly, when the LDPC codeword is grouped by M number of continuous bits, the bits having the same codeword characteristics belong to the same group.

In the above-described example, the number of bits constituting each bit group is M. However, this is merely an example and the number of bits constituting each bit group is variable.

For example, the number of bits constituting each bit group may be an aliquot part of M. That is, the number of bits constituting each bit group may be an aliquot part of the number of columns constituting a column group of the information word submatrix of the parity check matrix. In this case, each bit group may be formed of aliquot part of M number of bits. For example, when the number of columns constituting a column group of the information word submatrix is 360, that is, M=360, the group interleaver 122 may divide the LDPC codeword into a plurality of bit groups such that the number of bits constituting each bit group is one of the aliquot parts of 360.

In the following explanation, the number of bits constituting a bit group is M by way of an example, for the convenience of explanation.

Thereafter, the group interleaver 122 interleaves the LDPC codeword in bit group wise. Specifically, the group interleaver 122 may group the LDPC codeword into the plurality of bit groups and rearrange the plurality of bit groups in bit group wise. That is, the group interleaver 122 changes positions of the plurality of bit groups constituting the LDPC codeword and rearranges the order of the plurality of bit groups constituting the LDPC codeword in bit group wise.

Herein, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise such that bit groups including bits mapped onto the same modulation symbol from among the plurality of bit groups are spaced apart from one another at predetermined intervals.

In this case, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by considering at least one of the number of rows and columns of the block interleaver 124 , the number of bit groups of the LDPC codeword, and the number of bits included in each bit group, such that bit groups including bits mapped onto the same modulation symbol are spaced apart from one another at predetermined intervals.

To achieve this, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by using Equation 21 presented below:

Y j =X π(j) (0≤ j<N group )  (21),

where X j is the j th bit group before group interleaving, and Y j is the j th bit group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a modulation method, and a code rate. That is, π(j) denotes a permutation order for group wise interleaving.

Accordingly, X π(j) is a π(j) th bit group before group interleaving, and Equation 21 means that the pre-interleaving π(j) th bit group is interleaved into the j th bit group.

According to an exemplary embodiment, an example of π(j) may be defined as in Tables 32 to 56 presented below.

In this case, π(j) is defined according to a length of an LPDC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate. Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in bit group wise based on π(j) satisfying the corresponding length of the LDPC codeword and code rate.

For example, when the encoder 110 performs LDPC encoding at a code rate of 7/15 to generate an LDPC codeword of a length of 16200, the group interleaver 122 may perform interleaving by using π(j) which is defined according to the length of the LDPC codeword of 16200 and the code rate of 7/15 in Tables 32 to 56 presented below.

For example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 5/15, and the modulation method(or modulation format) is Quadrature Phase Shift Keying (QPSK), π(j) may be defined as in Table 32 presented below. In particular, Table 32 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 26.

In the case of Table 32, Equation 21 may be expressed as Y 0 =X π(0) =X 35 , Y 1 =X π(1) =X 7 , Y 2 =X π(2) =X 29 , . . . , Y 43 =X π(43) =X 26 , and Y 44 =X π(44) =X 8 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 35 th bit group to the 0 th bit group, the 7 th bit group to the 1 st bit group, the 29 th bit group to the 2 nd bit group, . . . , the 26 th bit group to the 43 rd bit group, and the 8 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 7/15, and the modulation method is QPSK, π(j) may be defined as in Table 33 presented below. In particular, Table 33 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 6.

In the case of Table 33, Equation 21 may be expressed as Y 0 =X π(0) =X 4 , Y 1 =X π(1) =X 22 , Y 2 =X π(2) =X 23 , . . . , Y 43 =X π(43) =X 35 , and Y 44 =X π(44) =X 8 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 4 th bit group to the 0 th bit group, the 22 nd bit group to the 1 st bit group, the 23 rd bit group to the 2 nd bit group, . . . , the 35 th bit group to the 43 rd bit group, and the 8 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 9/15, and the modulation method is QPSK, π(j) may be defined as in Table 34 presented below. In particular, Table 34 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 8.

In the case of Table 34, Equation 21 may be expressed as Y 0 =X π(0) =X 28 , Y 1 =X π(1) =X 16 , Y 2 =X π(2) =X 13 , . . . , Y 43 =X π(43) =X 37 , and Y 44 =X π(44) =X 18 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 28 th bit group to the 0 th bit group, the 16 th bit group to the 1 st bit group, the 13 th bit group to the 2 nd bit group, . . . , the 37 th bit group to the 43 rd bit group, and the 18 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 11/15, and the modulation method is QPSK, π(j) may be defined as in Table 35 presented below. In particular, Table 35 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 10.

In the case of Table 35, Equation 21 may be expressed as Y 0 =X π(0) =X 1 , Y 1 =X π(1) =X 2 , Y 2 =X π(2) =X 40 , . . . , Y 43 =X π(43) =X 30 , and Y 44 =X π(44) =X 21 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 1 st bit group to the 0 th bit group, the 2 nd bit group to the 1 st bit group, the 40 th bit group to the 2 nd bit group, . . . , the 30 th bit group to the 43 rd bit group, and the 21 st bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 13/15, and the modulation method is QPSK, π(j) may be defined as in Table 36 presented below. In particular, Table 36 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 12.

In the case of Table 36, Equation 21 may be expressed as Y 0 =X π(0) =X 26 , Y 1 =X π(1) =X 10 , Y 2 =X π(2) =X 12 , . . . , Y 43 =X π(43) =X 35 , and Y 44 =X π(44) =X 1 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 26 th bit group to the 0 th bit group, the 10 th bit group to the 1 st bit group, the 12 th bit group to the 2 nd bit group, . . . , the 35 th bit group to the 43 rd bit group, and the 1 st bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 5/15, and the modulation method is QPSK, π(j) may be defined as in Table 37 presented below. In particular, Table 37 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 4.

In the case of Table 37, Equation 21 may be expressed as Y 0 =X π(0) =X 5 , Y 1 =X π(1) =X 20 , Y 2 =X π(2) =X 30 , . . . , Y 43 =X π(43) =X 11 , and Y 44 =X π(44) =X 6 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 5 th bit group to the 0 th bit group, the 20 th bit group to the 1 st bit group, the 30 th bit group to the 2 nd bit group, . . . , the 11 th bit group to the 43 rd bit group, and the 6 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 7/15, and the modulation method is QPSK, π(j) may be defined as in Table 38 presented below. In particular, Table 38 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 5.

In the case of Table 38, Equation 21 may be expressed as Y 0 =X π(0) =X 26 , Y 1 =X π(1) =X 10 , Y 2 =X π(2) =X 12 , . . . , Y 43 =X π(43) =X 35 , and Y 44 =X π(44) =X 1 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 26 th bit group to the 0 th bit group, the 10 th bit group to the 1 st bit group, the 12 th bit group to the 2 nd bit group, . . . , the 35 th bit group to the 43 rd bit group, and the 1 st bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 9/15, and the modulation method is QPSK, π(j) may be defined as in Table 39 presented below. In particular, Table 39 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 7.

In the case of Table 39, Equation 21 may be expressed as Y 0 =X π(0) =X 4 , Y 1 =X π(1) =X 22 , Y 2 =X π(2) =X 23 , . . . , Y 43 =X π(43) =X 35 , and Y 44 =X π(44) =X 8 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 4 th bit group to the 0 th bit group, the 22 nd bit group to the 1 st bit group, the 23 rd bit group to the 2 nd bit group, . . . , the 35 th bit group to the 43 rd bit group, and the 8 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 11/15, and the modulation method is QPSK, π(j) may be defined as in Table 40 presented below. In particular, Table 40 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 9.

In the case of Table 40, Equation 21 may be expressed as Y 0 =X π(0) =X 4 , Y 1 =X π(1) =X 22 , Y 2 =X π(2) =X 23 , . . . , Y 43 =X π(43) =X 35 , and Y 44 =X π(44) =X 8 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 4 th bit group to the 0 th bit group, the 22 nd bit group to the 1 st bit group, the 23 rd bit group to the 2 nd bit group, . . . , the 35 th bit group to the 43 rd bit group, and the 8 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 13/15, and the modulation method is QPSK, π(j) may be defined as in Table 41 presented below. In particular, Table 41 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 11.

In the case of Table 41, Equation 21 may be expressed as Y 0 =X π(0) =X 6 , Y 1 =X π(1) =X 3 , Y 2 =X π(2) =X 30 , . . . , Y 43 =X π(43) =X 16 , and Y 44 =X π(44) =X 5 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 6 th bit group to the 0 th bit group, the 3 rd bit group to the 1 st bit group, the 30 th bit group to the 2 nd bit group, . . . , the 16 th bit group to the 43 rd bit group, and the 5 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 7/15, and the modulation method is QPSK, π(j) may be defined as in Table 42 presented below. In particular, Table 42 may be applied when LDPC encoding is performed based on the parity check matrix defined by Table 6.

In the case of Table 42, Equation 21 may be expressed as Y 0 =X π(0) =X 3 , Y 1 =X π(1) =X 22 , Y 2 =X π(2) =X 7 , . . . , Y 43 =X π(43) =X 43 , and Y 44 =X π(44) =X 5 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 3 rd bit group to the 0 th bit group, the 22 nd bit group to the 1 st bit group, the 7 th bit group to the 2 nd bit group, . . . , the 43 rd bit group to the 43 rd bit group, and the 8 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 5/15, and the modulation method is QPSK, π(j) may be defined as in Table 43 presented below.

In the case of Table 43, Equation 21 may be expressed as Y 0 =X π(0) =X 28 , Y 1 =X π(1) =X 20 , Y 2 =X π(2) =X 5 , . . . , Y 43 =X π(43) =X 16 , and Y 44 =X π(44) =X 5 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 28 th bit group to the 0 th bit group, the 20 th bit group to the 1 st bit group, the 8 th bit group to the 2 nd bit group, . . . , the 16 th bit group to the 43 rd bit group, and the 5 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 6/15, and the modulation method is QPSK, π(j) may be defined as in Table 44 presented below.

In the case of Table 44, Equation 21 may be expressed as Y 0 =X π(0) =X 36 , Y 1 =X π(1) =X 2 , Y 2 =X π(2) =X 31 , . . . , Y 43 =X π(43) =X 4 , and Y 44 =X π(44) =X 16 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 36 th bit group to the 0 th bit group, the 2 nd bit group to the 1 st bit group, the 31 st bit group to the 2 nd bit group, . . . , the 4 th bit group to the 43 rd bit group, and the 16 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 7/15, and the modulation method is QPSK, π(j) may be defined as in Table 45 presented below.

In the case of Table 45, Equation 21 may be expressed as Y 0 =X π(0) =X 12 , Y 1 =X π(1) =X 39 , Y 2 =X π(2) =X 21 , . . . , Y 43 =X π(43) =X 34 , and Y 44 =X π(44) =X 2 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 12 th bit group to the 0 th bit group, the 39 th bit group to the 1 st bit group, the 21 st bit group to the 2nd bit group, . . . , the 34 th bit group to the 43 rd bit group, and the 2nd bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 16200, the code rate is 9/15, and the modulation method is QPSK, π(j) may be defined as in Table 46 presented below.

In the case of Table 46, Equation 21 may be expressed as Y 0 =X π(0) =X 41 , Y 1 =X π(1) =X 37 , Y 2 =X π(2) =X 26 , . . . , Y 43 =X π(43) =X 39 , and Y 44 =X π(44) =X 38 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 41 st bit group to the 0 th bit group, the 37 th bit group to the 1 st bit group, the 26 th bit group to the 2 nd bit group, . . . , the 39 th bit group to the 43 rd bit group, and the 38 th bit group to the 44 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 5/15, and the modulation method is QPSK, π(j) may be defined as in Table 47 presented below.

In the case of Table 47, Equation 21 may be expressed as Y 0 =X π(0) =X 120 , Y 1 =X π(1) =X 75 , Y 2 =X π(2) =X 171 , . . . , Y 178 =X π(178) =X 93 , and Y 179 =X π(179) =X 161 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 120 th bit group to the 0 th bit group, the 75 th bit group to the 1 st bit group, the 171 st bit group to the 2 nd bit group, . . . , the 93 rd bit group to the 178 th bit group, and the 161 st bit group to the 179 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is QPSK, π(j) may be defined as in Table 48 presented below.

In the case of Table 48, Equation 21 may be expressed as Y 0 =X π(0) =X 92 , Y 1 =X π(1) =X 79 , Y 2 =X π(2) =X 168 , . . . , Y 178 =X π(178) =X 31 , and Y 179 =X π(179) =X 165 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 92 nd bit group to the 0 th bit group, the 79 th bit group to the 1 st bit group, the 168 th bit group to the 2 nd bit group, . . . , the 31 st bit group to the 178 th bit group, and the 165 th bit group to the 179 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is QPSK, π(j) may be defined as in Table 49 presented below.

In the case of Table 49, Equation 21 may be expressed as Y 0 =X π(0) =X 53 , Y 1 =X π(1) =X 65 , Y 2 =X π(2) =X 29 , . . . , Y 178 =X π(178) =X 63 , and Y 179 =X π(179) =X 88 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 53 rd bit group to the 0 th bit group, the 65 th bit group to the 1 st bit group, the 29 th bit group to the 2 nd bit group, . . . , the 63 rd bit group to the 178 th bit group, and the 88 th bit group to the 179 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is QPSK, π(j) may be defined as in Table 50 presented below.

In the case of Table 50, Equation 21 may be expressed as Y 0 =X π(0) =X 18 , Y 1 =X π(1) =X 169 , Y 2 =X π(2) =X 30 , . . . , Y 178 =X π(178) =X 81 , and Y 179 =X π(179) =X 46 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 18 th bit group to the 0 th bit group, the 169 th bit group to the 1 st bit group, the 30 th bit group to the 2 nd bit group, . . . , the 81 st bit group to the 178 th bit group, and the 46 th bit group to the 179 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is QPSK, π(j) may be defined as in Table 51 presented below.

In the case of Table 51, Equation 21 may be expressed as Y 0 =X π(0) =X 18 , Y 1 =X π(1) =X 169 , Y 2 =X π(2) =X 30 , . . . , Y 178 =X π(178) =X 81 , and Y 179 =X π(179) =X 46 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 18 th bit group to the 0 th bit group, the 169 th bit group to the 1 st bit group, the 30 th bit group to the 2 nd bit group, . . . , the 81 st bit group to the 178 th bit group, and the 46 th bit group to the 179 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is QPSK, π(j) may be defined as in Table 52 presented below.

In the case of Table 52, Equation 21 may be expressed as Y 0 =X π(0) =X 18 , Y 1 =X π(1) =X 169 , Y 2 =X π(2) =X 30 , . . . , Y 178 =X π(178) =X 81 , and Y 179 =X π(179) =X 46 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 18 th bit group to the 0 th bit group, the 169 th bit group to the 1 st bit group, the 30 th bit group to the 2 nd bit group, . . . , the 81 st bit group to the 178 th bit group, and the 46 th bit group to the 179 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is QPSK, π(j) may be defined as in Table 53 presented below.

In the case of Table 53, Equation 21 may be expressed as Y 0 =X π(0) =X 43 , Y 1 =X π(1) =X 150 , Y 2 =X π(2) =X 26 , . . . , Y 178 =X π(178) =X 9 , and Y 179 =X π(179) =X 58 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 43 rd bit group to the 0 th bit group, the 150 th bit group to the 1 st bit group, the 26 th bit group to the 2 nd bit group, . . . , the 9 th bit group to the 178 th bit group, and the 58 th bit group to the 179 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is QPSK, π(j) may be defined as in Table 54 presented below.

In the case of Table 54, Equation 21 may be expressed as Y 0 =X π(0) =X 108 , Y 1 =X π(1) =X 17 s, Y 2 =X π(2) =X 95 , . . . , Y 17 s=X π(178) =X 87 , and Y 179 =X π(179) =X 112 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 108 th bit group to the 0 th bit group, the 178 th bit group to the 1 st bit group, the 95 th bit group to the 2 nd bit group, . . . , the 87 th bit group to the 178 th bit group, and the 112 th bit group to the 179 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is QPSK, π(j) may be defined as in Table 55 presented below.

In the case of Table 55, Equation 21 may be expressed as Y 0 =X π(0) =X 57 , Y 1 =X π(1) =X 154 , Y 2 =X π(2) =X 144 , . . . , Y 178 =X π(178) =X 155 , and Y 179 =X π(179) =X 76 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 57 th bit group to the 0 th bit group, the 154 th bit group to the 1 st bit group, the 144 th bit group to the 2 nd bit group, . . . , the 155 th bit group to the 178 th bit group, and the 76 th bit group to the 179 th bit group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, and the modulation method is QPSK, π(j) may be defined as in Table 56 presented below.

In the case of Table 56, Equation 21 may be expressed as Y 0 =X π(0) =X 127 , Y 1 =X π(1) =X 38 , Y 2 =X π(2) =X 14 , . . . , Y 178 =X π(178) =X 102 , and Y 179 =X π(179) =X 92 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by changing the 127 th bit group to the 0 th bit group, the 38 th bit group to the 1 st bit group, the 14 th bit group to the 2 nd bit group, . . . , the 102 nd bit group to the 178 th bit group, and the 92 nd bit group to the 179 th bit group.

As described above, the group interleaver 122 may rearrange the order of the plurality of bit groups in bit group wise by using Equation 21 and Tables 32 to 56.

“j-th block of Group-wise Interleaver output” in Tables 32 to 56 indicates the j-th bit group output from the group interleaver 122 after interleaving, and “π(j)-th block of Group-wise Interleaver input” indicates the π(j)-th bit group input to the group interleaver 122 .

In addition, since the order of the bit groups constituting the LDPC codeword is rearranged by the group interleaver 122 in bit group wise, and then the bit groups are block-interleaved by the block interleaver 124 , which will be described below, “Order of bits groups to be block interleaved” is set forth in Tables 32 to 56 in relation to π(j).

The LDPC codeword which is group-interleaved in the above-described method is illustrated in FIG. 25 . Comparing the LDPC codeword of FIG. 25 and the LDPC codeword of FIG. 24 before group interleaving, it can be seen that the order of the plurality of bit groups constituting wherein Q ldpc is a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, N ldpc is a length of the LDPC codeword, and K ldpc is a length of information word bits of the LDPC codeword.

the LDPC codeword is rearranged.

That is, as shown in FIGS. 24 and 25 , the groups of the LDPC codeword are arranged in order of bit group X 0 , bit group X 1 , . . . , bit group X Ngroup-1 before being group-interleaved, and are arranged in an order of bit group Y 0 , bit group Y 1 , . . . , bit group Y Ngroup-1 after being group-interleaved. In this case, the order of arranging the bit groups by the group interleaving may be determined based on Tables 32 to 56.

The group twist interleaver 123 interleaves bits in a same group. That is, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by changing the order of the bits in the same bit group.

In this case, the group twist interleaver 123 may rearrange the order of the bits in the same bit group by cyclic-shifting a predetermined number of bits from among the bits in the same bit group.

For example, as shown in FIG. 26 , the group twist interleaver 123 may cyclic-shift bits included in the bit group Y 1 to the right by 1 bit. In this case, the bits located in the 0 th position, the 1 st position, the 2 nd position, . . . , the 358 th position, and the 359 th position in the bit group Y 1 as shown in FIG. 26 are cyclic-shifted to the right by 1 bit. As a result, the bit located in the 359 th position before being cyclic-shifted is located in the front of the bit group Y 1 and the bits located in the 0 th position, the 1 st position, the 2 nd position, . . . , the 358 th position before being cyclic-shifted are shifted to the right serially by 1 bit and located.

In addition, the group twist interleaver 123 may rearrange the order of bits in each bit group by cyclic-shifting a different number of bits in each bit group.

For example, the group twist interleaver 123 may cyclic-shift the bits included in the bit group Y 1 to the right by 1 bit, and may cyclic-shift the bits included in the bit group Y 2 to the right by 3 bits.

However, the above-described group twist interleaver 123 may be omitted according to circumstances.

In addition, the group twist interleaver 123 is placed after the group interleaver 122 in the above-described example. However, this is merely an example. That is, the group twist interleaver 123 changes only the order of bits in a certain bit group and does not change the order of the bit groups. Therefore, the group twist interleaver 123 may be placed before the group interleaver 122 .

The block interleaver 124 interleaves the plurality of bit groups the order of which has been rearranged. Specifically, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bit group wise (or bit group unit). The block interleaver 124 is formed of a plurality of columns each including a plurality of rows and may interleave by dividing the plurality of rearranged bit groups based on a modulation order determined according to a modulation method.

In this case, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged by the group interleaver 122 in bit group wise. Specifically, the block interleaver 124 may interleave by dividing the plurality of rearranged bit groups according to a modulation order by using a first part and a second part.

Specifically, the block interleaver 124 interleaves by dividing each of the plurality of columns into a first part and a second part, writing the plurality of bit groups in the plurality of columns of the first part serially in bit group wise, dividing the bits of the other bit groups into groups (or sub bit groups) each including a predetermined number of bits based on the number of columns, and writing the sub bit groups in the plurality of columns of the second part serially.

Herein, the number of bit groups which are interleaved in bit group wise may be determined by at least one of the number of rows and columns constituting the block interleaver 124 , the number of bit groups and the number of bits included in each bit group. In other words, the block interleaver 124 may determine the bit groups which are to be interleaved in bit group wise considering at least one of the number of rows and columns constituting the block interleaver 124 , the number of bit groups and the number of bits included in each bit group, interleave the corresponding bit groups in bit group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. For example, the block interleaver 124 may interleave at least part of the plurality of bit groups in bit group wise using the first part, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups using the second part.

Meanwhile, interleaving bit groups in bit group wise means that the bits included in the same bit group are written in the same column. In other words, the block interleaver 124 , in case of bit groups which are interleaved in bit group wise, may not divide the bits included in the same bit groups and write the bits in the same column, and in case of bit groups which are not interleaved in bit group wise, may divide the bits in the bit groups and write the bits in different columns.

Accordingly, the number of rows constituting the first part is a multiple of the number of bits included in one bit group (for example, 360), and the number of rows constituting the second part may be less than the number of bits included in one bit group.

In addition, in all bit groups interleaved by the first part, the bits included in the same bit group are written and interleaved in the same column of the first part, and in at least one group interleaved by the second part, the bits are divided and written in at least two columns of the second part.

The specific interleaving method will be described later.

Meanwhile, the group twist interleaver 123 changes only the order of bits in the bit group and does not change the order of bit groups by interleaving. Accordingly, the order of the bit groups to be block-interleaved by the block interleaver 124 , that is, the order of the bit groups to be input to the block interleaver 124 , may be determined by the group interleaver 122 . Specifically, the order of the bit groups to be block-interleaved by the block interleaver 124 may be determined by π(j) defined in Tables 32 to 56.

As described above, the block interleaver 124 may interleave the plurality of bit groups the order of which has been rearranged in bit group wise by using the plurality of columns each including the plurality of rows.

In this case, the block interleaver 124 may interleave the LDPC codeword by dividing the plurality of columns into at least two parts. For example, the block interleaver 124 may divide each of the plurality of columns into the first part and the second part and interleave the plurality of bit groups constituting the LDPC codeword.

In this case, the block interleaver 124 may divide each of the plurality of columns into N number of parts (N is an integer greater than or equal to 2) according to whether the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124 , and may perform interleaving.

When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124 , the block interleaver 124 may interleave the plurality of bit groups constituting the LDPC codeword in bit group wise without dividing each of the plurality of columns into parts.

Specifically, the block interleaver 124 may interleave by writing the plurality of bit groups of the LDPC codeword on each of the columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

In this case, the block interleaver 124 may interleave by writing bits included in a predetermined number of bit groups which corresponds to a quotient obtained by dividing the number of bit groups of the LDPC codeword by the number of columns of the block interleaver 124 on each of the plurality of columns serially in a column direction, and reading each row of the plurality of columns in which the bits are written in a row direction.

Hereinafter, the group located in the j th position after being interleaved by the group interleaver 122 will be referred to as group Y j .

For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R 1 number of rows. In addition, it is assumed that the LDPC codeword is formed of N group number of bit groups and the number of bit groups N group is a multiple of C.

In this case, when the quotient obtained by dividing N group number of bit groups constituting the LDPC codeword by C number of columns constituting the block interleaver 124 is A (=N group /C) (A is an integer greater than 0), the block interleaver 124 may interleave by writing A (=N group /C) number of bit groups on each column serially in a column direction and reading bits written on each column in a row direction.

For example, as shown in FIG. 27 , the block interleaver 124 writes bits included in bit group Y 0 , bit group Y 1 , . . . , bit group Y A−1 in the 1 st column from the 1 st row to the R 1 th row, writes bits included in bit group Y A , bit group Y A+1 , . . . , bit group Y 2A−1 in the 2nd column from the 1 st row to the R 1 th row, . . . , and writes bits included in bit group Y CA−A , bit group Y CA−A+1 , . . . , bit group Y CA−1 in the column C from the 1 st row to the R 1 th row. The block interleaver 124 may read the bits written in each row of the plurality of columns in a row direction.

Accordingly, the block interleaver 124 interleaves all bit groups constituting the LDPC codeword in bit group wise.

However, when the number of bit groups of the LDPC codeword is not an integer multiple of the number of columns of the block interleaver 124 , the block interleaver 124 may divide each column into 2 parts and interleave a part of the plurality of bit groups of the LDPC codeword in bit group wise, and divide bits of the other bit groups into sub bit groups and interleave the sub bit groups. In this case, the bits included in the other bit groups, that is, the bits included in the number of groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns are not interleaved in bit group wise, but interleaved by being divided according to the number of columns.

Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.

In this case, the block interleaver 124 may divide the plurality of columns into the first part and the second part based on at least one of the number of columns of the block interleaver 124 , the number of bit groups of the LDPC codeword, and the number of bits of bit groups.

Here, each of the plurality of bit groups may be formed of 360 bits. In addition, the number of bit groups of the LDPC codeword is determined based on the length of the LDPC codeword and the number of bits included in the bit group. For example, when an LDPC codeword in the length of 16200 is divided such that each bit group has 360 bits, the LDPC codeword is divided into 45 bit groups. Alternatively, when an LDPC codeword in the length of 64800 is divided such that each bit group has 360 bits, the LDPC codeword may be divided into 180 bit groups. Further, the number of columns constituting the block interleaver 124 may be determined according to a modulation method. This will be explained in detail below.

Accordingly, the number of rows constituting each of the first part and the second part may be determined based on the number of columns constituting the block interleaver 124 , the number of bit groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of bit groups.

Specifically, in each of the plurality of columns, the first part may be formed of as many rows as the number of bits included in at least one bit group which can be written in each column in bit group wise from among the plurality of bit groups of the LDPC codeword, according to the number of columns constituting the block interleaver 124 , the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group.

In each of the plurality of columns, the second part may be formed of rows excluding as many rows as the number of bits included in at least some bit groups which can be written in each of the plurality of columns in bit group wise. Specifically, the number rows of the second part may be the same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver 124 . In other words, the number of rows of the second part may be the same value as a quotient when the number of bits included in the remaining bit groups which are not written in the first part from among bit groups constituting the LDPC codeword is divided by the number of columns.

That is, the block interleaver 124 may divide each of the plurality of columns into the first part including as many rows as the number of bits included in bit groups which can be written in each column in bit group wise, and the second part including the other rows.

Accordingly, the first part may be formed of as many rows as the number of bits included in bit groups, that is, as many rows as an integer multiple of M. However, since the number of codeword bits constituting each bit group may be an aliquot part of M as described above, the first part may be formed of as many rows as an integer multiple of the number of bits constituting each bit group.

In this case, the block interleaver 124 may interleave by writing and reading the LDPC codeword in the first part and the second part in the same method.

Specifically, the block interleaver 124 may interleave by writing the LDPC codeword in the plurality of columns constituting each of the first part and the second part in a column direction, and reading the plurality of columns constituting the first part and the second part in which the LDPC codeword is written in a row direction.

That is, the block interleaver 124 may interleave by writing the bits included in at least some bit groups which can be written in each of the plurality of columns in bit group wise in each of the plurality of columns of the first part serially, dividing the bits included in the other bit groups except the at least some bit groups and writing in each of the plurality of columns of the second part in a column direction, and reading the bits written in each of the plurality of columns constituting each of the first part and the second part in a row direction.

In this case, the block interleaver 124 may interleave by dividing the other bit groups except the at least some bit groups from among the plurality of bit groups based on the number of columns constituting the block interleaver 124 .

Specifically, the block interleaver 124 may interleave by dividing the bits included in the other bit groups by the number of a plurality of columns, writing each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and reading the plurality of columns constituting the second part, where the divided bits are written, in a row direction.

That is, the block interleaver 124 may divide the bits included in the other bit groups except the bit groups written in the first part from among the plurality of bit groups of the LDPC codeword, that is, the bits in the number of bit groups which correspond to the remainder when the number of bit groups constituting the LDPC codeword is divided by the number of columns, by the number of columns, and may write the divided bits in each column of the second part serially in a column direction.

For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R 1 number of rows. In addition, it is assumed that the LDPC codeword is formed of N group number of bit groups, the number of bit groups N group is not a multiple of C, and A×C+1=N group (A is an integer greater than 0). In other words, it is assumed that when the number of bit groups constituting the LDPC codeword is divided by the number of columns, the quotient is A and the remainder is 1.

In this case, as shown in FIGS. 28 and 29 , the block interleaver 124 may divide each column into a first part including R 1 number of rows and a second part including R 2 number of rows. In this case, R 1 may correspond to the number of bits included in bit groups which can be written in each column in bit group wise, and R 2 may be R 1 subtracted from the number of rows of each column.

That is, in the above-described example, the number of bit groups which can be written in each column in bit group wise is A, and the first part of each column may be formed of as many rows as the number of bits included in A number of bit groups, that is, may be formed of as many rows as A×M number.

In this case, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise, that is, A number of bit groups, in the first part of each column in the column direction.

That is, as shown in FIGS. 28 and 29 , the block interleaver 124 writes the bits included in each of bit group Y 0 , bit group Y 1 , . . . , group Y A−1 in the 1 st to R 1 th rows of the first part of the 1 st column, writes bits included in each of bit group Y A , bit group Y A+1 , . . . , bit group Y 2A−1 in the 1 st to R 1 th rows of the first part of the 2 nd column, . . . , writes bits included in each of bit group Y CA−A , bit group Y CA−A+1 , . . . , bit group Y CA−1 in the 1 st to R 1 th rows of the first part of the column C.

As described above, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise in the first part of each column.

In other words, in the above exemplary embodiment, the bits included in each of bit group (Y 0 ), bit group (Y 1 ), . . . , bit group (Y A−1 ) may not be divided and all of the bits may be written in the first column, the bits included in each of bit group (Y A ), bit group (Y A+1 ), . . . , bit group (Y 2A−1 ) may not be divided and all of the bits may be written in the second column, and the bits included in each of bit group (Y CA−A ), bit group (Y CA−A+1 ), . . . , group (Y CA−1 ) may not be divided and all of the bits may be written in the C column. As such, all bit groups interleaved by the first part are written in the same column of the first part.

Thereafter, the block interleaver 124 divides bits included in the other groups except the bit groups written in the first part of each column from among the plurality of bit groups, and writes the bits in the second part of each column in the column direction. In this case, the block interleaver 124 divides the bits included in the other bit groups except the bit groups written in the first part of each column by the number of columns, so that the same number of bits are written in the second part of each column, and writes the divided bits in the second part of each column in the column direction.

In the above-described example, since A×C+1=N group , when the bit groups constituting the LDPC codeword are written in the first part serially, the last bit group Y Ngroup-1 of the LDPC codeword is not written in the first part and remains. Accordingly, the block interleaver 124 divides the bits included in the bit group Y Ngroup-1 into C number of sub bit groups as shown in FIG. 28 , and writes the divided bits (that is, the bits corresponding to the quotient when the bits included in the last group (Y Ngroup-1 ) are divided by C) in the second part of each column serially.

The bits divided based on the number of columns may be referred to as sub bit groups. In this case, each of the sub bit groups may be written in each column of the second part. That is, the bits included in the bit groups may be divided and may form the sub bit groups.

That is, the block interleaver 124 writes the bits in the 1 st to R 2 th rows of the second part of the 1 st column, writes the bits in the 1 st to R 2 th rows of the second part of the 2 nd column, . . . , and writes the bits in the 1 st to R 2 th rows of the second part of the column C. In this case, the block interleaver 124 may write the bits in the second part of each column in the column direction as shown in FIG. 28 .

That is, in the second part, the bits constituting the bit group may not be written in the same column and may be written in the plurality of columns. In other words, in the above example, the last bit group (Y Ngroup-1 ) is formed of M number of bits and thus, the bits included in the last bit group (Y Ngroup-1 ) may be divided by M/C and written in each column. That is, the bits included in the last bit group (Y Ngroup-1 ) are divided by M/C, forming M/C number of sub bit groups, and each of the sub bit groups may be written in each column of the second part.

Accordingly, in at least one bit group which is interleaved by the second part, the bits included in the at least one bit group are divided and written in at least two columns constituting the second part.

In the above-described example, the block interleaver 124 writes the bits in the second part in the column direction. However, this is merely an example. That is, the block interleaver 124 may write the bits in the plurality of columns of the second parts in a row direction. In this case, the block interleaver 124 may write the bits in the first part in the same method as described above.

Specifically, referring to FIG. 29 , the block interleaver 124 writes the bits from the 1 st row of the second part in the 1 st column to the 1 st row of the second part in the column C, writes the bits from the 2 nd row of the second part in the 1 st column to the 2 nd row of the second part in the column C, . . . , etc., and writes the bits from the R 2 th row of the second part in the 1 st column to the R 2 th row of the second part in the column C.

On the other hand, the block interleaver 124 reads the bits written in each row of each part serially in the row direction. That is, as shown in FIGS. 28 and 29 , the block interleaver 124 reads the bits written in each row of the first part of the plurality of columns serially in the row direction, and reads the bits written in each row of the second part of the plurality of columns serially in the row direction.

Accordingly, the block interleaver 124 may interleave a part of the plurality of bit groups constituting the LDPC codeword in bit group wise, and divide and interleave some of the remaining bit groups. That is, the block interleaver 124 may interleave by writing the LDPC codeword constituting a predetermined number of bit groups from among the plurality of bit groups in the plurality of columns of the first part in bit group wise, dividing the bits of the other bit groups and writing the bits in each of the columns of the second part, and reading the plurality of columns of the first and second parts in the row direction.

As described above, the block interleaver 124 may interleave the plurality of bit groups in the methods described above with reference to FIGS. 27 to 29 .

In particular, in the case of FIG. 28 , the bits included in the bit group which does not belong to the first part are written in the second part in the column direction and read in the row direction. In view of this, the order of the bits included in the bit group which does not belong to the first part is rearranged. Since the bits included in the bit group which does not belong to the first part are interleaved as described above, Bit Error Rate (BER)/Frame Error Rate (FER) performance can be improved in comparison with a case in which such bits are not interleaved.

However, the bit group which does not belong to the first part may not be interleaved as shown in FIG. 29 . That is, since the block interleaver 124 writes and read the bits included in the group which does not belong to the first part in and from the second part in the row direction, the order of the bits included in the group which does not belong to the first part is not changed and the bits are output to the modulator 130 serially. In this case, the bits included in the group which does not belong to the first part may be output serially and mapped onto a modulation symbol.

In FIGS. 28 and 29 , the last single bit group of the plurality of bit groups is written in the second part. However, this is merely an example. The number of bit groups written in the second part may vary according to the total number of bit groups of the LDPC codeword, the number of columns and rows, the number of transmission antennas, etc.

The block interleaver 124 may have a configuration as shown in Tables 57 and 58 presented below:

Herein, C (or N C ) is the number of columns of the block interleaver 124 , R 1 is the number of rows constituting the first part in each column, and R 2 is the number of rows constituting the second part in each column.

Referring to Tables 57 and 58, the number of columns has the same value as a modulation order according to a modulation method, and each of a plurality of columns is formed of rows corresponding to the number of bits constituting the LDPC codeword divided by the number of a plurality of columns.

For example, when the length N ldpc of the LDPC codeword is 64800 and the modulation method is QPSK, the block interleaver 124 is formed of 2 columns as the modulation order is 2 in the case of QPSK, and each column is formed of rows as many as R 1 +R 2 =32400(=64800/2).

Meanwhile, referring to Tables 57 and 58, when the number of bit groups constituting an LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R 1 corresponds to the number of rows constituting each column, and R 2 is 0. In addition, when the number of bit groups constituting an LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the groups by dividing each column into the first part formed of R 1 number of rows, and the second part formed of R 2 number of rows.

When the number of columns of the block interleaver 124 is equal to the number of bits constituting a modulation symbol, bits included in a same bit group are mapped onto a single bit of each modulation symbol as shown in Tables 57 and 58.

For example, when N ldpc =64800 and the modulation method is QPSK, the block interleaver 124 may be formed of two (2) columns each including 32400 rows. In this case, a plurality of bit groups are written in the two (2) columns in bit group wise and bits written in the same row in each column are output serially. In this case, since two (2) bits constitute a single modulation symbol in the modulation method of QPSK, bits included in the same bit group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a bit group written in the 1 st column may be mapped onto the first bit of each modulation symbol.

Referring to Tables 57 and 58, the total number of rows of the block interleaver 124 , that is, R 1 +R 2 , is N ldpc /C.

In addition, the number of rows of the first part, R 1 , is an integer multiple of the number of bits included in each group, M (e.g., M=360), and maybe expressed as └N group /C┘×M, and the number of rows of the second part, R 2 , may be N ldpc /C−R 1 . Herein, └N group /C┘ is the largest integer below N group /C. Since R 1 is an integer multiple of the number of bits included in each group, M, bits may be written in R 1 in bit groups wise.

In addition, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, it can be seen from Tables 57 and 58 that the block interleaver 124 interleaves by dividing each column into two parts.

Specifically, the length of the LDPC codeword divided by the number of columns is the total number of rows included in the each column. In this case, when the number of bit groups of the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, each column is divided into two parts.

For example, it is assumed that the number of columns of the block interleaver 124 is identical to the number of bits constituting a modulation symbol, and an LDPC codeword is formed of 64800 bits as shown in Table 57. In this case, each bit group of the LDPC codeword is formed of 360 bits, and the LDPC codeword is formed of 64800/360 (=180) bit groups.

When the modulation method is QPSK, the block interleaver 124 may be formed of two (2) columns and each column may have 64800/2 (=32400) rows.

In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/2 (=90), bits can be written in each column in bit group wise without dividing each column into two parts. That is, bits included in 90 bit groups which is the quotient when the number of bit groups constituting the LDPC codeword is divided by the number of columns, that is, 90×360 (=32400) bits can be written in each column.

However, when the modulation method is 256-QAM, the block interleaver 124 may be formed of eight (8) columns and each column may have 64800/8(=8100) rows.

In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 180/8=22.5, the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight (8) columns into two parts to perform interleaving in bit group wise.

In this case, since the bits should be written in the first part of each column in bit group wise, the number of bit groups which can be written in the first part of each column in bit group wise is 22 which is the quotient when the number of bit groups constituting the LDPC codeword is divided by the number of columns, and accordingly, the first part of each column has 22×360 (=7920) rows. Accordingly, 7920 bits included in 22 bit groups may be written in the first part of each column.

The second part of each column has rows which are the rows of the first part subtracted from the total rows of each column. Accordingly, the second part of each column includes 8100-7920 (=180) rows.

In this case, the bits included in the other bit groups which have not been written in the first part are divided and written in the second part of each column.

Specifically, since 22×8 (=176) bit groups are written in the first part, the number of bit groups to be written in the second part is 180-176 (=4) (for example, bit group Y 176 , bit group Y 177 , bit group Y 178 , and bit group Y 179 from among bit group Y 0 , bit group Y 1 , bit group Y 2 , . . . , bit group Y 178 , and bit group Y 179 constituting the LDPC codeword).

Accordingly, the block interleaver 124 may write the four (4) bit groups which have not been written in the first part and remains from among the groups constituting the LDPC codeword in the second part of each column serially.

That is, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y 176 in the 1 st row to the 180 th row of the second part of the 1 st column in the column direction, and may write the other 180 bits in the 1 st row to the 180 th row of the second part of the 2 nd column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y 177 in the 1 st row to the 180 th row of the second part of the 3 rd column in the column direction, and may write the other 180 bits in the 1 st row to the 180 th row of the second part of the 4 th column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y 178 in the 1 st row to the 180 th row of the second part of the 5 th column in the column direction, and may write the other 180 bits in the 1 st row to the 180 th row of the second part of the 6 th column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the bit group Y 179 in the 1 st row to the 180 th row of the second part of the 7 th column in the column direction, and may write the other 180 bits in the 1 st row to the 180 th row of the second part of the 8 th column in the column direction.

Accordingly, the bits included in the bit group which has not been written in the first part and remains are not written in the same column in the second part and may be divided and written in the plurality of columns.

Hereinafter, the block interleaver of FIG. 23 according to an exemplary embodiment will be explained in detail with reference to FIG. 30 .

In a group-interleaved LDPC codeword (v 0 , v 1 , . . . , v N ldpc −1 ), Y j is continuously arranged like V={Y 0 , Y 1 , . . . Y N group −1 }.

The LDPC codeword after group interleaving may be interleaved by the block interleaver 124 as shown in FIG. 30 . In this case, the block interleaver 124 divide a plurality of columns into the first part (Part 1) and the second part (Part 2) based on the number of columns of the block interleaver 124 and the number of bits of bit groups. In this case, in the first part, the bits constituting the bit groups may be written in the same column, and in the second part, the bits constituting the bit groups may be written in a plurality of columns (i.e. the bits constituting the bit groups may be written in at least two columns).

Specifically, input bits v i are written serially from the first part to the second part column wise, and then read out serially from the first part to the second part row wise. That is, the data bits v i are written serially into the block interleaver column-wise starting in the first part and continuing column-wise finishing in the second part, and then read out serially row-wise from the first part and then row-wise from the second part. Accordingly, the bit included in the same bit group in the first part may be mapped onto a single bit of each modulation symbol.

In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 vary according to a modulation format and a length of the LDPC codeword as in Table 30 presented below. That is, the first part and the second part block interleaving configurations for each modulation format and code length are specified in Table 59 presented below. Herein, the number of columns of the block interleaver 124 may be equal to the number of bits constituting a modulation symbol. In addition, a sum of the number of rows of the first part, N r1 and the number of rows of the second part, N r2 , is equal to N ldpc /N C (herein, N C is the number of columns). In addition, since N r1 (=└N groop /N c ┘×360) is a multiple of 360, a multiple of bit groups may be written in the first part.

Hereinafter, an operation of the block interleaver 124 will be explained in detail.

Specifically, as shown in FIG. 30 , the input bit v i (0≤i<N C ×N r1 ) is written in r i row of c i column of the first part of the block interleaver 124 . Herein, c i and r i are

⁢ c i = ⌊ i N r ⁢ ⁢ 1 ⌋ ⁢ ⁢ and ⁢ ⁢ r i = ( i ⁢ ⁢ mod ⁢ ⁢ N r ⁢ ⁢ 1 ) ,

respectively.

In addition, the input bit v i (N C ×N r1 ≤i<N ldpc ) is written in an r i row of c i column of the second part of the block interleaver 124 . Herein, c i and r i satisfy

c i = ⌊ ( i - N C × N r ⁢ ⁢ 1 ) N r ⁢ ⁢ 2 ⌋ ⁢ ⁢ and ⁢ ⁢ r i = N r ⁢ ⁢ 1 + { ( i - N C × N r ⁢ ⁢ 1 ) ⁢ ⁢ mod ⁢ ⁢ N r ⁢ ⁢ 2 } ,

respectively.

An output bit q j (0≤j<N ldpc ) is read from c j column of r j row. Herein, r j and c j satisfy

r j = ⌊ j N c ⌋ ⁢ ⁢ and ⁢ ⁢ c j = ( j ⁢ ⁢ mod ⁢ ⁢ N C ) ,

respectively.

For example, when the length N ldpc of an LDPC codeword is 64800 and the modulation method is 256-QAM, the order of bits output from the block interleaver 124 may be (q 0 , q 1 , q 2 , . . . , q 63357 , q 63358 , q 63359 , q 63360 , q 63361 , . . . , q 64799 )=(v 0 , v 7920 , v 15840 , . . . , v 47519 , v 55439 , v 63359 , v 63360 , v 63540 , . . . , v 64799 ). Herein, the indexes of the right side of the foregoing equation may be specifically expressed for the eight (8) columns as 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, . . . , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, . . . , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

Hereinafter, the interleaving operation of the block interleaver 124 will be explained in detail.

The block interleaver 124 may interleave by writing a plurality of bit groups in each column in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

In this case, the number of columns constituting the block interleaver 124 may vary according to a modulation method, and the number of rows may be the length of the LDPC codeword/the number of columns. For example, when the modulation method is QPSK, the block interleaver 124 may be formed of 2 columns. In this case, when the length N ldpc of the LDPC codeword is 16200, the number of rows is 8100 (=16200/2), and, when the length N ldpc of the LDPC codeword is 64800, the number of rows is 32400 (=64800/2).

Hereinafter, the method for interleaving the plurality of bit groups in bit group wise by the block interleaver 124 will be explained in detail.

When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 may interleave by writing the bit groups as many as the number of bit groups divided by the number of columns in each column serially in bit group wise.

For example, when the modulation method is QPSK and the length N ldpc of the LDPC codeword is 64800, the block interleaver 124 may be formed of two (2) columns each including 32400 rows. In this case, since the LDPC codeword is divided into (64800/360=180) number of bit groups when the length N ldpc of the LDPC codeword is 64800, the number of bit groups (=180) of the LDPC codeword may be an integer multiple of the number of columns (=2) when the modulation method is QPSK.

In this case, as shown in FIG. 31 , the block interleaver 124 writes the bits included in each of the bit group Y 0 , bit group Y 1 , . . . , bit group Y 89 in the 1 st row to 32400 th row of the first column, and writes the bits included in each of the bit group Y 90 , the bit group Y 91 , . . . , the bit group Y 179 in the 1 st row to 32400 th row of the second column. In addition, the block interleaver 124 may read the bits written in each row of the two columns serially in the row direction.

However, when the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 may interleave by dividing each column into N number of parts (N is an integer greater than or equal to 2).

Specifically, the block interleaver 124 may divide each column into a part including as many rows as the number of bits included in the bit group which can be written in each column in bit group wise, and a part including the other rows, and may interleave by using the divided parts.

In this case, the block interleaver 124 may write at least some bit groups which can be written in each of the plurality of columns in bit group wise from among the plurality of bit groups in each of the plurality of columns serially, and then divides the bits included in the other bit groups into sub bit groups and writes the bits in the other area remaining in each of the plurality of columns after the at least some bit groups are written in bit group wise. That is, the block interleaver 124 may write the bits included in at least some bit groups which are writable in the first part of each column in bit group wise, and may divide the bits included in the other bit groups and writhe the bits in the second part of each column.

For example, when the modulation method is QPSK and the length N ldpc of the LDPC codeword is 16200, the block interleaver 124 may be formed of two (2) columns each including 8100 rows. In this case, since the LDPC codeword is divided into (16200/360=45) number of bit groups when the length N ldpc of the LDPC codeword is 16200, the number of bit groups (=45) of the LDPC codeword is not an integer multiple of the number of columns (=2) when the modulation method is QPSK. That is, a remainder exists.

In this case, the block interleaver 124 may divide each column into the first part including 7920 rows and the second part including 180 rows as shown in FIGS. 32 and 33 .

The block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise in the first part of each column in the column direction.

That is, as shown in FIGS. 32 and 33 , the block interleaver 124 writes the bits included in each of the bit group Y 0 , bit group Y 1 , . . . , bit group Y 21 in the 1 st row to 7920 th row of the first part of the first column, and writes the bits included in each of the bit group Y 22 , the bit group Y 23 , . . . , the bit group Y 43 in the 1 st row to 7920 th row of the first part of the second column.

As described above, the block interleaver 124 writes the bits included in the bit groups which can be written in each column in bit group wise in the first part of each column in bit group wise.

Thereafter, the block interleaver 124 divides the bits included in the other bit groups except for the bit groups written in the first part of each column from among the plurality of bit groups, and writes the bits in the second part of each column in the column direction. In this case, the block interleaver 124 may divide the bits included in the other bit groups except for the bit groups written in the first part of each column by the number of columns, such that the same number of bits are written in the second part of each column, and writes the divided bits in each column of the second part in the column direction.

For example, when the bit group Y 44 , which is the last bit group of the LDPC codeword, remains as shown in FIG. 32 , the block interleaver 124 divides the bits included in the bit group Y 44 by 2, and writes the divided bits in the second part of each column serially.

That is, the block interleaver 124 may write the bits in the 1 st row to 180 th row of the second part of the first column, and writes the bits in the 1 st row to 180 th row of the second part of the second column. In this case, the block interleaver 124 may write the bits in the second part of each column in the column direction as shown in FIG. 32 . That is, the bits constituting the bit group are not written in the same column in the second part and are written in the plurality of columns.

In the above-described example, the block interleaver 124 writes the bits in the second part in the column direction. However, this is merely an example. That is, the block interleaver 124 may write the bits in the plurality of columns of the second part in the row direction. However, the block interleaver 124 may write the bits in the first part in the same method as described above.

Specifically, referring to FIG. 33 , the block interleaver 124 may write the bits in the 1 st row of the second part of the first column to the 1 st row of the second part of the second column, writes the bits in the 2 nd row of the second part of the first column to the 2 nd row of the second part of the second column, . . . , writes the bits in the 180 th row of the second part of the first column to the 180 th row of the second part of the second column.

The block interleaver 124 reads the bits written in each row of each part serially in the row direction. That is, as shown in FIGS. 32 and 33 , the block interleaver 124 may read the bits written in each row of the first part of the plurality of columns serially in the row direction, and may read the bits written in each row of the second part of the plurality of columns serially in the row direction.

As described above, the block interleaver 124 may interleave the plurality of bit groups in the method described above with reference to FIGS. 31 to 33 .

The modulator 130 maps the interleaved LDPC codeword onto a modulation symbol. Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword, modulate the demultiplexed LDPC codeword, and map the LDPC codeword onto a constellation.

In this case, the modulator 130 may generate a modulation symbol using the bits included in each of a plurality of bit groups.

In other words, as described above, the bits included in different bit groups are written in each column of the block interleaver 124 , and the block interleaver 124 reads the bits written in each column in the row direction. In this case, the modulator 130 generates a modulation symbol by mapping the bits read in each column onto each bit of the modulation symbol. Accordingly, each bit of the modulation symbol belongs to a different group.

For example, it is assumed that the modulation symbol consists of C number of bits. In this case, the bits which are read from each row of C number of columns of the block interleaver 124 may be mapped onto each bit of the modulation symbol and thus, each bit of the modulation symbol consisting of C number of bits belong to C number of different groups.

Hereinbelow, the above feature will be described in greater detail.

First, the modulator 130 demultiplexes the interleaved LDPC codeword. To achieve this, the modulator 130 may include a demultiplexer (not shown) to demultiplex the interleaved LDPC codeword.

The demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, the demultiplexer (not shown) performs serial-to-parallel conversion with respect to the interleaved LDPC codeword, and demultiplexes the interleaved LDPC codeword into a cell having a predetermined number of bits (or a data cell).

For example, as shown in FIG. 34 , the demultiplexer (not shown) receives an LDPC codeword Q=(q 0 , q 1 , q 2 , . . . ) output from the interleaver 120 , outputs the received LDPC codeword bits to a plurality of substreams serially, converts the input LDPC codeword bits into cells, and outputs the cells.

In this case, bits having a same index in each of the plurality of substreams may constitute a same cell. Accordingly, the cells may be configured like (y 0,0 , y 1,0 , . . . , y ηMOD−1,0 )=(q 0 , q 1 , q ηMOD−1 ), (y 0,1 , y 1,1 , . . . , y ηMOD−1,1 )=(q ηMOD , q ηMOD+1 , . . . q 2×ηMOD−1 ), . . . .

Herein, the number of substreams, N substreams , may be equal to the number of bits constituting a modulation symbol, η MOD . Accordingly, the number of bits constituting each cell may be equal to the number of bits constituting a modulation symbol (that is, a modulation order).

For example, when the modulation method is QPSK, the number of bits constituting the modulation symbol, η MOD , is 2, and thus, the number of substreams, N substreams , is 2, and the cells may be configured like (y 0,0 , y 1,0 )=(q 0 , q 1 ), (y 0,1 , y 1,1 )=(q 2 ,q 3 ), (y 0,2 , y 1,2 )=(q 4 , q 5 ), . . . .

The modulator 130 may map the demultiplexed LDPC codeword onto modulation symbols.

Specifically, the modulator 130 may modulate bits (that is, cells) output from the demultiplexer (not shown) in various modulation methods. For example, when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, the number of bits constituting a modulation symbol, η MOD (that is, the modulation order), may be 2, 4, 6, 8, 10 and 12, respectively.

In this case, since each cell output from the demultiplexer (not shown) is formed of as many bits as the number of bits constituting a modulation symbol, the modulator 130 may generate a modulation symbol by mapping each cell output from the demultiplexer (not shown) onto a constellation point serially. Herein, a modulation symbol corresponds to a constellation point on a constellation.

However, the above-described demultiplexer (not shown) may be omitted according to circumstances. In this case, the modulator 130 may generate modulation symbols by grouping a predetermined number of bits from interleaved bits serially and mapping the predetermined number of bits onto constellation points. In this case, the modulator 130 may generate modulation symbols by mapping η MOD number of bits onto the constellation points serially according to a modulation method.

When an LDPC codeword is generated based on the parity check matrix defined as in Tables 4 to 21 and Tables 23 to 31, a plurality of bit groups of the LDPC codeword are interleaved by using interleaving parameters defined as in Tables 32 to 56 for the following reasons.

In general, when modulation is performed by using QPSK, encoding/decoding performance depends on how LDPC codeword bits are mapped onto two bits of a QPSK symbol.

In particular, when two parity bits are connected to a single check node in a parity check matrix, good performance can be guaranteed by mapping the two parity bits onto a single QPSK symbol. In addition, good performance can be guaranteed by mapping two parity bits connected to a single check node in the parity check matrix onto a single QPSK symbol. In addition, when there are a plurality of parity bits each connected to a single check node in a parity check matrix, good performance can be guaranteed by selecting two check nodes and mapping two parity bits connected to the two check nodes onto a single QPSK symbol.

Accordingly, after the LDPC codeword bits generated based on the parity check matrix defined as in Tables 4 to 21 and Tables 23 to 31 are group-interleaved based on Equation 21 and Tables 32 to 56, when the interleaved LDPC codeword bits are modulated by QPSK, two parity bits connected to a single check node may be mapped onto a same QPSK symbol or two parity bits connected to the selected two check nodes may be mapped onto a same QPSK symbol. Accordingly, encoding/decoding performance can be improved and the transmitting apparatus is robust to a burst error.

Specifically, since the order of bit groups to be written/read in the plurality of columns of the block interleaver 124 is determined according to the interleaving in bit group wise in the group interleaver 122 , bits to be mapped onto a modulation symbol may be determined according to the interleaving in bit group wise in the group interleaver 122 .

Accordingly, the group interleaver 122 may interleave the LDPC codeword bits in bit group wise such that bits belonging to a predetermined number of continuous bit groups, that is, bits connected to a predetermined number of same check nodes, are mapped onto a same QPSK symbol, by considering reliability of bits mapped onto a modulation symbol and performance of the codeword bits of the LDPC codeword. To achieve this, the group interleaver 122 may interleave the LDPC codeword bits in bit group wise based on Equation 21 and Tables 32 to 56.

Hereinafter, a method for designing the group interleaver 122 according to an exemplary embodiment will be explained. For the convenience of explanation, a method for defining π(j) with reference to Table 33 from among Tables 32 to 56 by way of an example will be explained.

In the case of the QPSK modulation method, the block interleaver 124 is formed of two columns, and two bits read and output from a same row of two columns configure a same QPSK symbol. Accordingly, bits of continuous bit groups from among the plurality of bit groups of the LDPC codeword should be written in a same row in each of the two columns of the block interleaver 124 to be mapped onto a same QPSK symbol.

That is, in order to map two parity bits connected to a single check node in the parity check matrix onto a same QPSK modulation symbol, bits belonging to two continuous bit groups to which the two parity bits belong should be written in a same row in each of the two columns of the block interleaver 124 .

When bits included in two continuous bit groups from the 25 th bit group to the 44 th bit group from among 45 bit groups constituting an LDPC codeword (that is, the 0 th to 44 th bit groups) should be mapped onto a same QPSK symbol for the purpose of improving encoding/decoding performance, and it is assumed that the 26 th bit group, 28 th bit group, . . . , 42 nd bit group, and 44 th bit groups are written in the 4321 st row to the 7920 th row of the first part of the first column of the block interleaver 124 as shown in (a) of FIG. 35 , the 25 th bit group, 27 th bit group, . . . , 41 st bit group, and 43 rd bit group should be written in the 4321 st row to the 7920 th row of the first part of the second column.

In this case, encoding/decoding performance depends on which bit groups are mapped onto a same modulation symbol (in the above-described example, two continuous bit groups from the 25 th bit group to the 44 th bit group are mapped onto the same modulation symbol). Therefore, the other bit groups may be randomly written in the block interleaver 124 .

That is, in the above-described example, the 0 th bit group to the 24 th bit group may be randomly written in the other rows of the first part and the second part which remain after the 25 th bit group to the 44 th bit group are written in the block interleaver 124 . For example, as shown in (a) of FIG. 35 , the 3 rd bit group, 22 nd bit group, 7 th bit group, . . . , 2 nd bit group, 23 rd bit group, 11 th bit group, 0 th bit group, 13 th bit group, . . . , 12 th bit group, and 16 th bit group may be written in the other rows of the first part, and the 8 th bit group may be written in the second part.

However, when the LDPC codeword bits are written in each column of the block interleaver 124 in bit group wise as shown in (a) of FIG. 35 , the bits included in the 25 th bit group to the 44 th bit group are mapped onto continuous QPSK symbols, and thus, are vulnerable to a bust error.

Accordingly, in order not to map the bits included in the 25 th bit group to the 44 th bit group onto continuous QPSK symbols, the rows of the block interleaver 124 may be randomly interleaved (row-wise random interleaving) as shown in (a) of FIG. 35 and the order of the bit groups to be written in the block interleaver 124 may be changed as shown in (b) of FIG. 35 .

As a result, when the group interleaver 122 interleaves a plurality of bit groups of an LDPC codeword in the order shown in Table 33, the plurality of bit groups of the LDPC codeword may be written in the block interleaver 124 in the order shown in (b) of FIG. 35 , and accordingly, parity bits included in two continuous bit groups may be mapped onto a same QPSK symbol.

That is, when the encoder 110 performs LDPC-encoding in a code rate of 7/15 based on a parity check matrix including an information word submatrix defined by the Table 6 and a parity submatrix having a dual diagonal configuration, and the plurality of bit groups of the LDPC codeword are interleaved by the group interleaver 122 based on π(j) defined by Table 33, the plurality of bit groups of the LDPC codeword may be written in the block interleaver 124 as shown in (b) of FIG. 35 , and thus, bits included in two continuous bit groups of 20 bit groups may be mapped onto a same modulation symbol.

In (a) and (b) of FIG. 35 , bits included in two continuous bit groups of the 20 bit groups from the 25 th bit group to the 44 th bit group are mapped onto a same modulation symbol. However, this is merely an example. The number of continuous bit groups to be mapped onto a same modulation symbol may vary according to a parity check matrix and a code rate. That is, when LDPC encoding is performed with a parity check matrix having a different configuration and at a different code rate, the number of continuous bit groups to be mapped onto a same modulation symbol may be changed.

Hereinafter, a method for defining π(j) with reference to Table 36 according to another exemplary embodiment will be explained.

In the case of the QPSK modulation method, the block interleaver 124 is formed of two columns, and two bits read and output from a same row of two columns configure a same QPSK symbol. Accordingly, bits of continuous bit groups from among a plurality of bit groups of an LDPC codeword should be written in a same row in each of two columns of the block interleaver 124 to be mapped onto a same QPSK symbol.

That is, in order to map two parity bits connected to a single check node in a parity check matrix onto a same QPSK modulation symbol, bits belonging to two continuous bit groups to which the two parity bits belong should be written in a same row in each of two columns of the block interleaver 124 .

When bits included in two continuous bit groups from the 39 th bit group to the 44 th bit group from among 45 bit groups constituting an LDPC codeword (that is, the 0 th to 44 th bit groups) should be mapped onto a same QPSK symbol for the purpose of improving encoding/decoding performance, and it is assumed that the 40 th bit group, 42 nd bit group, and 44 th bit groups are written in the 6841 st row to the 7920 th row of the first part of the first column of the block interleaver 124 as shown in (a) of FIG. 36 , the 39 th bit group, 41 st bit group, and 43 rd bit group should be written in the 6841 st row to the 7920 th row of the first part of the second column.

In this case, encoding/decoding performance depends on which bit groups are mapped onto a same modulation symbol (in the above-described example, two continuous bit groups from the 39 th bit group to the 44 th bit group are mapped onto a same modulation symbol). Therefore, the other bit groups may be randomly written in the block interleaver 124 .

That is, in the above-described example, the 0 th bit group to the 38 th bit group may be randomly written in the other rows of the first part and the second part which remain after the 39 th bit group to the 44 th bit group are written in the block interleaver 124 . For example, as shown in (a) of FIG. 36 , the 13 th bit group, 10 th bit group, 0 th bit group, . . . , 36 th bit group, 38 th bit group, 6 th bit group, 7 th bit group, 17 th bit group, . . . , 35 th bit group, and 37 th bit group may be written in the other rows of the first part, and the 1 st bit group may be written in the second part.

However, when LDPC codeword bits are written in each column of the block interleaver 124 in bit group wise as shown in (a) of FIG. 36 , bits included in the 39 th bit group to the 44 th bit group are mapped onto continuous QPSK symbols, and thus, are vulnerable to a bust error.

Accordingly, in order not to map bits included in the 39 th bit group to the 44 th bit group onto continuous QPSK symbols, the rows of the block interleaver 124 may be randomly interleaved (row-wise random interleaving) as shown in (a) of FIG. 36 and the order of the bit groups to be written in the block interleaver 124 may be changed as shown in (b) of FIG. 36 .

As a result, when the group interleaver 122 interleaves a plurality of bit groups of an LDPC codeword in the order shown in Table 36, the plurality of bit groups of the LDPC codeword may be written in the block interleaver 124 in the order shown in (b) of FIG. 36 , and accordingly, parity bits included in two continuous bit groups may be mapped onto a same QPSK symbol.

That is, when the encoder 110 performs LDPC-encoding in a code rate of 13/15 based on a parity check matrix including an information word submatrix defined by Table 12 and a parity submatrix having a dual diagonal configuration, and the plurality of bit groups of the LDPC codeword are interleaved by the group interleaver 122 based on π(j) defined by Table 36, the plurality of bit groups of the LDPC codeword may be written in the block interleaver 124 as shown in (b) of FIG. 36 , and thus, bits included in two continuous bit groups of 6 bit groups may be mapped onto a same modulation symbol.

In (a) and (b) of FIG. 36 , bits included in two continuous bit groups of the 6 bit groups from the 39 th bit group to the 44 th bit group are mapped onto a same modulation symbol. However, this is merely an example. The number of continuous bit groups to be mapped onto a same modulation symbol may vary according to a parity check matrix and a code rate. That is, when LDPC encoding is performed with a parity check matrix having a different configuration and at a different code rate, the number of continuous bit groups to be mapped onto a same modulation symbol may be changed.

In addition, since performance is greatly affected by which continuous bit groups are mapped onto a same modulation symbol, the other bit groups except for the continuous bit groups mapped onto the same modulation symbol may be randomly written in the plurality of columns as shown in (a) and (b) of FIG. 35 or (a) and (b) of FIG. 36 .

Accordingly, as long as a same bit group is mapped onto a same modulation symbol, interleaving may be regarded as being performed in the same method as the group interleaver presented in the present disclosure.

For example, in Table 60, A and A_perm indicate π(j) after/before row-wise random interleaving is performed, and B_perm, C_perm, D_perm, and E_perm indicate π(j) when row-wise random interleaving is performed after the other bit groups except for continuous bit groups are randomly written in the plurality of columns in different methods. Referring to Table 60, in B_perm, C_perm, D_perm, and E_perm, the same group as in A_perm is mapped onto a same modulation symbol. Accordingly, it can be seen that a same interleaving method as in A_perm is used for B_perm, C_perm, D_perm, and E_perm.

In the above-described example, an interleaving pattern in the case of a parity check matrix having the configuration of FIG. 20 has been described. Hereinafter, a method for designing an interleaving pattern when a parity check matrix has the configuration of FIG. 22 will be explained with reference to Table 32.

When there are bit groups formed of parity bits connected to a single check node from among a plurality of bit groups of the LDPC codeword, bits included in two bit groups selected from the corresponding bit groups should be written in a same row of two columns of the block interleaver 124 .

It is assumed that the 18 th bit group to the 44 th bit group from among the 45 bit groups (that is, 0 th to 44 th bit groups) of an LDPC codeword are bit groups formed of parity bits connected to a single check node connected to a single parity bit, and two bits are selected from the corresponding bit groups and 2880 (=8×360) QPSK symbols in total should be generated.

In this case, as shown in (a) of FIG. 37 , 8 bit groups randomly selected from among the 18 th bit group to the 44 th bit group should be written in the 5041 st row to the 7920 th row of the first part of the first column, and the other 8 bit groups randomly selected should be written in the 5041 st row to the 7920 th row of the first part of the second column.

Since encoding/decoding performance depends on how many QPSK symbols are formed of parity bits connected to a single check node connected to a single parity bit, the other bit groups may be randomly written in the block interleaver 124 .

Accordingly, the 29 bit groups which are not selected in the above-described example may be randomly written in the other rows of the first part, and the second part which remain after the selected groups are written in the block interleaver 124 . For example, as shown in (a) of FIG. 37 , the 0 th bit group, 17 th bit group, 38 th bit group, . . . , 37 th bit group, 5 th bit group, and 3 rd bit group may be written in the other rows of the first part, and the 8 th bit group may be written in the second part.

However, when LDPC codeword bits are written in each column of the block interleaver 124 in bit group wise as shown in (a) of FIG. 37 , a bust error may be intensively generated only in the parity bit, and thus, may undermine encoding/decoding performance of the LDPC code. Accordingly, the rows of the block interleaver 124 may be randomly interleaved as shown in (a) of FIG. 37 , and the order of the bit groups to be written in the block interleaver 124 may be changed as shown in (b) of FIG. 37 , so that a bust error does not affect only the parity bit if any.

As a result, when the group interleaver 122 interleaves a plurality of bit groups of an LDPC codeword in the order of Table 32, the plurality of bit groups of the LDPC codeword may be written in the block interleaver 124 in the order shown in (b) of FIG. 37 , and accordingly, a QPSK symbol formed of only parity bits connected to a check node connected to a single parity bit may be generated.

That is, when the encoder 110 performs LDPC encoding based on the parity check matrix defined in Table 26 at a code rate of 5/15, and the group interleaver 122 interleaves a plurality of bit groups of an LDPC codeword based on π(j) defined by Table 32, the plurality of bit groups of the LDPC codeword may be written in the block interleaver 124 as shown in (b) of FIG. 37 , and thus, bits included in two continuous bit groups of 16 bit groups may be mapped onto a same modulation symbol.

In (a) and (b) of FIG. 37 , only the 16 bit groups are randomly selected from the 18 th bit group to the 44 th bit group and a modulation symbol formed of only bits included in selected bit groups is generated. However, this is merely an example. The number of bit groups, corresponding to parity bits connected to a check node connected to a single parity bit, which are mapped onto a same modulation symbol, may be changed according to a parity check matrix and a code rate.

The transmitting apparatus 100 may transmit a modulation symbol to a receiving apparatus 1300 . For example, the modulator 130 may map the modulation symbol onto an Orthogonal Frequency Division Multiplexing (OFDM) frame using OFDM, and may transmit the modulation symbol mapped onto the OFDM frame to the receiving apparatus 1300 through an allocated channel.

FIG. 38 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment. Referring to FIG. 38 , the receiving apparatus 1500 includes a demodulator 1510 , a multiplexer 1520 , a deinterleaver 1530 and a decoder 1540 .

The demodulator 1510 receives and demodulates a signal transmitted from the transmitting apparatus 100 . Specifically, the demodulator 1510 generates a value corresponding to an LDPC codeword by demodulating the received signal, and outputs the value to the multiplexer 1520 . In this case, the demodulator 1510 may use a demodulation method corresponding to a modulation method used in the transmitting apparatus 100 . To do so, the transmitting apparatus 100 may transmit information regarding the modulation method to the receiving apparatus 1500 , or the transmitting apparatus 100 may perform modulation using a pre-defined modulation method between the transmitting apparatus 100 and the receiving apparatus 1500 .

The value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There are various methods for determining the channel value, and for example, a method for determining a Log Likelihood Ratio (LLR) value may be the method for determining the channel value.

The LLR value is a log value for a ratio of the probability that a bit transmitted from the transmitting apparatus 100 is 0 and the probability that the bit is 1. In addition, the LLR value may be a bit value which is determined by a hard decision, or may be a representative value which is determined according to a section to which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 belongs.

The multiplexer 1520 multiplexes the output value of the demodulator 1510 and outputs the value to the deinterleaver 1530 .

Specifically, the multiplexer 1520 is an element corresponding to a demultiplexer (not shown) provided in the transmitting apparatus 100 , and performs an operation corresponding to the demultiplexer (not shown). That is, the multiplexer 1520 performs an inverse operation of the operation of the demultiplexer (not shown), and performs cell-to-bit conversion with respect to the output value of the demodulator 1510 and outputs the LLR value in the unit of bit. However, when the demultiplexer (not shown) is omitted from the transmitting apparatus 100 , the multiplexer 1520 may be omitted from the receiving apparatus 1500 .

The information regarding whether the demultiplexing operation is performed or not may be provided by the transmitting apparatus 100 , or may be pre-defined between the transmitting apparatus 100 and the receiving apparatus 1500 .

The deinterleaver 1530 deinterleaves the output value of the multiplexer 1520 and outputs the values to the decoder 1540 .

Specifically, the deinterleaver 1530 is an element corresponding to the interleaver 120 of the transmitting apparatus 100 and performs an operation corresponding to the interleaver 120 . That is, the deinterleaver 1530 deinterleaves the LLR value by performing the interleaving operation of the interleaver 120 inversely.

To do so, the deinterleaver 1530 may include a block deinterleaver 1531 , a group twist deinterleaver 1532 , a group deinterleaver 1533 , and a parity deinterleaver 1534 as shown in FIG. 39 .

The block deinterleaver 1531 deinterleaves the output of the multiplexer 1520 and outputs a value to the group twist deinterleaver 1532 .

Specifically, the block deinterleaver 1531 is an element corresponding to the block interleaver 124 provided in the transmitting apparatus 100 and performs the interleaving operation of the block interleaver 124 inversely.

That is, the block deinterleaver 1531 deinterleaves by writing the LLR value output from the multiplexer 1520 in each row in the row direction and reading each column of the plurality of rows in which the LLR value is written in the column direction by using at least one row formed of the plurality of columns.

In this case, when the block interleaver 124 interleaves by dividing the column into two parts, the block deinterleaver 1531 may deinterleave by dividing the row into two parts.

In addition, when the block interleaver 124 writes and reads in and from the group that does not belong to the first part in the row direction, the block deinterleaver 1531 may deinterleave by writing and reading values corresponding to the group that does not belong to the first part in the row direction.

Hereinafter, the block deinterleaver 1531 will be explained with reference to FIG. 40 . However, this is merely an example and the block deinterleaver 1531 may be implemented in other methods.

An input LLR v i (0≤i<N ldpc ) is written in a r i row and a c i column of the block deinterleaver 1531 . Herein, c i =(i mod N c ) and

On the other hand, an output LLR q i (0≤i<N c ×N r1 ) is read from a c i column and a r i row of the first part of the block deinterleaver 1531 . Herein,

In addition, an output LLR q i (N c ×N r1 ≤i<N ldpc ) is read from a c i column and a r i row of the second part. Herein,

The group twist deinterleaver 1532 deinterleaves the output value of the block deinterleaver 1531 and outputs the value to the group deinterleaver 1533 .

Specifically, the group twist deinterleaver 1532 is an element corresponding to the group twist interleaver 123 provided in the transmitting apparatus 100 , and may perform the interleaving operation of the group twist interleaver 123 inversely.

That is, the group twist deinterleaver 1532 may rearrange the LLR values of the same bit group by changing the order of the LLR values existing in the same bit group. When the group twist operation is not performed in the transmitting apparatus 100 , the group twist deinterleaver 1532 may be omitted.

The group deinterleaver 1533 (or the group-wise deinterleaver) deinterleaves an output value of the group twist deinterleaver 1532 and outputs a value to the parity deinterleaver 1534 .

Specifically, the group deinterleaver 1533 is an element corresponding to the group interleaver 122 provided in the transmitting apparatus 100 and may perform the interleaving operation of the group interleaver 122 inversely.

That is, the group deinterleaver 1533 may rearrange the order of the plurality of bit groups in bit group wise. In this case, the group deinterleaver 1533 may rearrange the order of the plurality of bit groups in bit group wise by applying the interleaving method of Tables 32 to 56 inversely according to a length of the LDPC codeword, a modulation method and a code rate.

The parity deinterleaver 1534 performs parity deinterleaving with respect to an output value of the group deinterleaver 1533 and outputs a value to the decoder 1540 .

Specifically, the parity deinterleaver 1534 is an element corresponding to the parity interleaver 121 provided in the transmitting apparatus 100 and may perform the interleaving operation of the parity interleaver 121 inversely. That is, the parity deinterleaver 1534 may deinterleave the LLR values corresponding to the parity bits from among the LLR values output from the group deinterleaver 1533 . In this case, the parity deinterleaver 1534 may deinterleave the LLR value corresponding to the parity bits inversely to the parity interleaving method of Equation 8.

However, the parity deinterleaver 1534 may be omitted depending on the decoding method and embodiment of the decoder 1540 .

Although the deinterleaver 1530 of FIG. 38 includes three (3) or four (4) elements as shown in FIG. 39 , operations of the elements may be performed by a single element. For example, when bits each of which belongs to each of bit groups X a and X b constitute a single modulation symbol, the deinterleaver 1530 may deinterleave these bits to locations corresponding to their bit groups based on the received single modulation symbol.

For example, when the code rate is 13/15 and the modulation method is QPSK, the group deinterleaver 1533 may perform deinterleaving based on Table 36.

In this case, bits each of which belongs to each of bit groups Y 3 (=X 38 ) and Y 25 (=X 37 ) may constitute a single modulation symbol. Since one bit in each of the bit groups Y 3 (=X 38 ) and Y 25 (=X 37 ) constitutes a single modulation symbol, the deinterleaver 1530 may map bits onto decoding initial values corresponding to the bit groups Y 3 (=X 38 ) and Y 25 (=X 37 ) based on the received single modulation symbol.

The decoder 1540 may perform LDPC decoding by using the output value of the deinterleaver 1530 . To achieve this, the decoder 1540 may include an LDPC decoder (not shown) to perform the LDPC decoding.

Specifically, the decoder 1540 is an element corresponding to the encoder 110 of the transmitting apparatus 100 and may correct an error by performing the LDPC decoding by using the LLR value output from the deinterleaver 1530 .

For example, the decoder 1540 may perform the LDPC decoding in an iterative decoding method based on a sum-product algorithm. The sum-product algorithm is one example of a message passing algorithm, and the message passing algorithm refers to an algorithm which exchanges messages (e.g., LLR value) through an edge on a bipartite graph, calculates an output message from messages input to variable nodes or check nodes, and updates.

The decoder 1540 may use a parity check matrix when performing the LDPC decoding. In this case, the parity check matrix used in the decoding may have the same configuration as that of the parity check matrix used in the encoding of the encoder 110 , and this has been described above with reference to FIGS. 20 to 22 .

In addition, information on the parity check matrix and information on the code rate, etc. which are used in the LDPC decoding may be pre-stored in the receiving apparatus 1500 or may be provided by the transmitting apparatus 100 .

FIG. 41 is a flowchart to illustrate an interleaving method of a transmitting apparatus according to an exemplary embodiment.

First, an LDPC codeword is generated by LDPC encoding based on a parity check matrix (S 1710 ).

Thereafter, the LDPC codeword is interleaved (S 1720 ). In this case, the LDPC codeword may be interleaved such that bits included in continuous bit groups from among a plurality of bit groups of the LDPC codeword are mapped onto a same modulation symbol. In addition, when there are a plurality of check nodes connected only to a single parity bit in the parity check matrix of the LDPC codeword, the LDPC codeword may be interleaved such that bits included in bit groups corresponding to the parity bit connected to the corresponding check nodes are selectively mapped onto a same modulation symbol.

Then, the interleaved LDPC codeword is mapped onto a modulation symbol (S 1730 ). That is, the bits included in the continuous bit groups from among the plurality of bit groups of the LDPC codeword may be mapped onto a same modulation symbol. In addition, when there are a plurality of check nodes connected only to a single parity bit in the parity check matrix of the LDPC codeword, the bits included in bit groups corresponding to the parity bit connected to the corresponding check nodes may be selectively mapped onto a same modulation symbol.

Each of the plurality of bit groups may be formed of M number of bits, and M may be a common divisor of N ldpc and K ldpc and may be determined to satisfy Q ldpc =(N ldpc −K ldpc )/M. Herein, Q ldpc is a cyclic shift parameter value regarding columns in a column group of an information word submatrix of the parity check matrix, N ldpc is a length of the LDPC codeword, and K ldpc is a length of information word bits of the LDPC codeword.

Operation S 1720 may include parity-interleaving parity bits of the LDPC codeword, dividing the parity-interleaved LDPC codeword by the plurality of bit groups and rearranging an order of the plurality of bit groups in bit group wise, and interleaving the plurality of bit groups the order of which is rearranged.

The order of the plurality of bit groups may be rearranged in bit group wise based on the above-described Equation 21 presented above.

In Equation 21, π(j) is determined based on at least one of a length of the LDPC codeword and a code rate.

For example, when the LDPC codeword has a length of 16200, the modulation method is QPSK, and the code rate is 13/15, π(j) in Equation 21 may be defined as in Table 36 presented above.

Operation S 1720 may include dividing the LDPC codeword by the plurality of bit groups and rearranging an order of the plurality of bit groups in bit group wise, and interleaving the plurality of bit groups the order of which is rearranged.

The order of the plurality of bit groups may be rearranged in bit group wise based on Equation 21 presented above.

π(j) in Equation 21 may be determined based on at least one of a length of the LDPC codeword and a code rate.

For example, when the LDPC codeword has a length of 16200, the modulation method is QPSK, and the code rate is 5/15, π(j) in Equation 21 may be defined as in Table 32 presented above.

However, this is merely an example. The order of the plurality of bit groups may be rearranged in bit group wise by using one of Tables 32 to 56 and Equation 21.

The interleaving the plurality of bit groups may include: writing the plurality of bit groups in each of a plurality of columns in bit group wise in a column direction, and reading each row of the plurality of columns in which the plurality of bit groups are written in bit group wise in a row direction.

In addition, the interleaving the plurality of bit groups may include: serially write, in the plurality of columns, at least some bit group which is writable in the plurality of columns in bit group wise from among the plurality of bit groups, and then dividing and writing the other bit groups in an area which remains after the at least some bit group is written in the plurality of columns in bit group wise.

FIG. 42 is a block diagram illustrating a configuration of a receiving apparatus according to an exemplary embodiment.

Referring to FIG. 42 , a receiving apparatus 3800 may comprise a controller 3810 , an RF receiver 3820 , a demodulator 3830 and a service regenerator 3840 .

The controller 3810 determines an RF channel and a PLP through which a selected service is transmitted. The RF channel may be identified by a center frequency and a bandwidth, and the PLP may be identified by its PLP ID. A specific service may be transmitted through at least one PLP included in at least one RF channel, for each component constituting the specific service. Hereinafter, for the sake of convenience of explanation, it is assumed that all of data needed to play back one service is transmitted as one PLP which is transmitted through one RF channel. In other words, a service has only one data obtaining path to reproduce the service, and the data obtaining path is identified by an RF channel and a PLP.

The RF receiver 3820 detects an RF signal from an RF channel selected by a controller 3810 and delivers OFDM symbols, which are extracted by performing signal processing on the RF signal, to the demodulator 3830 . Herein, the signal processing may include synchronization, channel estimation, equalization, etc. Information required for the signal processing may be a value predetermined by the receiving apparatus 3810 and a transmitter according to use and implementation thereof and included in a predetermined OFDM symbol among the OFDM symbols and then transmitted to the receiving apparatus.

The demodulator 3830 performs signal processing on the OFDM symbols, extracts user packet and delivers the user packet to a service reproducer 3740 , and the service reproducer 3840 uses the user packet to reproduce and then output a service selected by a user. Here, a format of the user packet may differ depending on a service implementation method and may be, for example, a TS packet or a IPv4 packet.

FIG. 43 is a block diagram illustrating a demodulator according to an exemplary embodiment.

Referring to FIG. 43 , a demodulator 3830 may include a frame demapper 3831 , a BICM decoder 3832 for L1 signaling, a controller 3833 , a BICM decoder 3834 and an output handler 3835 .

The frame demapper 3831 selects a plurality of OFDM cells constituting an FEC block which belongs to a selected PLP in a frame including OFDM symbols, based on control information from the controller 3833 , and provides the selected OFDM cells to the BICM decoder 3834 . The frame demapper 3831 also selects a plurality of OFDM cells corresponding to at least one FEC block which includes L1 signaling, and delivers the selected OFDM cells to the BICM decoder 3832 for L1 signaling.

The BICM decoder for L1 signaling 3832 performs signal processing on an OFDM cell corresponding to an FEC block which includes L1 signaling, extracts L1 signaling bits and delivers the L1 signaling bits to the controller 3833 . In this case, the signal processing may include an operation of extracting an LLR value for decoding an LDPC codeword and a process of using the extracted LLR value to decode the LDPC codeword.

The controller 3833 extracts an L1 signaling table from the L1 signaling bits and uses the L1 signaling table value to control operations of the frame demapper 3831 , the BICM decoder 3834 and the output handler 3835 . FIG. 43 illustrates that the BICM decoder 3832 for L1 signaling does not use control information of the controller 3833 . However, when the L1 signaling has a layer structure similar to the layer structure of the above described L1 pre signaling and L1 post signaling, it is obvious that the BICM decoder 3832 for L1 signaling may be constituted by at least one BICM decoding block, and operation of this BICM decoding block and the frame demapper 3831 may be controlled by L1 signaling information of an upper layer.

The BICM decoder 3834 performs signal processing on the OFDM cells constituting FEC blocks which belong to a selected PLP to extract BBF (Baseband frame)s and delivers the BBFs to the output handler 3835 . In this case, the signal processing may include an operation of extracting an LLR value for decoding an LDPC codeword and an operation of using the extracted LLR value to decode the LDPC codeword, which may be performed based on control information output from the controller 3833 .

The output handler 3835 performs signal processing on a BBF, extracts a user packet and delivers the extracted user packet to a service reproducer 3840 . In this case, the signal processing may be performed based on control information output from the controller 3833 .

According to an exemplary embodiment, the output handler 3835 comprises a BBF handler(not shown) which extracts BBP (Baseband packet) from the BBF.

FIG. 44 is a flowchart provided to illustrate an operation of a receiving apparatus from a moment when a user selects a service until the selected service is reproduced, according to an exemplary embodiment.

It is assumed that service information on all services selectable by a user are acquired at an initial scan (S 4010 ) prior to the user's service selection (S 4020 ). Service information may include information on a RF channel and a PLP which transmits data required to reproduce a specific service in a current receiving apparatus. As an example of the service information, program specific information/service information (PSI/SI) in an MPEG2-TS is available, and normally can be achieved through L2 signaling and an upper-layer signaling.

In the initial scan (S 4010 ), comprehensive information on a payload type of PLPs which are transmitted to a specific frequency band. As an example, there may be information on whether every PLP transmitted to the frequency band includes a specific type of data.

When the user selects a service (S 4020 ), the receiving apparatus transforms the selected service to a transmitting frequency and performs RF signaling detection (S 4030 ). In the frequency transforming operation (S 4020 ), the service information may be used.

When an RF signal is detected, the receiving apparatus performs an L1 signaling extracting operation from the detected RF signal (S 4050 ). Then, the receiving apparatus selects a PLP transmitting the selected service, based on the extracted L1 signaling, (S 4060 ) and extracts a BBF from the selected PLP (S 4070 ). In S 4060 , the service information may be used.

The operation to extract a BBF (S 4070 ) may include an operation of demapping the transmitted frame and selecting OFDM cells included in a PLP, an operation of extracting an LLR value for LDPC coding/decoding from an OFDM cell, and an operation of decoding the LDPC codeword using the extracted LLR value.

The receiving apparatus, using header information of an extracted BBF, extracts a BBP from the BBF (S 4080 ). The receiving apparatus also uses header information of an extracted BBP to extract a user packet from the extracted BBP (S 4090 ). The extracted user packet is used to reproduce the selected service (S 4100 ). In the BBP extraction operation (S 4080 ) and user packet extraction operation (S 4090 ), L1 signaling information extracted in the L1 signaling extraction operation may be used.

According to an exemplary embodiment, the L1 signaling information includes information on types of a user packet transmitted through a corresponding PLP, and information on an operation used to encapsulate the user packet in a BBF. The foregoing information may be used in the user packet extraction operation (S 1480 ). Specifically, this information may be used in an operation of extracting the user packet which is a reverse operation of encapsulation of the user packet in the BBF. In this case, process for extracting user packet from the BBP(restoring null TS packet and inserting TS sync byte) is same as above description.

A non-transitory computer readable medium, which stores a program for performing the interleaving methods according to various exemplary embodiments in sequence, may be provided.

The non-transitory computer readable medium refers to a medium that stores data semi-permanently rather than storing data for a very short time, such as a register, a cache, and a memory, and is readable by an apparatus. Specifically, the above-described various applications or programs may be stored in a non-transitory computer readable medium such as a compact disc (CD), a digital versatile disk (DVD), a hard disk, a Blu-ray disk, a universal serial bus (USB), a memory card, and a read only memory (ROM), and may be provided.

At least one of the components, elements or units represented by a block as illustrated in FIGS. 19, 23, 34, 38 and 39 may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an exemplary embodiment. For example, at least one of these components, elements or units may use a direct circuit structure, such as a memory, processing, logic, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components, elements or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions. Also, at least one of these components, elements or units may further include a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Further, although a bus is not illustrated in the above block diagrams, communication between the components, elements or units may be performed through the bus. Functional aspects of the above exemplary embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components, elements or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.

The foregoing exemplary embodiments and advantages are merely exemplary and are not to be construed as limiting the present inventive concept. The exemplary embodiments can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments is intended to be illustrative, and not to limit the scope of the inventive concept, and many alternatives, modifications, and variations will be apparent to those skilled in the art.