Oversampled continuous-time pipeline ADC with digital signal reconstruction

The present disclosure relates generally to analog-to-digital converters (ADCs) and, more particularly, to oversampled continuous-time pipeline ADC with digital signal reconstruction.

In many electronics applications, an analog input signal is converted to a digital output signal (e.g., for further digital signal processing). For instance, in precision measurement systems, electronics are provided with one or more sensors to make measurements, and these sensors may generate an analog signal. The analog signal would then be provided to an ADC as input to generate a digital output signal for further processing. In another instance, an antenna generates an analog signal based on the electromagnetic waves carrying information/signals in the air. The analog signal generated by the antenna is then provided as input to an ADC to generate a digital output signal for further processing.

ADCs can be found in many places such as broadband communication systems, audio systems, receiver systems, etc. ADCs can translate analog electrical signals representing real-world phenomena, e.g., light, sound, temperature or pressure for data processing purposes. ADCs are used in a broad range of applications including Communications, Energy, Healthcare, Instrumentation and Measurement, Motor and Power Control, Industrial Automation and Aerospace/Defense. Designing an ADC is a non-trivial task because each application may have different needs in speed, performance, power, cost and size. As the applications needing ADCs grow, the need for accurate and reliable conversion performance also grows.

To provide a more complete understanding of the present disclosure and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying figures, wherein like reference numerals represent like parts, in which:

FIG. 1 is an illustrative system diagram of a multi-stage ADC, according to some embodiments of the disclosure;

FIG. 2 shows a continuous-time (CT) pipeline ADC, according to some embodiments of the disclosure;

FIGS. 3 and 4 show two discrete-time systems relating D N−1 and D N , according to some embodiments of the disclosure;

FIG. 5 shows a first digital filter B 1 (z) and a second digital filter A 1 (z) for processing D N−1 and D N respectively, according to some embodiments of the disclosure;

FIG. 6 shows a signal path from x N−1 (t) to x′ N−1 [kT S ], according to some embodiments of the disclosure;

FIG. 7 shows dither injection to estimate a transfer function relating D N−1 and D N , according to some embodiments of the disclosure;

FIG. 8 shows an exemplary CT pipeline ADC with digital signal reconstruction, according to some embodiments of the disclosure;

FIG. 9 shows an additional optional digital equalization filter E(z), according to some embodiments of the disclosure; and

FIG. 10 is a flow diagram illustrating a method for digital signal reconstruction in a CT multi-stage ADCs, according to some embodiments of the disclosure.

CT pipeline ADCs can achieve excellent performance, and avoid sampling-related artifacts traditionally associated with discrete-time pipeline ADCs. However, the CT circuitry in the ADCs can pose a challenge for digital signal reconstruction, since the transfer characteristics of the CT circuitry are not as well characterized or as simple as their discrete-time counterparts. To achieve perfect digital signal reconstruction, special techniques are used to implement an effective and efficient digital filter that combines the digital output signals from the stages of the CT ADCs.

Designing ADCs

ADCs are electronic devices that convert a continuous physical quantity carried by an analog signal to a digital number that represents the quantity's amplitude (or to a digital signal carrying that digital number). The conversion involves quantization of the analog input signal, so it would introduce a small amount of error. Typically the quantization occurs through periodic sampling of the analog input signal. The result is a sequence of digital values (i.e., a digital signal) that has converted a CT and continuous-amplitude analog input signal to a discrete-time and discrete-amplitude digital signal. An ADC can be defined by the following application requirements: its bandwidth (the range of frequencies of analog signals it can properly convert to a digital signal) and its resolution (the number of discrete levels the maximum analog signal can be divided into and represented in the digital signal). An ADC also has various specifications for quantifying ADC dynamic performance, including signal-to-noise-and-distortion ratio (SINAD), effective number of bits (ENOB), signal to noise ratio (SNR), total harmonic distortion (THD), total harmonic distortion plus noise (THD+N), and spurious free dynamic range (SFDR). ADCs have many different designs, which can be chosen based on the application requirements and performance specifications.

FIG. 1 is an illustrative system diagram of a multi-stage ADC converter, according to some embodiments of the disclosure. The multi-stage converter 100 includes a plurality of converter stages 110 . 0 - 110 .N, connected in series, in pipeline, or in cascading configuration. Each converter stage (referred herein as a stage) may receive a respective analog input signal (“x 0 ”, “x 1 ”, “x 2 ”, “x 3 ” . . . “x N4 ”, and “x N ”), and may generate a respective analog output signal (“x 1 ”, “x 2 ”, “x 3 ” . . . “x N−1 ”, and “x N ”) and a respective digital output signal (“D 0 ”, “D 1 ”, “D 2 ”, “D 3 ” . . . “D N−1 ”, and “D N ”). The respective analog output signals can be residues of the respective converter stages formed by summation/subtraction (e.g., x 1 is a residue of converter stage 110 . 0 ).

The converter stages can have the same number of bits for digital resolution, or the converter stages can have different numbers of bits for digital resolution. Each converter stage may generate respective digital output signals, which may be combined to form an overall digital output signal D OUT for the multi-stage converter 100 . The digital output signals (e.g., “D 0 ”, “D 1 ”, “D 2 ”, “D 3 ” . . . “D N−1 ”, and “D N ”) can be provided to a digital signal reconstruction filter 130 , which combines and/or filters the respective digital output signals and form the final converter digital output signal D OUT representing the analog input signal x 0 .

For simplicity, some signal paths may not be shown. For instance, in some cases, one or more converter stages may receive other analog input signals (e.g., analog input signals of the previous stages and/or analog input signals of subsequent stages).

The stages of the multi-stage ADC can be implemented with the same kind of converter architecture, or a combination of different converter architectures. Possible converter architectures include: DS modulation (e.g., as MASH ADCs), Flash conversion (e.g., as in pipeline ADCs), successive approximation register (SAR) conversion, and voltage-controlled-oscillator-based (VCO-based) conversion.

Multi-stage converter 100 can be a CT converter, which means that the converter stages has CT circuitry, and do not use discrete-time (DT) circuitry for conversion, e.g., switched-capacitor circuits. CT ADCs can operate with lower power and achieve better wideband performance than its DT counterparts. CT ADCs can avoid issues traditionally associated with switched-capacitor circuits in DT ADCs. However, CT converters can be more difficult to design. In some cases, the multi-stage converter 100 can be a hybrid CT-DT converter, where one or more stages uses CT circuitry, and one or more stages uses DT circuitry.

CT Pipeline ADC

A CT pipeline ADC based on the architecture shown in FIG. 1 comprises a plurality of CT converter stages, where within a CT converter stage, a fast ADC digitizes the input signal to the CT converter stage to generate the digital output signal of that CT converter stage. The fast ADC can be a Flash ADC comprising a bank of comparators. When there is a subsequent stage, the CT converter stage can reconstruct the input signal using digital-to-analog converter (DAC) to generate a reconstructed input signal, and form a residue for the CT converter stage by subtracting a delayed analog input signal to the stage by the reconstructed input signal. The delayed analog input signal can be formed by a CT delay circuit, where the delay provided by the CT delay circuit matches the delay of the ADC digitizing the input signal and the DAC reconstructing the input signal. The CT delay circuit can be optimized to minimize or reduce the peak of an analog residue waveform. The subtraction of the delayed analog input signal by the reconstructed input signal can be performed using CT circuitry. The subtraction can be performed by the CT circuitry through voltage domain subtraction or current domain subtraction.

FIG. 2 shows a CT pipeline ADC, according to some embodiments of the disclosure. A digital signal reconstruction filter is omitted in the FIGURE, for simplicity. The CT pipeline ADC has N+1 stages. As shown, the CT pipeline ADC has stage 0 , stage 1 , . . . stage N−1, and stage N.

Stage 0 comprises ADC 0 202 to digitize input signal x 0 (t) and generate a digital output signal D 0 . Stage 0 further includes a DAC 0 204 to reconstruct the input signal to the stage based on D 0 to generate a reconstructed signal. DAC 0 204 can have a transfer function g DAC (t) (or pulse shape). Stage 0 further includes a CT delay circuit 206 , which delays the input signal x 0 (t). The transfer function of the CT delay circuit 206 is shown as G delay (s). The amount of delay can match the delay of the ADC 0 202 and DAC 0 204 . The CT delay element can be implemented in different ways to provide different frequency responses, desired behaviors, and/or characteristic impedances. Exemplary circuitry for the CT delay circuit 206 includes resistor-capacitor (RC) lattice, one or more inductor-capacitor (LC) lattices, transmission line, etc. Stage 0 further includes CT circuitry for performing subtraction of the delayed input signal from the CT delay circuit 206 by the reconstructed signal from DAC 0 204 , shown as summation node 208 , to generate a residue signal. Stage 0 further includes a residue amplifier 210 to amplify the residue signal for conversion by Stage 1 and generate an amplified residue signal shown as x 1 (t). The residue amplifier 210 can have a transfer function, shown as H(s).

Stage 1 comprises ADC 1 212 to digitize an input signal to the stage, i.e., the amplified residue signal shown as x 1 (t), and generate a digital output signal D 1 . Stage 1 further includes a DAC 1 214 to reconstruct the input signal to the stage, i.e., the amplified residue signal x 1 (t), based on D 1 to generate a reconstructed signal. Stage 1 further includes a CT delay circuit 216 , which delays the input signal to the stage, i.e., the amplified residue signal x 1 (t). Stage 1 further includes CT circuitry for performing subtraction of the delayed input signal from the CT delay circuit 216 by the reconstructed signal from DAC 1 214 , shown as summation node 218 , to generate a residue signal. Stage 1 further includes a residue amplifier 220 to amplify the residue signal for conversion by Stage 2 and generate an amplified residue signal shown as x 2 (t).

The same architecture can be repeated for more stages of the CT pipeline ADC, if desired. For illustration, a second to the last stage, Stage N−1, is shown for the CT pipeline ADC. Stage N−1 comprises ADC N−1 222 to digitize an input signal to the stage, i.e., an amplified residue signal shown as x N−1 (t), and generate a digital output signal D N−1 . Stage N−1 further includes a DAC N−1 224 to reconstruct the input signal to the stage, i.e., the amplified residue signal x N−1 (t) based on D N−1 to generate a reconstructed signal. Stage N−1 further includes a CT delay circuit 226 , which delays the input signal to the stage, i.e., the amplified residue signal x N−1 (t). Stage N−1 further includes CT circuitry for performing subtraction of the delayed input signal from the CT delay circuit 226 by the reconstructed signal from DAC N−1 224 , shown as summation node 228 , to generate a residue signal. Stage N−1 further includes a residue amplifier 230 to amplify the residue signal for conversion by Stage N and generate an amplified residue signal shown as x N (t).

The last stage, Stage N, comprises ADC N 232 to digitize an input signal to the stage, i.e., amplified residue signal shown as x N−1 (t), and generate a digital output signal D N .

Transfer functions of the CT delay circuits, DACs, and residue amplifiers can depend on the analog circuitry therein. The transfer functions of such circuitry can also differ from stage to stage, since the analog circuitry therein may differ.

Digital Signal Reconstruction for DT Pipeline ADC

Referring back to FIG. 1 , a digital signal reconstruction filter 130 is included to combine the respective digital output signals (“D 0 ”, “D 1 ”, “D 2 ”, “D 3 ” . . . “D N−1 ”, and “D N ”) from the stages of multi-stage ADC. The technical task of the digital signal reconstruction filter 130 is to form the final converter digital output signal D OUT based on the respective digital output signals, where the final converter digital output signal D OUT is reconstructed in such a way to accurately represent the analog input signal x 0 .

One way to perform digital signal reconstruction is to start from the last digital output signal D N and combine D N with the digital output signal of the previous stage D N−1 to form a reconstructed input signal to the previous stage x′ N−1 . Then the result from combining D N and D N−1 can be combined with the digital output signal of a further previous stage D N−2 to form a reconstructed input signal to the further previous stage x′ N−2 . The digital signal reconstruction filter 130 can continue to work in this manner all the way to D 0 to form the final digital output signal D OUT , which would accurately represent the analog input signal x 0 .

If the multi-stage ADC is a DT pipeline ADC, the digital signal reconstruction filter 130 is straight forward. D N is multiplied by the step size of the DAC (G DAC ) and divided by the gain of the residue amplifier (H). D N−1 is multiplied by the step size of the DAC (G DAC ). To form x′ N−1 , D N ·G DAC /H and D N−1 ·G DAC are added together. x 0 can be reconstructed (i.e., finding x′ 0 ) according to the following:

Digital Signal Reconstruction for CT Pipeline ADC

Digital signal reconstruction filter 130 for a CT pipeline ADC is not as straight forward. The implementation and behavior of CT circuitry in the stages of the CT pipeline ADC complicates digital signal reconstruction, and finding a digital signal reconstruction filter 130 for a CT pipeline ADC is not trivial. Referring back to FIG. 2 , the DACs in the stages has a transfer function g DAC (t) (also referred to as the pulse shape), and the residue amplifiers in the stages has a transfer function H(s). For simplicity, all the stages are assumed to have the identical CT circuitry therein, but it does not have to be the case. An example of H(s) is as follows:

H ( s )= H 0 /(1+ s τ)  eq. (2)

H(s) can be of any suitable order and can have other definitions, and is not limited to the definition in Equation (2). The definition of H(s) would depend on the analog circuitry used for performing residue amplification. The technical task of the digital signal reconstruction filter 130 is to estimate a sampled version of the analog input signal x 0 (t), i.e., x′ 0 [kT s ], from the respective digital output signals (“D 0 ”, “D 1 ”, “D 2 ”, “D 3 ” . . . “D N−1 ”, and “D N ”) of the stages in the CT pipeline ADC. Similar to the approach used in the CT pipeline ADC, one way to perform digital signal reconstruction is to start from the last digital output signal D N and combine D N with the digital output signal of the previous stage D N−1 to determine a reconstructed digital output signal x′ N−1 [kT s ] which accurately represents the analog input signal to the previous stage x N−1 (t). Phrased differently, the digital signal reconstruction filter can estimate x N−1 (t) from D N−1 and D N . Then, the result from combining D N and D N−1 can be combined with the digital output signal of a further previous stage D N−2 to determine a reconstructed digital output signal x′ N−2 [kT s ] which accurately represents the analog input signal to the previous stage x N−2 (t). The digital signal reconstruction filter 130 can continue to work in this manner all the way to D 0 to form the final digital output signal D OUT , which would accurately represent the sampled version of the analog input signal x 0 (t), i.e., x′ 0 [kT s ].

To ensure proper digital signal reconstruction, it is desirable to ensure that all of the respective digital output signals (“D 0 ”, “D 1 ”, “D 2 ”, “D 3 ” . . . “D N−1 ”, and “D N ”) do not contribute to the final digital output signal D OUT , representing the sampled version of the analog input signal x 0 (t), i.e., x′ 0 [kT s ]. The cancellation of the respective digital output signals from the stages of the CT pipeline ADC during the digital signal reconstruction process is not trivial. The challenges in digital signal reconstruction are explained in the following passages.

A relationship between D N−1 and D N is characterized, and the relationship is used to determine reconstructed digital output signal x′ N−1 [kT s ]. Referring back to the last two stages of the CT pipeline converter of FIG. 2 , it can be seen that:

* is the convolution operator, and g delay (t) and h(t) denote the impulse responses of the CT delay circuit (CT delay circuit 226 ) and residue amplifier (residue amplifier 230 ) respectively. D N is the result of quantizing x N [kTs], and can be expressed as:

D N [ k ]= x N [ kT S ]+ e N [ k ]  eq. (4)

e N is the quantization noise introduced by the ADC in stage N (ADC N 232 ) at the end of the CT pipeline ADC.

As discussed previously, proper digital signal reconstruction at the end of the CT pipeline ADC aims to remove contribution of D N−1 from x′ N−1 [kT s ]. To understand how to remove contribution of D N−1 from x′ N−1 [kT s ], the relationship between D N−1 and D N (a sampled version of x N (t), i.e., x N [kTs]) is characterized first. Once the relationship between D N−1 and D N is characterized, it is possible to remove the contribution of D N−1 from x′ N−1 [kT s ].

FIGS. 3 and 4 show two DT systems relating D N−1 and D N , according to some embodiments of the disclosure. In FIGS. 2 and 3 , it can be seen that D N−1 drives a cascade of two filters with impulse responses g DAC (t) (associated with the DAC N−1 224 ) and −h(t) (associated with residue amplifier 230 and inversion due to subtraction at summation node 228 ) respectively. The output signal of the cascade of two filters is then sampled by sampler 302 representing the effect of the ADC in stage N (ADC N 232 ).

The final output signal of the signal path D N seen in FIG. 3 can be thought of as the result of filtering D N−1 by a DT system whose transfer function is shown as −A 1 (z)/B 1 (z) in FIG. 4 . In other words, −A 1 (z)/B 1 (z) relates D N−1 and D N , and represents the overall transfer function the DT system seen in FIG. 3 , i.e., the transfer function of the DAC (DAC N−1 224 ) and the transfer function of the residue amplifier (residue amplifier 230 ).

As mentioned previously, part of the technical task of digital signal reconstruction filter is to remove the contribution of D N−1 from the reconstructed digital output signal x′ N−1 [kT s ]. In other words, the transfer function D N−1 to x′ N−1 [kT s ] is preferably zero. Based on the transfer function −A 1 (z)/B 1 (z) of the DT system seen in FIG. 4 relating D N−1 and D N , it is possible to design a filter for filtering D N as part of the digital signal reconstruction filter to remove the contribution of D N−1 in x′ N−1 [kT s ]. Such a filter can inverse the transfer function−A 1 (z)/B 1 (z) of the DT system seen in FIG. 3 to cancel the contribution of D N−1 in x′ N−1 [kT s ].

In some embodiments, a digital signal reconstruction filter for a CT pipeline comprises a first digital filter to filter a first digital output signal from a first stage of the CT pipeline ADC (e.g., D N of stage N). The first digital filter can generate a first filtered digital output signal. The first digital filter can remove a contribution of a second digital output signal from a second stage (e.g., D N−1 of stage N−1) in front of the first stage of the CT pipeline ADC from a reconstructed digital output signal (e.g., x′ N−1 [kT s ]). The first digital filter can be determined based on a transfer function relating the second digital output signal (e.g., D N−1 ) and the first digital output signal (e.g., D N ). The transfer function can correspond to −A 1 (z)/B 1 (z) of the DT system seen in FIG. 4 , and the first digital filter can be designed to inverse the effect of the transfer function.

When using a single first digital filter B 1 (z)/A 1 (z) to filter D N to remove the contribution of D N−1 from x′ N−1 [kT s ], the single first digital filter may be anti-casual (e.g., B 1 (z)/A 1 (z) may be anti-causal) and possibly difficult or inefficient to implement efficiently in the digital domain. The following passages describe some techniques, which can be applied to make digital signal reconstruction more effective and efficient.

Designing an Effective and Efficient Digital Signal Reconstruction Filter

Rather than using just a single digital filter to filter D N to remove the contribution of D N−1 from x′ N−1 [kT s ], it is possible to use two digital filters to filter D N and D N−1 respectively to remove the contribution of D N−1 from x′ N−1 [kT s ]. The two digital filters creates equal and opposite signal paths for D N−1 to ensure that the contribution of D N−1 cancels out.

FIG. 5 shows a first digital filter B 1 (z) 504 and a second digital filter A 1 (z) 502 for processing D N−1 and D N respectively, according to some embodiments of the disclosure. The first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 are part of a digital signal reconstruction filter for processing the respective digital outputs of stages in a CT pipeline ADC.

In FIG. 5 , the first digital filter B 1 (z) 504 filters a first digital output signal D N from a first stage (stage N) of the CT pipeline ADC and generates a first filtered digital output signal, and the second digital filter A 1 (z) 502 filters a second digital output signal D N−1 from a second stage (stage N−1) in front of the first stage of the CT pipeline ADC (stage N−1) of the CT pipeline ADC to generate a second filtered digital output signal. A summer 506 can sum the first filtered digital output signal and the second filtered digital output signal to generate the reconstructed digital output signal x′ N−1 [kT S ]. Together, the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 can remove a contribution of the second digital output signal D N−1 of the second stage (stage N−1) from a reconstructed digital output signal x′ N−1 [kT S ].

The first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 can be determined based on a transfer function relating D N−1 and D N . Moreover, first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 can be designed to ensure that the transfer function relating D N−1 and the output of Path 1 508 (the second filtered digital output signal) and the transfer function relating D N−1 and the output of Path 2 510 (the first filtered digital output signal) are equal and opposite of each other. When the first filtered digital output signal and the second filtered digital output signal are summed, the contribution from D N−1 would cancel out. As seen in FIG. 5 , the transfer function relating D N−1 and the output of Path 1 508 is A 1 (z). As seen in FIG. 5 , the transfer function relating D N−1 and the output of Path 2 510 is a combination of −A 1 (z)/B 1 (z) (previously illustrated by FIGS. 3 and 4 ), and B 1 (z). In other words, the overall transfer function D N−1 and the output of Path 2 510 is (−A 1 /(z)/B 1 (z))·B 1 (z)=−A 1 (z). That means that the transfer function relating D N−1 and the output of Path 1 508 is equal and opposite of the transfer function relating D N−1 and the output of Path 2 510 (A 1 (z) is equal and opposite of −A 1 (z)). Accordingly, the contribution of the second digital output signal D N−1 is cancelled out and removed from a reconstructed digital output signal x′ N−1 [kT S ] after the first filtered digital output signal and the second filtered digital output signal are combined. Phrased differently, the second digital output signal D N−1 does not contribute to the reconstructed digital output signal x′ N−1 [kT S ]. Moreover, first digital filter B 1 (z) 504 and the second digital filter A 1 (z) can be implemented efficiently since it is not in the form of B 1 (z)/A 1 (z).

The first digital filter B 1 (z) 504 and the second digital filter A 1 (z) can be determined from a transfer function relating D N−1 and D N , represented by −A 1 (z)/B 1 (z) in FIG. 4 . The transfer function relating the second digital output signal D N−1 and the first digital output signal D N can, as seen in FIG. 3 , correspond to a transfer function of a (CT) digital-to-analog converter (DAC N−1 224 ) in the second stage and a transfer function of a CT residue amplifier (residue amplifier 230 ) amplifying a residue from the second stage and providing an amplified residue to the first stage.

In some embodiments, the transfer function relating D N−1 and D N , can be characterized by analytically determining the transfer function of DAC N−1 224 and the transfer function of the residue amplifier 230 based on the circuitry implementing DAC N−1 224 and the residue amplifier 230 . In some cases, the transfer function of the sampler 302 is also taken into account. Once the overall transfer function relating D N−1 and D N is determined analytically, it is possible to determine CT filter responses for the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 . Part of determining the filter responses for the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 can include determining DT equivalent filter responses based on the CT filter responses, and finding digital filter coefficients which effectively and efficiently approximates those DT equivalent filter responses. Preferably, the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 are implemented with finite impulse response (FIR) filters of a certain desirable length (or number of taps) for efficient digital implementation. In some cases, the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 are infinite impulse response (IIR) filters or approximations thereof. FIR filters are generally preferred, since they can be used at high speed.

FIG. 6 shows a signal path from x N−1 (t) to x′ N−1 [kT S ], based on the embodiment seen in FIG. 5 , according to some embodiments of the disclosure. x N−1 (t) experiences transfer function G delay (S) of the CT delay circuit 226 and the transfer function H(s) of the residue amplifier 230 . Then the output from the residue amplifier 230 is sampled by sampler 302 representing the effect of the ADC in stage N (ADC N 232 ). Also, the quantization noise e N from the ADC in stage N (ADC N 232 ) is introduced to the signal by summer 602 . The signal from the summer 602 is then processed by the first digital filter 504 B 1 (z). Note that the first digital filter B 1 (z) 504 filters the quantization noise e N , and thus first digital filter B 1 (z) 504 is part of the noise transfer function (NTF) of the CT pipeline converter.

Instead of starting with determining the transfer function relating D N−1 to D N , it is possible to select/determine one or more of the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 to achieve a particular result for the CT pipeline ADC by determining the rest of the variables accordingly. The variables in the filter design can include: the first digital filter B 1 (z) 504 , the second digital filter A 1 (z), the transfer function of DAC N−1 224 , the transfer function of the residue amplifier 230 , and the transfer function of sampler 302 (illustrated in FIG. 3 ). Referring back to FIG. 6 , the first digital filter B 1 (z) 504 can have an effect on the quantization noise e N , and thus first digital filter B 1 (z) 504 is part of the NTF of the CT pipeline converter (which includes the transfer function from e N to x′ N−1 [kT S ]). Put simply, first digital filter B 1 (z) 504 can suppress quantization noise e N . If a certain NTF is desired, it is possible to select the first digital filter B 1 (z) 504 to have a particular NTF or effect on filtering the quantization noise e N , and set the rest of the variables accordingly. For instance, it is possible to select the first digital filter B 1 (z) 504 , then design the residue amplifier 230 to have a particular transfer function such that conditions are met for proper digital signal reconstruction.

In some embodiments, the transfer function relating D N−1 and D N can be estimated through dither injection (as opposed to analytically through knowledge of the circuitry). FIG. 7 shows dither injection to estimate a transfer function relating D N−1 and D N , according to some embodiments of the disclosure. To estimate the transfer function, the CT pipeline ADC can include a dither signal generator 702 to inject a dither signal 704 to an input of a DAC in the second stage. The dither signal 704 is preferably a random signal which is uncorrelated with D N−1 . The dither signal 704 can be added to D N−1 such that the dither signal 704 can experience the signal path from D N−1 to D N . The CT pipeline ADC can further include processing logic 706 to correlate the dither signal 704 with the first digital output signal D N to estimate/extract the transfer function. The result of the correlation can correspond to the transfer function of the signal path from D N−1 to D N (thus the transfer function relating from D N−1 to D N ). Depending on where the dither signal is injected and which digital output signal is used for correlating with the injected dither signal, it is possible to extract a transfer function of a signal path from the node of where the dither signal is injected to the node of the digital output signal used for the correlation.

Processing logic 706 can be a microprocessor on-chip with the CT pipeline ADC executing instructions to perform the correlation. Dither injection and correlation can be performed in the background or in the foreground. Dither injection and correlation can be performed from time to time, e.g., to re-assess the transfer function if operating conditions change, to update filter coefficients accordingly.

Once the transfer function is extracted, a Steiglitz-McBride iteration can be applied to the extracted transfer function to determine filter responses for the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 . A Steiglitz-McBride iteration can find filter implementations for the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 which are efficient and can approximate the extracted transfer function. The processing logic 706 can write coefficients or updated coefficients 710 into first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 , whose coefficients can be programmable digitally.

Referring back to FIGS. 4 and 5 , the constraints on the filter design specifies the ratio between the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 . Therefore, it is possible to scale both of the filters by a same factor to achieve the same result. For instance, it may be desirable to scale the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) 502 in a manner such that a DC (direct current) gain of A 1 (z) is unity, so that the DC gain of B 1 (z) becomes 1/H 0 . In such instance, the suppression of e N at DC would be identical/comparable to the discrete-time counterpart (a DT pipeline ADC).

Referring back to FIGS. 3 and 4 , it can be seen that with the filtering configuration shown in FIG. 5 , A 1 (z)/B 1 (z) corresponds to a DT equivalent of a transfer function G delay (s)H(s). In some embodiments, first digital filter B 1 (z) 504 can be a DT equivalent of the denominator polynomial of the transfer function H(s) of residue amplifier 230 , scaled by 1/H 0 . With a first order H(s), first digital filter B 1 (z) 504 can be a two-tap FIR filter. Second digital filter A 1 (z) 502 can be a numerator polynomial of the DT equivalent of G delay (S)H(s). Second digital filter A 1 (z) 502 can also be a FIR filter.

Digital signal reconstruction shown in FIG. 7 can be extended to all stages of the CT pipeline ADC as illustrated by FIG. 2 . FIG. 8 shows an exemplary CT pipeline ADC with digital signal reconstruction, according to some embodiments of the disclosure. D N−1 is filtered by A 1 (z) as discussed previously, and more generally, D k is filtered by A N−k (Z) (e.g., D 1 is filtered by A N−1 (z), and D 0 is filtered by A N (z), and so on). A N−k (Z) can correspond to the numerator of the DT transfer function from D k to D N . x′ k+1 [kT S ] is filtered by filter B N−k (Z). The result from filtering D k by A N−k (Z) is combined (or summed) with the result from filtering x′ k+1 [kT S ] by filter B N−k (Z) to form x′ k [kT S ].

In the same fashion as the technique described in relation to FIG. 7 , the filters for digital signal reconstruction in FIG. 8 can be implemented with FIR filters filtering the respective digital output signals from the stages of the CT pipeline ADC. FIR filters are generally preferred, since they can be used at high speed. Higher order poles in the CT delay circuits and residue amplifiers in the CT pipeline ADC can potentially increase the length (number of taps) for the FIR filters.

B N−k (Z) can all be the same as B 1 (z). B 1 (z), which can correspond to the denominator polynomial of the transfer function H(s) of residue amplifier, can cancel the pole of the residue amplifier (assuming the CT delay circuit has a large bandwidth). A k (Z), which can correspond to a numerator polynomial of the DT equivalent of G delay (S)H(s), can represent the zeros of the DT equivalent transfer function from D N−k to D N .

In some cases, the number of taps for A k (Z) can increase with k, indicating that the FIR filters closer to the input of the CT pipeline ADC are longer. This characteristic of the digital signal reconstruction filter is consistent with the fact that the output of the stage 0 DAC, i.e., D 0 , is processed by a long chain of residue amplifiers and CT delay circuits. The long chain of residue amplifiers and CT delay circuits has a large influence and D 0 has to be cancelled out by the digital signal reconstruction process. Accordingly, A k (Z) can increase with k to account for the large influence of D 0 through the long chain of residue amplifiers and CT delay circuits.

As explained previously, it is possible to implement a single digital filter B 1 (z)/A 1 (z) to filter D N and remove the contribution of D N−1 from x′ N−1 [kT s ]. The single digital filter can be realizable as an IIR filter whose transfer function has a polynomial numerator and a polynomial denominator. But IIR filters in digital are not as fast as FIR filters, since FIR filters can operate at higher speeds (e.g., through interleaving). Rather than using just a single digital filter to filter D N to remove the contribution of D N−1 from x′ N−1 [kT s ], it is possible to use three FIR digital filters to remove the contribution of D N−1 from x′ N−1 [kT s ].

FIG. 9 shows an additional optional digital equalization filter E(z) 902 , according to some embodiments of the disclosure. Similar to the digital signal reconstruction filter in FIG. 8 , the digital signal reconstruction filter in FIG. 9 has the first digital filter B 1 (z) 504 and the second digital filter A 1 (z) for performing digital signal reconstruction. Additionally, an optional digital equalization filter E(z) 902 is included as part of the digital signal reconstruction filter for processing the respective digital outputs of stages in a CT pipeline ADC. In FIG. 9 , the first digital filter B 1 (z) 504 filters a first digital output signal D N from a first stage (stage N) of the CT pipeline ADC and generates a first filtered digital output signal, and the second digital filter A 1 (z) 502 filters a second digital output signal D N−1 from a second stage (stage N−1) in front of the first stage of the CT pipeline ADC (stage N−1) of the CT pipeline ADC to generate a second filtered digital output signal. A summer 506 can sum the first filtered digital output signal and the second filtered digital output signal. A result generated by or downstream from summer 506 can be filtered by digital equalization filter E(z) 902 to generate the reconstructed digital output signal x′ N−1 [kT S ]. In the example shown in FIG. 9 , E(z) 902 filters a result from summer 904 which combines the signals produced by A N (z) 806 and B N (z) 808 to generate the reconstructed digital output signal x′ 0 [kT S ].

With this filter configuration, it is possible to, in some cases, set E(z) to be 1/A 1 (z), if the desired (single) filter for filtering D N is B 1 (z)/A 1 (z) to remove the contribution of D N−1 from x′ N−1 [kT S ]. In other words, digital equalization filter E(z) can correspond to an inverse of the second digital filter A 1 (z) 502 to filter a combined signal downstream from the summer 506 to generate the reconstructed digital output signal. With E(z)=1/A 1 (z):

In Equation 5, it can be seen that x′ N−1 [kT S ] appears as D N processed by a filter having a transfer function of B 1 (z)/A 1 (z). Mathematically, the digital equalization filter E(z) 902 takes the polynomial denominator A 1 (z) out and applies 1/A 1 (z) in the end after all the filtered digital output signals are summed. Together, a first digital filter B 1 (z) 504 , a second digital filter A 1 (z) 502 , and a digital equalization filter E(z) 902 , can remove a contribution of the second digital output signal D N−1 of the second stage (stage N−1) from a reconstructed digital output signal x′ N−1 [kT S ], without requiring an IIR filter (i.e., having a polynomial numerator and polynomial denominator) in the digital signal reconstruction filter.

In some embodiments, at least one of the first digital filter B 1 (z) 504 , the second digital filter A 1 (z) 502 , and the digital equalization filter E(z) 902 is a FIR filter. In some embodiments, the first digital filter B 1 (z) 504 , the second digital filter A 1 (z) 502 , and the digital equalization filter E(z) 902 are FIR filters.

In some cases, E(z) 902 can be implemented to undo a low pass filter response of the signal path having the residue amplifiers and B(z)'s. In practice, E(z) 902 does not have to be exactly or precisely 1/A 1 (z). In some cases, the amplitude of E(z) 902 is similar to the amplitude of 1/A 1 (z) in a certain band of interest. Therefore, E(z) 902 can be implemented efficiently and can be made simpler than a filter which is exactly 1/A 1 (z).

Methods and Systems for Digital Signal Reconstruction

FIG. 10 is a flow diagram illustrating a method for digital signal reconstruction in a CT multi-stage ADCs, according to some embodiments of the disclosure. In 1002 . a first digital output signal from a first stage of the CT pipeline ADC is filtered by a first digital filter to generate a first filtered digital output signal. In 1004 , a second digital output signal from a second stage of the CT pipeline ADC is filtered by a second digital filter to generate a second filtered digital output signal. In 1006 , the first filtered digital output signal and the second filtered digital output signal are summed to generate a reconstructed digital output signal. Advantageously, the first digital output signal does not contribute to the reconstructed digital output signal. Preferably, the first digital filter and the second digital filter are FIR filters.

In some embodiments, the method can further include determining the first digital filter and the second digital filter based on a transfer function relating the first digital output signal and the second digital output signal.

In some cases, the transfer function can be estimated by injecting a dither signal to an input of a DAC of the first stage, and correlating the second digital output signal with the dither signal to estimate a transfer function relating the first digital output signal and the second digital output signal.

In some embodiments, the method can further include filtering a summed signal generated from summing the first filtered digital output signal and the second filtered output digital signal by a digital equalization filter, wherein, optionally, the digital equalization filter corresponds to an inverse of the first digital filter. Preferably, the digital equalization filter is a FIR filter.

A CT pipeline ADC can be implemented to perform conversion with digital signal reconstruction. The CT pipeline ADC can include a first CT converter stage for converting an analog input signal into a first digital output signal and generating a first amplified residue signal and a second CT converter stage for converting the first amplified residue signal into a second digital output signal. The CT pipeline ADC further includes a digital signal reconstruction filter to remove a contribution of a first digital output signal from a reconstructed output, wherein the digital signal reconstruction filter is determined based on a transfer function relating the first digital output signal and the second digital output signal.

In some embodiments, the digital signal reconstruction filter comprises: a first digital filter to filter the first digital output signal, a second digital filter to filter the second digital output signal, a summer to combine output signals of the first digital filter and the second digital filter, and an equalization filter to filter a result generated by or downstream the summer.

In some embodiments, the transfer function relating the first digital output signal and the second digital output signal is estimated by injecting a dither signal to an input of a DAC in the first CT converter stage and correlating the dither signal and the second digital output signal.

Example 1 is a method for digital signal reconstruction in a CT pipeline ADC, the method comprising: filtering a first digital output signal from a first stage of the CT pipeline ADC by a first digital filter to generate a first filtered digital output signal; filtering a second digital output signal from a second stage of the CT pipeline ADC by a second digital filter to generate a second filtered digital output signal; and summing the first filtered digital output signal and the second filtered digital output signal to generate a reconstructed digital output signal.

In Example 2, Example 1 can further include: determining the first digital filter and the second digital filter based on a transfer function relating the first digital output signal and the second digital output signal.

In Example 3, Example 1 or 2 can further include: injecting a dither signal to an input of a digital-to-analog converter of the first stage; and correlating the second digital output signal with the dither signal to estimate a transfer function relating the first digital output signal and the second digital output signal.

In Example 4, any one of Examples 1-3 can further include: the first digital output signal does not contribute to the reconstructed digital output signal.

In Example 5, any one of Examples 1-4 can further include: the first digital filter and the second digital filter being finite impulse response filters.

In Example 6, any one of Examples 1-5 can further include: filtering a summed signal generated from summing the first filtered digital signal and the second filtered digital signal by a digital equalization filter, wherein the digital equalization filter corresponds to an inverse of the first digital filter.

In Example 7, Example 6 can further include: the digital equalization filter being a finite impulse response filter.

Example 8 is a digital signal reconstruction filter for a CT pipeline ADC, the digital signal reconstruction filter comprising: a first digital filter to filter a first digital output signal from a first stage of the CT pipeline ADC, to generate a first filtered digital output signal, and to remove a contribution of a second digital output signal from a second stage in front of the first stage of the CT pipeline ADC from a reconstructed digital output signal; wherein the first digital filter is determined based on a transfer function relating the second digital output signal and the first digital output signal.

In Example 9, Example 8 can further include: a second digital filter to filter the second digital output signal to generate a second filtered digital output signal; and a summer to sum the first filtered digital output signal and the second digital output signal to generate the reconstructed digital output signal.

In Example 10, Example 9 can further include: a digital equalization filter to filter a combined signal downstream from the summer to generate the reconstructed digital output signal.

In Example 11, Example 10 can further include: at least one of the first digital filter, the second digital filter, and the digital equalization filter being a finite impulse response filter.

In Example 12, Example 10 can further include: the first digital filter, the second digital filter, and the digital equalization filter being finite impulse response filters.

In Example 13, any one of Examples 8-12 can further include: the transfer function relating the second digital output signal and the first digital output signal corresponding to a transfer function of a CT digital-to-analog converter in the second stage and a transfer function of a CT residue amplifier amplifying a residue from the second stage and providing an amplified residue to the first stage.

In Example 14, any one of Examples 8-13 can further include: a dither signal generator to inject a dither signal to an input of a digital-to-analog converter in the second stage.

In Example 15, any one of Examples 8-14 can further include: processing logic to correlate the dither signal with the first digital output signal to estimate the transfer function.

In Example 16, any one of Examples 8-15 can further include: the second digital output signal not contributing to the reconstructed digital output signal.

In Example 17, any one of Examples 8-16 can further include: the first digital filter suppressing a quantization noise of the first stage.

Example 18 is a CT pipeline ADC, the CT pipeline ADC comprising: a first CT converter stage for converting an analog input signal into a first digital output signal and generating a first amplified residue signal; a second CT converter stage for converting the first amplified residue signal into a second digital output signal; and a digital signal reconstruction filter to remove a contribution of a first digital output signal from a reconstructed output, wherein the digital signal reconstruction filter is determined based on a transfer function relating the first digital output signal and the second digital output signal.

In Example 19, Example 18 can further include the digital signal reconstruction filter comprising: a first digital filter to filter the first digital output signal; a second digital filter to filter the second digital output signal; a summer to combine output signals of the first digital filter and the second digital filter; and an equalization filter to filter a result generated by the summer.

In Example 20, Example 18 or 19 can further include the transfer function relating the first digital output signal and the second digital output signal being estimated by injecting a dither signal to an input of a digital-to-analog converter in the first CT converter stage and correlating the dither signal and the second digital output signal.

Example 21 is an apparatus comprising means for implementing and/or carrying out the methods of any one of Examples 1-7 and/or any of the functionalities described herein.

Other Implementation Notes, Variations, and Applications

The following passages are describing an example of digital signal reconstruction for CT pipeline ADC. However, the teachings herein are not limited to CT pipeline ADCs, but other CT multi-stage ADCs as well. The embodiments described herein can be applicable to a variety of converters, including other ADC architectures employing hybrid CT and DT circuit designs (which uses switched-capacitor circuits), etc.

The present architecture for digital signal reconstruction are particularly suitable for high speed, high precision applications where CT pipeline ADCs are used. Applications which can greatly benefit from the architecture include: instrumentation, testing, spectral analyzers, military purposes, radar, wired or wireless communications, mobile telephones (especially because standards continue to push for higher speed communications), and base stations.

In some embodiments, transfer function estimation can be implemented with an on-chip microprocessor (i.e., on-chip with the ADC, executing instructions/firmware provided to the on-chip microprocessor) or by dedicated on-chip digital hardware. In various other embodiments, the digital filters or digital functionalities may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other semiconductor architectures.

All of the specifications, dimensions, and relationships outlined herein (e.g., the number of processors, logic operations, etc.) have only been offered for purposes of example and teaching only. Such information may be varied considerably without departing from the spirit of the present disclosure, or the scope of the appended claims. The specifications apply only to one non-limiting example and, accordingly, they should be construed as such. In the foregoing description, example embodiments have been described with reference to particular processor and/or component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the present disclosure, appended claims. The description and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the FIGURES may be combined in various possible configurations, all of which are clearly within the broad scope of this Specification. In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of electrical elements. It should be appreciated that the electrical circuits of the FIGURES and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to a myriad of other architectures.

Note that in this Specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment”, “example embodiment”, “an embodiment”, “another embodiment”, “some embodiments”, “various embodiments”, “other embodiments”, “alternative embodiment”, and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments.

The functions related to protecting the tunable resistors, such as the processes shown in FIG. 10 , illustrate only some of the possible functions that may be executed by, or within, the circuits illustrated in the FIGURES or circuits coupled to the systems illustrated in the FIGURES (e.g., digital circuitry or an on-chip microprocessor). Some of these operations may be deleted or removed where appropriate, or these operations may be modified or changed considerably without departing from the scope of the present disclosure. In addition, the timing of these operations may be altered considerably. The preceding operational flows have been offered for purposes of example and discussion. Substantial flexibility is provided by embodiments described herein in that any suitable arrangements, chronologies, configurations, and timing mechanisms may be provided without departing from the teachings of the present disclosure.

Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the disclosure, appended claims. Note that all optional features of the apparatus described above may also be implemented with respect to the method or process described herein and specifics in the examples may be used anywhere in one or more embodiments.