Semiconductor device and method of manufacturing the same

This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2017-0164435 filed on Dec. 1, 2017, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

Inventive concepts relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including conductive patterns on a substrate and a method of manufacturing the same.

Semiconductor devices are beneficial in electronic industry because of their small size, multi-functionality, and/or low fabrication cost. Semiconductor device may be categorized as one of a semiconductor memory device storing logic data, a semiconductor logic device processing operations of logic data, and a hybrid semiconductor device having both memory and logic elements. A semiconductor device has been increasingly required for higher integration with the advanced development of the electronic industry. For example, a semiconductor device has been increasingly requested for higher reliability, higher speed, and/or multi-functionality. A semiconductor device is gradually complicated and integrated to meet these requested characteristics.

Some example embodiments of inventive concepts provide a semiconductor device with improved reliability due to reduction in process risk.

Some example embodiments of inventive concepts provide a method of manufacturing a semiconductor device in which the method has an improvement in reliability due to the reduction in process risk.

According to example embodiments of inventive concepts, a method of manufacturing a semiconductor device may comprise: providing a layout comprising a first group and a second group, the first group including a first pattern and a second pattern, the second group including a third pattern and a fourth pattern; examining a bridge risk region in the layout; biasing one end of at least one of the first and third patterns; and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns may be adjacent to the bridge risk region.

According to example embodiments of inventive concepts, a method of manufacturing a semiconductor device may comprise: providing a layout; performing a line-end biasing on the layout; and using the layout to form conductive patterns on a substrate. The operation of performing the line-end biasing comprises: examining a bridge risk region in the layout; biasing one end of at least one of patterns in the layout, the one end being adjacent to the bridge risk region; and performing a design rule check.

According to example embodiments of inventive concepts, a semiconductor device may comprise: a substrate; and first, second, third, and fourth conductive patterns on the substrate. The first to fourth conductive patterns may extend in parallel to each other in a first direction. The first to fourth conductive patterns may be sequentially arranged in a second direction crossing the first direction. The third conductive pattern may comprise on its one side a first extension protruding toward the first conductive pattern. The second conductive pattern may comprise on its one side a second extension protruding toward the fourth conductive pattern. The first extension and the second extension may be spaced apart from each other in the first direction. The first extension may be aligned in the second direction with one end of the first conductive pattern. The second extension may be aligned in the second direction with one end of the fourth conductive pattern.

FIG. 1 illustrates a block diagram showing a computer system for designing a semiconductor device, according to example embodiments of inventive concepts.

FIG. 2 illustrates a flow chart showing a method of designing and manufacturing a semiconductor device, according to example embodiments of inventive concepts.

FIG. 3 illustrates a plan view showing a layout according to example embodiments of inventive concepts.

FIGS. 4A, 5A, and 6A illustrate plan views showing a method of manufacturing a semiconductor device on a substrate based on the layout of FIG. 3 .

FIGS. 4B, 5B, and 6B illustrate cross-sectional views taken along line A-A′ of FIGS. 4A, 5A, and 6A , respectively.

FIG. 7 illustrates a detailed flow chart of a line-end biasing operation S 40 of FIG. 2 , showing a line-end biasing method according to example embodiments of inventive concepts.

FIGS. 8 to 12 illustrate plan views of layouts, showing a line-end biasing method according to example embodiments of inventive concepts.

FIG. 13 illustrates a plan view showing a semiconductor device fabricated on a substrate, based on the layout of FIG. 12 .

FIGS. 14 and 16 illustrate plan views of layouts, showing a line-end biasing method according to example embodiments of inventive concepts.

FIGS. 15 and 17 illustrate plan views showing a semiconductor device fabricated on a substrate, based on the layouts of FIGS. 14 and 16 , respectively.

FIG. 18 illustrates a flow chart showing a line-end biasing method according to example embodiments of inventive concepts.

FIGS. 19 to 27 illustrate plan views of layouts, showing a line-end biasing method according to example embodiments of inventive concepts.

FIG. 28 illustrates a plan view showing a semiconductor device fabricated on a substrate, based on the layout of FIG. 27 .

FIG. 1 illustrates a block diagram showing a computer system for designing a semiconductor device, according to example embodiments of inventive concepts. Referring to FIG. 1 , a computer system may include a central processing unit (CPU) 10 , a working memory 30 , an input/output (I/O) device 50 , and an auxiliary storage 70 . The computer system may be provided as a dedicated device for designing a layout according to example embodiments of inventive concepts. The computer system may be configured to drive various design and verification simulation programs.

The CPU 10 may allow the computer system to execute software (e.g., application programs, operating system, and device drivers). The CPU 10 may process an operating system loaded in the working memory 30 . The CPU 10 may execute various application programs driven based on the operating system. For example, the CPU 10 may process a layout design tool 32 , a placement and routing tool 34 , a line-end biasing tool 36 , and/or an OPC tool 38 loaded in the working memory 30 .

The operating system or application programs may be loaded in the working memory 30 . When the computer system is booted up, based on booting sequence, an operating system image (not shown) stored in the auxiliary storage 70 may be loaded to the working memory 30 . Overall input/output operations of the computer system may be supported by the operating system. Likewise, the working memory 30 may be loaded with the application programs that are selected by a user or provided for a basic service.

The layout design tool 32 for layout design may be loaded from the auxiliary storage 70 to the working memory 30 . The working memory 30 may be loaded from the auxiliary storage 70 with the placement and routing tool 34 that places designed standard cells and routes the placed standard cells.

The line-end biasing tool 36 may be loaded from the auxiliary storage 70 to the working memory 30 . The working memory 30 may be loaded from the auxiliary storage 70 with the OPC tool 38 that performs an optical proximity correction (OPC) on designed layout data.

The layout design tool 32 may include a bias function by which specific layout patterns are changed in shapes and positions defined by a design rule. In addition, the layout design tool 32 may perform a design rule check (DRC) under the changed bias data condition. The working memory 30 may be either a volatile memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) or a nonvolatile memory such as PRAM (Phase change Random Access Memory), MRAM (Magnetic Random Access Memory), ReRAM (Resistance Random Access Memory), FRAM (Ferroelectric Random Access Memory), or NOR Flash memory.

The line-end biasing tool 36 may include a bias function for changing layout patterns in the placed standard cells. For example, the line-end biasing tool 36 may extend or pull back one end of the layout pattern. The line-end biasing tool 36 may execute a design rule check (DRC) under the changed bias data condition.

The I/O device 50 may control user input/output operations of user interfaces. For example, the I/O device 50 may include a keyboard or a monitor, allowing a designer to put relevant information. The user may use the I/O device 50 to receive information about a semiconductor region or data paths requiring adjusted operating characteristics. The I/O device 50 may display a progress status or a process result of the OPC tool 38 .

The auxiliary storage 70 may serve as a storage medium for the computer system. The auxiliary storage 70 may store the application programs, the operating system image, and various data. The auxiliary storage 70 may be provided in the form of one among memory cards (e.g., MMC, eMMC, SD, and Micro SD) and a hard disk drive (HDD). The auxiliary storage 70 may include a NAND Flash memory having large memory capacity. Alternatively, the auxiliary storage 70 may include a NOR Flash memory or a next-generation volatile memory such as PRAM, MRAM, ReRAM, and FRAM.

A system interconnector 90 may be provided to serve as a system bus for providing a network in the computer system. The CPU 10 , the working memory 30 , the I/O device 50 , and the auxiliary storage 70 may be electrically connected through the system interconnector 90 and may exchange data with each other. The system interconnector 90 may not be limited to the above descriptions. For example, the system interconnector 90 may further include additional elements for increasing efficiency in data communication.

FIG. 2 illustrates a flow chart showing a method of designing and manufacturing a semiconductor device, according to example embodiments of inventive concepts.

Referring to FIG. 2 , a high-level description operation of a semiconductor integrated circuit may be performed using the computer system discussed with reference to FIG. 1 (S 10 ). The high-level description operation may mean that an integrated circuit corresponding to a design target is described with a high-level language of a hardware description language. For example, the high-level language such as C language may be used in the high level design process. A register transfer level (RTL) coding or simulation may be used to express circuits designed by the high-level design process. In addition, codes created by the RTL coding may be converted into a netlist, and the netlist may be synthesized to describe an entire semiconductor device. The synthesized schematic circuit may be verified by a simulation tool, and an adjustment process may be performed based on the verified result.

A layout design operation may be performed to implement on a silicon substrate a semiconductor integrated circuit that is logically completed (S 20 ). For example, the layout design operation may be performed based on the schematic circuit synthesized in the high-level design operation or the netlist corresponding to the schematic circuit. The layout design operation may include a routing process that places and connects various standard cells provided from a cell library, based on a prescribed design rule.

The cell library for the layout design operation may include information about operation, speed, and power consumption of the standard cell. A cell library for representing a layout of a specific gate-level circuit as a layout may be defined in the layout design tool. The layout may be prepared to define shapes or dimensions of patterns constituting transistors and metal lines that will be actually formed on a silicon substrate. For example, in order to actually form an inverter circuit on a silicon substrate, it may be necessary to appropriately place or describe layout patterns such as PMOS, NMOS, N-WELL, gate electrodes, and metal lines thereon. For this, a search may be first performed to select a suitable one of inverters predefined in the cell library.

A routing operation may be performed on the selected and placed standard cells (S 30 ). For example, high-level lines may be provided on the placed standard cells. The standard cells may be well-designedly connected to each other through the routing operation. The placement and routing of the standard cells may be automatically performed by the placement and routing tool 34 .

After the routing operation, the layout may be examined to determine whether or not a bridge risk region is present. When it is determined that the bridge risk region is present, the layout pattern may be biased (changed) in its line-end causing the bridge risk region (S 40 ). The line-end biasing tool 36 may execute the search of the bridge risk region and the biasing of the line-end.

A verification operation may be performed on the layout to check whether any portion of the schematic circuit violates the given design rule. The verification operation may include a design rule check (DRC) for verifying whether the layout meets the given design rule, an electrical rule check (ERC) for verifying whether there is an issue of an electrical disconnection in the layout, and a layout vs. schematic (LVS) for verifying whether the layout is coincident with the gate-level netlist.

An optical proximity correction (OPC) operation may be performed (S 50 ). A photolithography process may be employed to realize on a silicon substrate the layout patterns obtained by the layout design operation. The optical proximity correction operation may be a technique for correcting an unintended optical effect occurred in the photolithography process. For example, the optical proximity correction process may correct an undesirable phenomenon such as refraction or process side effects caused by characteristics of light in an exposure process using the layout patterns. When the optical proximity correction operation is performed, the designed layout patterns may be slightly changed in their shapes and positions.

A photomask may be generated based on the layout changed by the optical proximity correction operation (S 60 ). The photomask may generally be manufactured by describing the layout patterns using a chromium layer coated on a glass substrate.

The generated photomask may be used to manufacture a semiconductor device (S 70 ). Various exposure and etching processes may be repeatedly performed in fabricating the semiconductor device using the photomask. Through these processes described above, patterns defined in the layout design operation may be sequentially formed on a silicon substrate.

FIG. 3 illustrates a plan view showing a layout according to example embodiments of inventive concepts.

Referring to FIG. 3 , there may be provided a layout LA according to some example embodiments of inventive concepts. The layout LA of FIG. 3A may define conductive patterns that are supposed to be formed on one among stacked layers of a semiconductor device. For example, the conductive patterns may be or include contacts, wiring lines, or vias.

The layout LA may include first to fourth patterns LP 1 to LP 4 . Each of the first to fourth patterns LP 1 to LP 4 may have a linear or bar shape extending in a second direction D 2 . The first to fourth patterns LP 1 to LP 4 may be spaced apart from each other in a first direction D 1 . Neighboring ones of the first to fourth patterns LP 1 to LP 4 may be arranged at substantially the same pitch. For example, a pitch between the first pattern LP 1 and the second pattern LP 2 may be substantially the same as a pitch between the second pattern LP 2 and the third pattern LP 3 . The pitch between the second pattern LP 2 and the third pattern LP 3 may be substantially the same as a pitch between the third pattern LP 3 and the fourth pattern LP 4 . The term pitch may mean a distance in the first direction D 1 between one side of a pattern and one side of an adjacent pattern.

The first pattern LP 1 and the third pattern LP 3 may constitute a first group CL 1 . The second pattern LP 2 and the fourth pattern LP 4 may constitute a second group CL 2 . A first photomask may be fabricated based on the first group CL 1 , and a second photomask may be fabricated based on the second group CL 2 . For example, the layout LA of FIG. 3 may be used to separately fabricate a total of two photomasks. The first and second photomasks may be used to form respective patterns on a substrate. For example, the first and third patterns LP 1 and LP 3 included in the first group CL 1 of the layout LA may be displayed in the same first color, and the second and fourth patterns LP 2 and LP 4 included in the second group CL 2 of the layout LA may be displayed in the same second color.

FIGS. 4A, 5A, and 6A illustrate plan views showing a method of manufacturing a semiconductor device based on the layout of FIG. 3 . FIGS. 4B, 5B , and 6 B illustrate cross-sectional views taken along line A-A′ of FIGS. 4A, 5A, and 6A , respectively.

Referring to FIGS. 4A and 4B , a substrate 100 may be provided to include an active region. Although not shown, transistors may be disposed on the active region of the substrate 100 . An etching target layer ETL, a mask layer HM, and a first mold layer ML 1 may be sequentially formed on the substrate 100 . The etching target layer ETL and the mask layer HM may have etch selectivity to each other. The first photomask, which is fabricated based on the first group CL 1 of FIG. 3 , may be used to form a first photoresist pattern PR 1 on the first mold layer ML 1 . The first photoresist pattern PR 1 may be formed using a photolithography process. For example, the formation of the first photoresist pattern PR 1 may include forming a first photoresist layer on the first mold layer ML 1 and using the first photomask to perform exposure and development processes on the first photoresist layer.

The first photoresist pattern PR 1 may be used as an etching mask to sequentially etch the first mold layer ML 1 and the mask layer HM. A first hole IH 1 and a third hole IH 3 may then be formed to partially expose the etching target layer ETL. The first hole IH 1 and the third hole IH 3 may be defined respectively by the first pattern LP 1 and the third pattern LP 3 of FIG. 3 .

A pattern distortion may occur in the photolithography process. As a result, a first extension hole EH 1 may be formed at a region adjacent to an end EN 1 of the first hole IH 1 . The third hole IH 3 may include the first extension hole EH 1 . The first extension hole EH 1 may have a shape that protrudes in the first direction D 1 from the third hole IH 3 . For example, the first extension hole EH 1 may have a shape that protrudes from the third hole IH 3 toward the first hole IH 1 . When viewed in plan, the first extension hole EH 1 may be aligned in the first direction D 1 with the end EN 1 of the first hole IH 1 . For example, a line LI in the first direction D 1 passing through a center of the first extension hole EH 1 may substantially overlap the end EN 1 of the first hole IH 1 . In conclusion, the pattern distortion in the photolithography process may cause the third hole IH 3 to have a planar shape different from that of the third pattern LP 3 of FIG. 3 .

Referring to FIGS. 5A and 5B , the first photoresist pattern PR 1 and the first mold layer ML 1 may be removed. A second mold layer ML 2 may be formed to cover the mask layer HM. A third mold layer ML 3 may be formed on the second mold layer ML 2 . The second photomask, which is fabricated based on the second group CL 2 of FIG. 3 , may be used to form a second photoresist pattern PR 2 on the third mold layer ML 3 . The second photoresist pattern PR 2 may be formed using a photolithography process. For example, the formation of the second photoresist pattern PR 2 may include forming a second photoresist layer on the third mold layer ML 3 and using the second photomask to perform exposure and development processes on the second photoresist layer.

The second photoresist pattern PR 2 may be used as an etching mask to sequentially etch the third mold layer ML 3 , the second mold layer ML 2 , and the mask layer HM. A second hole IH 2 and a fourth hole IH 4 may then be formed to partially expose the etching target layer ETL. The second hole IH 2 and the fourth hole IH 4 may be defined respectively by the second pattern LP 2 and the fourth pattern LP 4 of FIG. 3 .

A pattern distortion may occur in the photolithography process. As a result, a second extension hole EH 2 may be formed at a region adjacent to an end EN 2 of the fourth hole IH 4 . The second hole IH 2 may include the second extension hole EH 2 . The second extension hole EH 2 may have a shape that protrudes from the second hole IH 2 toward the fourth hole IH 4 . When viewed in plan, the second extension hole EH 2 may be aligned in the first direction D 1 with the end EN 2 of the fourth hole IH 4 . The first extension hole EH 1 and the second extension hole EH 2 may adjoin each other. For example, the first extension hole EH 1 and the second extension hole EH 2 may be connected to each other. In conclusion, the pattern distortion in the photolithography process may cause the second hole IH 2 to have a planar shape different from that of the second pattern LP 2 of FIG. 3 .

Referring to FIGS. 6A and 6B , the second photoresist pattern PR 2 , the third mold layer ML 3 , and the second mold layer ML 2 may be removed. The mask layer HM having the first to fourth holes IH 1 to IH 4 may be used as an etching mask to etch the etching target layer ETL, forming first to fourth holes IH 1 to IH 4 in the etching target layer ETL.

The mask layer HM may be removed. The first to fourth holes IH 1 to IH 4 of the etching target layer ETL may be filled with a conductive material to form first to fourth conductive patterns IL 1 to IL 4 , respectively. The conductive material may include one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum).

The third conductive pattern IL 3 may include a first extension EP 1 , and the second conductive pattern IL 2 may include a second extension EP 2 . The first and second holes EH 1 and EH 2 may be filled with a conductive material to form the first and second extensions EP 1 and EP 2 , respectively. The first and second extensions EP 1 and EP 2 may be extremely close to each other. For example, the first and second extensions EP 1 and EP 2 may be in contact with each other. Thus, an electrical short may occur between the first and second extensions EP 1 and EP 2 . For example, a bridge (e.g., an electrical short between adjacent patterns) may occur between the second conductive pattern IL 2 and the third conductive pattern IL 3 , causing process defects on a semiconductor device.

FIG. 7 illustrates a detailed flow chart of the line-end biasing operation S 40 of FIG. 2 , showing a line-end biasing method according to example embodiments of inventive concepts. FIGS. 8 to 12 illustrate plan views of layouts, showing a line-end biasing method according to example embodiments of inventive concepts. FIG. 13 illustrates a plan view showing a semiconductor device fabricated on a substrate, based on the layout of FIG. 12 .

A line-end biasing method according to some example embodiments of inventive concepts may reduce or prevent the bridge discussed above with reference to FIGS. 3 and 4A to 6B . Referring to FIGS. 7 and 8 , the layout LA of FIG. 3 may be examined to determine whether or not a bridge risk region is present (S 410 ). There may be defined a first line LI 1 in the first direction D 1 passing through a first end LE 1 of the first pattern LP 1 included in the first group CL 1 . When neighboring ones of the first to fourth patterns LP 1 to LP 4 are arranged at one pitch, the first and third patterns LP 1 and LP 3 included in the first group CL 1 may be arranged at two pitches. The first line LI 1 may extend as much as two pitches from the first end LE 1 toward the third pattern LP 3 . The first line LI 1 may reach a first site CS 1 of the third pattern LP 3 included in the first group CL 1 .

A first bulging region BR 1 may be defined on the first site CS 1 of the third pattern LP 3 . The first bulging region BR 1 may define an area where formed is the first extension EP 1 discussed above with reference to FIG. 6A .

Referring to FIGS. 7 and 9 , there may be defined a second line LI 2 in the first direction D 1 passing through a second end LE 2 of the fourth pattern LP 4 included in the second group CL 2 . The second line LI 1 may extend as much as two pitches from the second end LE 2 toward the second pattern LP 2 . The second line LI 2 may reach a second site CS 2 of the second pattern LP 2 included in the second group CL 2 .

A second bulging region BR 2 may be defined on the second site CS 2 of the second pattern LP 2 . The second bulging region BR 2 may define an area where formed is the second extension EP 2 discussed above with reference to FIG. 6A .

Referring to FIGS. 7 and 10 , a bridge risk region BRR may be defined to indicate an area where the first bulging region BR 1 and the second bulging region BR 2 overlap each other. The bridge risk region BRR may define a zone where an electrical short occurs between the first and second extensions EP 1 and EP 2 discussed above with reference to FIG. 6A . For example, it may be examined to determine the presence of the area where the first bulging region BR 1 and the second bulging region BR 2 overlap each other, which attempt may ascertain whether or not the bridge risk region BRR is present.

Referring to FIGS. 7 and 11 , a biasing action may be performed on one or more of the first end LE 1 and the second end LE 2 adjacent to the bridge risk region BRR (S 420 ). For example, the first end LE 1 of the first pattern LP 1 may change in position. The second end LE 2 of the fourth pattern LP 4 may change in position.

The biasing method may include placing an extension pattern EX 1 or EX 2 on one or more of the first end LE 1 of the first pattern LP 1 and the second end LE 2 of the fourth pattern LP 4 . For example, a first extension pattern EX 1 may be placed on the first end LE 1 of the first pattern LP 1 , and a second extension pattern EX 2 may be placed on the second end LE 2 of the second pattern LP 2 .

Each of the first and second extension patterns EX 1 and EX 2 may have a bar shape extending in the second direction D 2 . Each of the first and second extension patterns EX 1 and EX 2 may have a width substantially the same as a width of each of the first to fourth patterns LP 1 to LP 4 . The first and second extension patterns EX 1 and EX 2 may have substantially the same length or different lengths from each other. For example, the length of each of the first and second extension patterns EX 1 and EX 2 may be the same as or greater than a length of each of the first and second bulging regions BR 1 and BR 2 .

Referring to FIGS. 7 and 12 , the first bulging region BR 1 may be redefined based on a biased first end LE 1 a of the first pattern LP 1 . The second bulging region BR 2 may be redefined based on a biased second end LE 2 a of the second pattern LP 2 . As the biasing action is performed on the first and second ends LE 1 and LE 2 of the first and second patterns LP 1 and LP 2 , the first bulging region BR 1 and the second bulging region BR 2 may not overlap each other but become spaced apart from each other in the second direction D 2 . For example, the bridge risk region BRR may not exist in the biased layout LA.

Referring to FIG. 13 , based on the biased layout LA of FIG. 12 , the first to fourth conductive patterns IL 1 to IL 4 may be formed on the substrate 100 . The formation of the first to fourth conductive patterns IL 1 to IL 4 may be similar to that discussed above with reference to FIGS. 4A to 6B . The first extension EP 1 of the third conductive pattern IL 3 may be aligned in the first direction D 1 with a first end EN 1 of the first conductive pattern IL 1 . The second extension EP 2 of the second conductive pattern IL 2 may be aligned in the first direction D 1 with a second end EN 2 of the fourth conductive pattern IL 4 .

The first extension EP 1 of the third conductive pattern IL 3 shown in FIG. 13 may be spaced apart in the second direction D 2 from the second extension EP 2 of the second conductive pattern IL 2 . A semiconductor device according to some example embodiments of inventive concepts may not have the bridge, shown above in FIG. 6A , between the second and third conductive patterns IL 2 and IL 3 .

FIGS. 14 and 16 illustrate plan views of layouts, showing a line-end biasing method according to example embodiments of inventive concepts. FIGS. 15 and 17 illustrate plan views showing a semiconductor device fabricated on a substrate, based on the layouts of FIGS. 14 and 16 , respectively.

Referring to FIGS. 7, 14, and 15 , a biasing action may be performed on one or more of the first end LE 1 and the second end LE 2 adjacent to the bridge risk region BRR (S 420 ). For example, the biasing method may include placing a first extension pattern EX 1 on the first end LE 1 of the first pattern LP 1 . The first end LE 1 alone may be biased, while the second end LE 2 may not be biased.

When the first end LE 1 is sufficiently biased, for example, when the first end LE 1 extends as much as at least the first bulging region BR 1 , the bridge risk region BRR may be removed. As illustrated in FIG. 15 , the first extension EP 1 may be spaced apart in the second direction D 2 from the second extension EP 2 , which arrangement may in turn reduce or prevent the bridge.

Alternatively, referring to FIGS. 7, 16, and 17 , a biasing action may be performed on one or more of the first end LE 1 and the second end LE 2 adjacent to the bridge risk region BRR (S 420 ). The biasing method may include pulling back the first end LE 1 of the first pattern LP 1 . For example, the biasing method may include removing a portion PA that constitutes the first end LE 1 of the first pattern LP.

When the first end LE 1 is sufficiently biased, for example, when the first end LE 1 is pulled back as much as at least the first bulging region BR 1 , the bridge risk region BRR may be removed. As illustrated in FIG. 17 , the second extension EP 2 may be spaced apart in the second direction D 2 from the first extension EP 1 , which arrangement may in turn reduce or prevent the bridge.

FIG. 18 illustrates a flow chart showing a line-end biasing method according to example embodiments of inventive concepts. FIGS. 19 to 27 illustrate plan views of layouts, showing a line-end biasing method according to example embodiments of inventive concepts. FIG. 28 illustrates a plan view showing a semiconductor device fabricated on a substrate, based on the layout of FIG. 27 . In the example embodiments that follow, a detailed description of technical features repetitive to those discussed above with reference to FIGS. 7 to 13 will be omitted, and a difference thereof will be explained in more detail.

Referring to FIGS. 18 and 19 , a layout LA may be provided to include first to thirteenth patterns LP 1 to LP 13 (S 400 ). Each of the first to thirteenth patterns LP 1 to LP 13 may have a linear or bar shape extending in a second direction D 2 . Neighboring ones of the first to thirteenth patterns LP 1 to LP 13 may be arranged at substantially the same pitch.

The second, fourth, sixth, eighth, tenth, and thirteenth patterns LP 2 , LP 4 , LP 6 , LP 8 , LP 10 , and LP 13 may constitute a first group. The first, third, fifth, seventh, ninth, eleventh, and twelfth patterns LP 1 , LP 3 , LP 5 , LP 7 , LP 9 , LP 11 , and LP 12 may constitute a second group. A first photomask may be fabricated based on the first group, and a second photomask may be fabricated based on the second group.

Referring to FIGS. 18 and 20 , the layout LA may be examined to determine whether or not a bridge risk region is present (S 410 ). Based on one end of the fourth pattern LP 4 , a first bulging region BR 1 may be defined on one side of the sixth pattern LP 6 . Based on one end of the eighth pattern LP 8 , a first bulging region BR 1 may be defined on an opposite side of the sixth pattern LP 6 and one side of the tenth pattern LP 10 . Based on one end of the first pattern LP 1 , a second bulging region BR 2 may be defined on one side of the third pattern LP 3 . Based on one end of the third pattern LP 3 , a second bulging region BR 2 may be defined on one side of the first pattern LP 1 . Based on an opposite end of the third pattern LP 3 , a second bulging region BR 2 may be defined on one side of the fifth pattern LP 5 . Based on one end of the seventh pattern LP 7 , a second bulging region BR 2 may be defined on an opposite side of the fifth pattern LP 5 and one side of the ninth pattern LP 9 . Based on one end of the eleventh pattern LP 11 , a second bulging region BR 2 may be defined on an opposite side of the ninth pattern LP 9 . Based on one end of the twelfth pattern LP 12 , a second bulging region BR 2 may be defined on the opposite side of the ninth pattern LP 9 .

Between the ninth pattern LP 9 and the tenth pattern LP 10 , a first bridge risk region BRR 1 may be defined to indicate an area where the first bulging region BR 1 and the second bulging region BR 2 overlap each other. Between the fifth pattern LP 5 and the sixth pattern LP 6 , a second bridge risk region BRR 2 may be defined to indicate an area where the first bulging region BR 1 and the second bulging region BR 2 overlap each other. The overlapping area between the first and second bulging regions BR 1 and BR 2 may be examined to ascertain whether or not the bridge risk region is present in the layout LA of FIG. 20 .

Referring to FIGS. 18 and 21 , a first biasing action may be performed on pattern ends adjacent to the bridge risk region (S 420 ). A biasing action may be performed on an end of each of the eighth and eleventh patterns LP 8 and LP 11 adjacent to the first bridge risk region BRR 1 . A biasing action may be performed on an end of each of the fourth and seventh patterns LP 4 and LP 7 adjacent to the second bridge risk region BRR 2 . For example, a first extension pattern EX 1 may be placed on the end of each of the fourth and eighth patterns LP 4 and LP 8 . A second extension pattern EX 2 may be placed on the end of each of the seventh and eleventh patterns LP 7 and LP 11 .

The biased layout LA may undergo a design rule check (DRC) for verifying whether or not any portion violates a design rule (S 430 ). The twelfth pattern LP 12 and the second extension pattern EX 2 placed on the eleventh pattern LP 11 may be spaced apart in the second direction D 2 from each other at a distance less than a minimum distance defined by the design rule. For example, a design rule violation (DRV) may exist between the twelfth pattern LP 12 and the second extension pattern EX 2 placed on the eleventh pattern LP 11 .

Referring to FIGS. 18 and 22 , a cancel action may be performed on the biased eleventh pattern LP 11 that violates the design rule (S 440 ). For example, the second extension pattern EX 2 may be removed from the end of the eleventh pattern LP 11 . The design rule may then be satisfied between the eleventh pattern LP 11 and the twelfth pattern LP 12 .

Referring to FIGS. 18 and 23 , the biased layout LA may be reexamined to determine whether or not the bridge risk region is present (S 410 ). Based on the one end of the fourth pattern LP 4 , a first bulging region BR 2 may be defined on one side of the second pattern LP 2 and the one side of the sixth pattern LP 6 . Based on the one end of the eighth pattern LP 8 , a first bulging region BR 1 may be defined on the opposite side of the sixth pattern LP 6 and the one side of the tenth pattern LP 10 . Based on the one end of the first pattern LP 1 , a second bulging region BR 2 may be defined on the one side of the third pattern LP 3 . Based on the one end of the third pattern LP 3 , a second bulging region BR 2 may be defined on the one side of the first pattern LP 1 . Based on the opposite end of the third pattern LP 3 , a second bulging region BR 2 may be defined on the one side of the fifth pattern LP 5 . Based on the one end of the seventh pattern LP 7 , a second bulging region BR 2 may be defined on the opposite side of the fifth pattern LP 5 and the one side of the ninth pattern LP 9 . Based on the one end of the eleventh pattern LP 11 , a second bulging region BR 2 may be defined on the opposite side of the ninth pattern LP 9 . Based on one end of the twelfth pattern LP 12 , a second bulging region BR 2 may be defined on the opposite side of the ninth pattern LP 9 .

Between the ninth pattern LP 9 and the tenth pattern LP 10 , a third bridge risk region BRR 3 may be defined to indicate an area where the first bulging region BR 1 and the second bulging region BR 2 overlap each other. Between the second pattern LP 2 and the third pattern LP 3 , a fourth bridge risk region BRR 2 may be defined to indicate an area where the first bulging region BR 1 and the second bulging region BR 2 overlap each other. Although the first biasing action removes the first and second bridge risk regions BRR 1 and BRR 2 discussed above, it may be ascertained that the third and fourth bridge risk regions BRR 3 and BRR 4 are newly formed.

Referring to FIGS. 18 and 24 , a second biasing action may be performed on pattern ends adjacent to the bridge risk region (S 420 ). A biasing action may be performed on an end of each of the eighth and twelfth patterns LP 8 and LP 12 adjacent to the third bridge risk region BRR 3 . A biasing action may be performed on an end of each of the first and fourth patterns LP 1 and LP 4 adjacent to the fourth bridge risk region BRR 4 . For example, a first extension pattern EX 1 may be placed on the end of each of the fourth and eighth patterns LP 4 and LP 8 . A second extension pattern EX 2 may be placed on the end of each of the first and twelfth patterns LP 1 and LP 12 .

The biased layout LA may undergo a design rule check (DRC) for verifying whether or not any portion violates a design rule (S 430 ). The twelfth pattern LP 12 and the second extension pattern EX 2 placed on the eleventh pattern LP 11 may be spaced apart in the second direction D 2 from each other at a distance less than a minimum distance defined by the design rule. For example, a design rule violation (DRV) may exist between the twelfth pattern LP 12 and the second extension pattern EX 2 placed on the eleventh pattern LP 11 .

Referring to FIGS. 18 and 25 , a cancel action may be performed on the biased twelfth pattern LP 12 that violates the design rule (S 440 ). For example, the second extension pattern EX 2 may be removed from the end of the twelfth pattern LP 12 . The design rule may then be satisfied between the eleventh pattern LP 11 and the twelfth pattern LP 12 .

Referring to FIGS. 18 and 26 , the biased layout LA may be reexamined to determine whether or not the bridge risk region is present (S 410 ). First bulging regions BR 1 may be defined based on the end of each of the second, fourth, and eighth patterns LP 2 , LP 4 , and LP 8 . Second bulging regions BR 2 may be defined based on the end of each of the third, seventh, eleventh, and twelfth patterns LP 3 , LP 7 , LP 11 , and LP 12 . The layout LA of FIG. 26 may have therein no overlapping area between the first bulging region BR 1 and the second bulging region BR 2 . For example, it may be ascertained that the bridge risk region does not exist in the layout LA of FIG. 26 .

Referring to FIGS. 18 and 27 , a final layout LA may be obtained from the layout that has experienced the first biasing action and the second biasing action. For example, each of the first and second extension patterns EX 1 and EX 2 may be combined with its connected pattern, thereby completing the final layout LA.

Referring to FIG. 28 , based on the layout LA of FIG. 27 , first to twelfth conductive patterns IL 1 to IL 12 may be formed on the substrate 100 . The formation of the first to twelfth conductive patterns IL 1 to IL 12 may be similar to that discussed above with reference to FIGS. 4A to 6B .

Each of the second, fourth, sixth, and tenth conductive patterns IL 2 , IL 4 , IL 6 , and IL 10 may include a first extension EP 1 . The first extension EP 1 may correspond to the first bulging region BR 1 discussed above in FIG. 26 . The sixth conductive pattern IL 6 may include a first extension EP 1 at one side thereof and a first extensions EP 1 at an opposite side thereof.

Each of the first, fifth, and ninth conductive patterns ILL IL 5 , and IL 9 may include a second extension EP 2 . The second extension EP 2 may correspond to the second bulging region BR 2 discussed above in FIG. 26 . The fifth conductive pattern IL 5 may include a second extension EP 2 at one side thereof and a second extension EP 2 at an opposite side thereof. The ninth conductive pattern IL 9 may include a second extension EP 2 at one side thereof and a plurality of second extensions EP 2 at an opposite side thereof.

A semiconductor device according to some example embodiments of inventive concepts may be fabricated by a layout design including a line-end biasing action. When a plurality of photomasks are used to form conductive patterns on a substrate, a bridge may be reduced or prevented between the conductive patterns. In conclusion, the semiconductor device may be provided to have improved reliability.

Although example embodiments of the present inventive concepts have been discussed with reference to accompanying figures, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concepts. It therefore will be understood that the example embodiments described above are just illustrative but not limitative in all aspects.