Dynamic amplifier and related gain boosting method

1. Field of the Invention

The present invention relates to a dynamic amplifier, and more particularly, to a gain boosting technique applicable to a dynamic amplifier.

2. Description of the Prior Art

A dynamic amplifier has been widely applied in various circuitries, such as an analog to digital converter (ADC), an integrator and an output buffer. Both a dynamic amplifier and a general operational amplifier provide a specific gain for amplifying input signals. The difference between the dynamic amplifier and the general operational amplifier is that, the general operational amplifier performs continuous-time operations while the dynamic amplifier performs discrete-time operations. Thus, the dynamic amplifier is applicable to a discrete-time circuit system such as a residue amplifier of a pipeline ADC and a discrete-time delta-sigma modulator (DSM) ADC.

The dynamic amplifier receives a differential pair of input signals, which generate differential currents for charging or discharging the output capacitors to amplify the input signals. A clock dynamically controls the amplifier to perform the amplification, as the name “dynamic amplifier” implies. In the dynamic amplifier, the gain A may be obtained as follows:

A = g m I d × Δ ⁢ ⁢ V CM ;

wherein g m equals the transconductance of the input differential pair of the amplifier, I d equals the current of the differential pair, and ΔV CM is the variation of common-mode voltage of the output terminals which changes due to signal amplification. In addition, ΔV CM may be obtained as follows:

Δ ⁢ ⁢ V CM = I d · T int C ;

wherein C is the capacitance value of the output capacitors, and T int is integrating time of the amplification.

In order to boost the gain A of the dynamic amplifier, the variation of common-mode voltage ΔV CM may be increased by increasing the integrating time T int . However, the variation of common-mode voltage ΔV CM is limited under the power supply voltage V DD of the dynamic amplifier, which further limits the gain A.

In the prior art, gain boosting is realized by including additional capacitor pairs in the dynamic amplifier, where charging/discharging operations are implemented in two steps on different capacitors, allowing extension of the integrating time T int . However, this implementation requires more capacitors such that the circuit cost may increase, and higher power consumption is required due to the increasing number of capacitors.

Thus, there is a need for improvement over the prior art.

It is therefore an objective of the present invention to provide a novel gain boosting technique for a dynamic amplifier, to realize higher gain and also prevent the above problems.

An embodiment of the present invention discloses a dynamic amplifier, which comprises a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.

Another embodiment of the present invention discloses a dynamic amplifier, which comprises a first output capacitor, a second output capacitor, a first cutoff switch, a second cutoff switch, a current source, an amplification control switch, a voltage detector, a first reset switch, a second reset switch, a coupling capacitor and a level shifter. The first cutoff switch is coupled between the first output capacitor and a first voltage detection node. The second cutoff switch is coupled between the second output capacitor and a second voltage detection node. The amplification control switch is coupled to the current source, the first voltage detection node and the second voltage detection node. The voltage detector is coupled to the first voltage detection node, the second voltage detection node, the first cutoff switch and the second cutoff switch. The first reset switch is coupled between the first voltage detection node and a power source. The second reset switch is coupled between the second voltage detection node and the power source. The level shifter is coupled to the voltage detector via the coupling capacitor.

Another embodiment of the present invention discloses a gain boosting method for a dynamic amplifier. The gain boosting method comprises resetting an output voltage of a first terminal of the output capacitor to a power supply voltage; charging or discharging the output capacitor with a charge or discharge current to perform amplification, to increase or decrease the output voltage; and shifting the output voltage by switching a second terminal of the output capacitor coupled to a first reference voltage node to be coupled to a second reference voltage node.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 is a schematic diagram of a general dynamic amplifier.

FIG. 2 illustrates an exemplary circuit structure of the dynamic amplifier shown in FIG. 1 .

FIG. 3 illustrates detailed operations of the dynamic amplifier shown in FIG. 1 .

FIG. 4 is a schematic diagram of a dynamic amplifier according to an embodiment of the present invention.

FIG. 5 illustrates an exemplary circuit structure of the dynamic amplifier shown in FIG. 4 .

FIG. 6 illustrates detailed operations of the dynamic amplifier shown in FIG. 4 .

FIG. 7 is a schematic diagram of the level shifter according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of a dynamic amplifier according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of another dynamic amplifier according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of another dynamic amplifier according to an embodiment of the present invention.

FIG. 11 illustrates detailed operations of the dynamic amplifier shown in FIG. 10 .

FIG. 12 is a schematic diagram of a further dynamic amplifier according to an embodiment of the present invention.

FIG. 13 illustrates detailed operations of the dynamic amplifier shown in FIG. 12 .

FIG. 14 is a schematic diagram of a gain boosting process according to an embodiment of the present invention.

FIG. 15 is a schematic diagram of a gain boosting process according to an embodiment of the present invention.

Please refer to FIG. 1 , which is a schematic diagram of a general dynamic amplifier 10 . As shown in FIG. 1 , the dynamic amplifier 10 includes an output capacitor 102 , a voltage-controlled current source (VCCS) 104 , a voltage detector 106 and switches SW 1 -SW 3 . The dynamic amplifier 10 receives a power supply voltage V DD from a power source 108 which may or may not be included in the dynamic amplifier 10 . The VCCS 104 is configured for charging or discharging the output capacitor 102 with a charge or discharge current based on a received input signal ΔV IN , to generate an output signal V OUT by amplifying the input signal ΔV IN . The voltage detector 106 , coupled to a voltage detection node ND and the switches SW 1 and SW 2 , is configured for detecting the output voltage of the output capacitor 102 via the voltage detection node ND, and thereby controlling the switches SW 1 and/or SW 2 to be turned on or off. The switch SW 1 , coupled between a terminal of the output capacitor 102 and the voltage detection node ND, acts as a cutoff switch that may cut off the signal path between the voltage detection node ND and the output capacitor 102 as controlled by the voltage detector 106 . The switch SW 2 , coupled between the VCCS 104 and the voltage detection node ND, acts as an amplification control switch for controlling the VCCS 104 to start to output the charge or discharge current or to stop outputting the charge or discharge current. The switch SW 3 , coupled between the voltage detection node ND and the power source 108 , acts as a reset switch for resetting the output voltage of the output capacitor 102 to the power supply voltage V DD when turned on.

FIG. 2 illustrates an exemplary circuit structure of the dynamic amplifier 10 shown in FIG. 1 . The output capacitor 102 is composed of two output capacitors C L1 and C L2 respectively disposed at the differential output terminals of the dynamic amplifier 10 , and the output capacitors C L1 and C L2 are coupled to switches SW 1 _ 1 and SW 1 _ 2 , respectively. The switches SW 1 _ 1 and SW 1 _ 2 , as the components of the cutoff switch SW 1 , are controlled by the voltage detector 106 . The VCCS 104 includes input transistors M 1 and M 2 , which receive the differential input voltages V inp and V inn to generate currents I d1 and I d2 . The amplification control switch SW 2 is controlled by a clock signal Clkn. The reset switch SW 3 is controlled by a reset signal Rst. The voltage detector 106 may detect the output voltage V outn of the output capacitor C L1 by receiving the voltage V 1 at a voltage detection node ND 1 , and detect the output voltage V outp of the output capacitor C L2 by receiving the voltage V 2 at a voltage detection node ND 2 .

FIG. 3 illustrates detailed operations of the dynamic amplifier 10 . The operations may include a pre-charge phase and an amplification phase. In the pre-charge phase, the reset switch SW 3 and the cutoff switch SW 1 are turned on and the amplification control switch SW 2 is turned off. More specifically, the reset signal Rst is in “Low” level to turn on the reset switch SW 3 which may be implemented with PMOS transistors, and the clock signal Clkn is in “Low” level to turn off the amplification control switch SW 2 which may be implemented with an NMOS transistor. The switches SW 1 _ 1 and SW 1 _ 2 are turned on by a control signal Vx from the voltage detector 106 . In such a situation, the output capacitors C L1 and C L2 are charged by currents from the power source, and the output voltages V outn and V outp together with the voltages V 1 and V 2 at the voltage detection nodes ND 1 and ND 2 are reset to the power supply voltage V DD , as shown in FIG. 3 .

At the end of the pre-charge phase, the clock signal Clkn rises to “High” level, allowing the dynamic amplifier 10 to enter the amplification phase and start to perform signal amplification. In the amplification phase, the cutoff switch SW 1 and the amplification control switch SW 2 are turned on and the reset switch SW 3 is turned off. More specifically, the clock signal Clkn is in “High” level to turn on the amplification control switch SW 2 , and the reset signal Rst is in “High” level to turn off the reset switch SW 3 . The switches SW 1 _ 1 and SW 1 _ 2 are still turned on by the control signal Vx from the voltage detector 106 . In such a situation, the output capacitors C L1 and C L2 are discharged by currents I d1 and I d2 generated by the VCCS 104 , and the output voltages V outn and V outp together with the voltages V 1 and V 2 at the voltage detection nodes ND 1 and ND 2 fall. The falling speed is determined by the magnitudes of the discharge currents I d1 and I d2 . During the discharging process, the voltage detector 106 may detect the common-mode voltage V com of the output voltages V outn and V outp reaches a threshold V TH . When detecting that the common-mode voltage V com reaches the threshold V H , the voltage detector 106 turns off the switches SW 1 _ 1 and SW 1 _ 2 via the control signal Vx, and the amplification control switch SW 2 may also be turned off, to stop the discharging operation.

Therefore, the input signal ΔV IN , which equals the difference between the input voltages V inp and V inn , is converted into discharge currents I d1 and I d2 and thereby amplified to generate the output signal V OUT , which equals the difference between the voltages V 1 and V 2 and also equals the difference between the output voltages V outn and V outp after the discharging process. In this case, the gain A of the dynamic amplifier 10 is obtained as follows:

A = V outp - V outn Δ ⁢ ⁢ V IN = g m I d × Δ ⁢ ⁢ V CM = g m I d × ( V DD - V com ) ;

wherein g m equals the transconductance of the input transistors M 1 and M 2 , I d equals a half of the total current supplied to the VCCS 104 , and ΔV CM is the variation of common-mode voltage V com which falls from the power supply voltage V DD due to the discharging operation during signal amplification.

In order to enhance the gain A, a level shifter is applied to shift the output voltages V outn and V out , to a higher voltage, to increase the variation of common-mode voltage ΔV CM . Please refer to FIG. 4 , which is a schematic diagram of a dynamic amplifier 40 according to an embodiment of the present invention. The structure of the dynamic amplifier 40 is similar to the structure of the dynamic amplifier 10 shown in FIG. 1 , so elements or modules having the same functions are denoted by the same symbols. The difference between the dynamic amplifier 40 and the dynamic amplifier 10 is that, the dynamic amplifier 40 further includes a level shifter LS coupled to another terminal of the output capacitor 102 . The level shifter LS may receive a shift control signal CS, which controls the output capacitor 102 to be coupled to different reference voltage nodes.

In an embodiment as shown in FIG. 4 , the level shifter LS includes a switch, which is controlled by the shift control signal CS to select to couple the output capacitor 102 to a reference voltage node N REF1 or a reference voltage node N REF2 . The reference voltage nodes N REF1 and N REF2 provide different reference voltages; hence, when the switch changes its status to couple the output capacitor 102 to one reference voltage node from the other reference voltage node, the output voltage of the output capacitor 102 may be shifted to another level.

FIG. 5 illustrates an exemplary circuit structure of the dynamic amplifier 40 shown in FIG. 4 . In the dynamic amplifier 10 shown FIG. 2 , the upper terminal (e.g., the top plate) of the output capacitors C L1 and C L2 is coupled to the VCCS 104 via the switches SW 1 _ 1 and SW 1 _ 2 , respectively, and the lower terminal (e.g., the bottom plate) of the output capacitors C L1 and C L2 is coupled to the ground terminal. In comparison, in the dynamic amplifier 40 shown in FIG. 5 , the upper terminal of the output capacitors C L1 and C L2 is also coupled to the VCCS 104 , while the lower terminal of the output capacitors C L1 and C L2 is coupled to level shifters LS 1 and LS 2 , respectively.

FIG. 6 illustrates detailed operations of the dynamic amplifier 40 . The operations also include a pre-charge phase and an amplification phase, as similar to those in FIG. 3 . As shown in FIG. 6 , at the end of the pre-charge phase, the voltage VS at the lower terminal of the output capacitors C L1 and C L2 rises to V REF1 from V REF2 , which may be realized by the level shifters LS 1 and LS 2 controlling the lower terminal of the output capacitors C L1 and C L originally coupled to the reference voltage node N REF2 switched to be coupled to the reference voltage node N REF1 . Therefore, the voltages V outn and V outp at the upper terminal of the output capacitors C L1 and C L2 are shifted to a higher level. This results in that the value of the variation of output common-mode voltage ΔV CM increases to ΔV CM,LS equivalently, which thereby increases the gain of the dynamic amplifier 40 . Similarly, the gain boosting method may also be considered as being realized with an increase in the integrating time of discharging the output capacitors (from T int to T int +T L s as shown in FIG. 6 ).

In an embodiment, the voltage detector 106 includes two detection capacitors C D1 and C D2 and a buffer BUF, as shown in FIG. 5 . The detection capacitor C D1 is coupled to the voltage detection node ND 1 , for detecting the output voltage V outn of the output capacitor C L1 by receiving the voltage V 1 . The detection capacitor C D2 is coupled to the voltage detection node ND 2 , for detecting the output voltage V outp of the output capacitor C L2 by receiving the voltage V 2 . The detection capacitors C D1 and C D2 thereby obtain the common-mode voltage V com of the output voltages V outn and V outp at a common-mode detection node. The buffer BUF, which is coupled to the switches SW 1 _ 1 and SW 1 _ 2 , may convert the received common-mode voltage V com into the control signal Vx, to control the switches SW 1 _ 1 and SW 1 _ 2 to be turned on or off according to the common-mode voltage V com .

Please note that the level shifter of the present invention may be implemented in any manners or any types, such as capacitive type, resistive type or current type. In an embodiment, the level shifter may be implemented with an inverter structure, as the level shifter 70 shown in FIG. 7 . The inverter structure, served as a switch controlling the coupling of the output capacitor, includes a PMOS transistor MP 1 and an NMOS transistor MN 1 . The PMOS transistor MP 1 is coupled between the output terminal of the level shifter 70 and the reference voltage node N REF1 . The NMOS transistor MN 1 is coupled between the output terminal of the level shifter 70 and the reference voltage node N REF2 . The PMOS transistor MP 1 and the NMOS transistor MN 1 are controlled by the same shift control signal, to select to couple the output terminal to the reference voltage node N REF1 or the reference voltage node N REF2 . In this embodiment, the reference voltage node N REF1 may output the reference voltage V REF1 equal to the power supply voltage or any other voltage greater than the reference voltage V REF2 , and the reference voltage node N REF2 may output the reference voltage V REF2 equal to the ground voltage or any other voltage smaller than the reference voltage V REF1 .

As shown in FIG. 7 , the shift control signal CS may be a logic signal generated from a digital control circuit, for example. If the shift control signal CS is “High”, the NMOS transistor MN 1 is turned on and the PMOS transistor MP 1 is turned off, so that the level shifter 70 may output the reference voltage V REF2 as the voltage V LS to the output capacitor. If the shift control signal CS is “Low”, the PMOS transistor MP 1 is turned on and the NMOS transistor MN 1 is turned off, so that the level shifter 70 may output the reference voltage V REF1 as the voltage V LS to the output capacitor. In such a situation, the level shifting method applied to the output capacitors of the dynamic amplifier may be realized by changing the status of the shift control signal CS.

In the dynamic amplifier 40 shown in FIG. 5 , the level shifting method is realized by introducing a level shifter coupled to the lower terminal of the output capacitors which is originally coupled to the ground terminal in the dynamic amplifier 10 shown in FIG. 2 . In this manner, the level shifting method may be realized without additional capacitors. In other embodiments, the level shifting method may be realized in other manners.

Please refer to FIG. 8 , which is a schematic diagram of a dynamic amplifier 80 according to an embodiment of the present invention. As shown in FIG. 8 , the structure of the dynamic amplifier 80 is similar to the structure of the dynamic amplifier 10 shown in FIG. 2 , so elements or modules having the same functions are denoted by the same symbols. The difference between the dynamic amplifier 80 and the dynamic amplifier 10 is that, the dynamic amplifier 80 further includes output capacitors C L3 and C L4 coupled to the differential output terminals of the dynamic amplifier 80 , respectively. Another terminal of the output capacitors C L3 and C L4 is coupled to the level shifters LS 1 and LS 2 , respectively. In such a situation, each output terminal of the dynamic amplifier 80 is coupled to two output transistors, one of which is further coupled to a level shifter, and the other is further coupled to the ground terminal. When the level shifter is switched to change its output voltage level, the output voltages of the dynamic amplifier 80 may also be shifted.

In the dynamic amplifier 80 , the level shifting method may be considered as being realized by introducing additional output capacitors and corresponding level shifters in the general dynamic amplifier 10 shown in FIG. 2 . Alternatively, the implementation of the dynamic amplifier 80 may be realized by dividing each output capacitor in the dynamic amplifier 10 into two parts, of which one part is further coupled to a level shifter and the other part is further coupled to the ground terminal.

Please refer to FIG. 9 , which is a schematic diagram of another dynamic amplifier 90 according to an embodiment of the present invention. As shown in FIG. 9 , the structure of the dynamic amplifier 90 is similar to the structure of the dynamic amplifier 40 shown in FIG. 5 , so elements or modules having the same functions are denoted by the same symbols. The difference between the dynamic amplifier 90 and the dynamic amplifier 40 is that, in the dynamic amplifier 90 the level shifter is coupled to the voltage detector 106 rather than coupled to the output capacitors C L1 and C L2 . As shown in FIG. 9 , the dynamic amplifier 90 includes a coupling capacitor C LS and a level shifter LS. The level shifter LS may shift the common-mode voltage V com of the output voltages V outn and V outp at the common-mode detection node of the voltage detector 106 ; hence, the common-mode voltage V com may fall to the threshold V TH at a later time point, which increases the integrating time of amplification. As a result, the gain of the dynamic amplifier 90 may increase.

Please refer back to FIG. 5 , where two level shifters are respectively coupled to the output capacitors C L1 and C L2 of the dynamic amplifier 40 . If a mismatch exists between the output capacitors C L1 and C L2 , the shifting quantities on the output voltages V outn and V outp may also have a mismatch. In comparison, as shown in FIG. 9 , there is only one level shifter LS shifting the common-mode voltage V com of the output voltages V outn and V outp , so the shifting quantities exerted on both output terminals will be identical, which solves the mismatch problem.

Please note that the present invention aims at providing a gain boosting method for a dynamic amplifier by shifting the level of an output voltage or an output common-mode voltage of the dynamic amplifier, to increase the variation of output common-mode voltage and also increase the integrating time of amplification. Those skilled in the art may make modifications and alternations accordingly. For example, in the above embodiments, the level shifter may change its status to shift the output voltages V outn and V outp to a higher level at the end of the pre-charge phase, as shown in FIG. 6 . In another embodiment, the level shifting operation may be implemented at another time point. For example, in the dynamic amplifier 40 , the level shifter LS may control the output capacitor originally coupled to the reference voltage node N REF2 switched to be coupled to the reference voltage node N REF1 to shift the level of the output voltage during the amplification phase.

Please further note that the gain boosting method of the present invention may be applied to any types of dynamic amplifiers. As long as the output signal of the dynamic amplifier is generated by charging or discharging the output capacitors via a current from a VCCS, the level shifter and gain boosting method of the present invention are applicable.

Please refer to FIG. 10 , which is a schematic diagram of another dynamic amplifier 100 according to an embodiment of the present invention. As shown in FIG. 10 , the structure of the dynamic amplifier 100 is similar to the structure of the dynamic amplifier 40 shown in FIG. 5 , so elements or modules having similar functions are denoted by similar symbols. The dynamic amplifier 100 and the dynamic amplifier 40 differ in that the dynamic amplifier 100 includes two additional transistors M 3 and M 4 served as a source follower. In addition to the output capacitors C L1 and C L2 , the dynamic amplifier 100 further includes two capacitors C m1 and C m2 coupled to the source terminal of the transistors M 3 and M 4 , respectively. The capacitors C m1 and C m2 are controlled by reset switches SW 3 _ 1 and SW 3 _ 4 . By discharging the capacitors C m1 and C m2 and the output capacitors C L1 and C L2 in order, higher gain may be achieved.

FIG. 11 illustrates detailed operations of the dynamic amplifier 100 . The operations also include a pre-charge phase and an amplification phase, as similar to those in FIG. 6 . In the pre-charge phase, the voltages of the lower terminal of the capacitors C m1 , C m2 , C L1 and C L2 are reset to the power supply voltage V DD . When the amplification phase starts, the discharge current of the VCCS 104 starts to discharge the capacitors C m1 and C m2 . When the voltages V mn and V mp fall to a specific threshold (i.e., the power supply voltage V DD minus the threshold voltage of the transistors M 3 and M 4 ), the transistors M 3 and M 4 are turned on and the discharge current of the VCCS 104 starts to discharge the output capacitors C L1 and C L2 . In this manner, the amplification phase includes two discharging periods, and thus the integrating time of amplification may increase. Also, the variation of output common-mode voltage ΔV CM is regarded as extending to ΔV CM0 equivalently. The increasing variation of output common-mode voltage leads to increasing gain of the dynamic amplifier 100 .

In addition, when the output capacitors C L1 and C L2 starts to be discharged, the level shifters LS 1 and LS 2 respectively shift the level of the output voltages V outn and V outp upwards, as shown in FIG. 11 . This further extends the variation of output common-mode voltage to ΔV CM0,LS , and the integrating time also increases to T in0 +T LS , so as to achieve the gain boosting effect. The detailed operations of the level shifters LS 1 and LS 2 shifting the level of the output voltages V outn and V outp are similar to the embodiments illustrated in FIGS. 4-6 , and will not be narrated herein.

Please refer to FIG. 12 , which is a schematic diagram of a further dynamic amplifier 120 according to an embodiment of the present invention. As shown in FIG. 12 , the structure of the dynamic amplifier 120 is similar to the structure of the dynamic amplifier 40 shown in FIG. 5 , so elements or modules having similar functions are denoted by similar symbols. The dynamic amplifier 120 and the dynamic amplifier 40 differ in that the dynamic amplifier 120 includes two VCCSs 104 _ 1 and 104 _ 2 . The VCCS 104 _ 1 is composed of two NMOS transistors M 1 and M 2 and the VCCS 104 _ 2 is composed of two PMOS transistors M 3 and M 4 . The voltage detector and pre-charge module 1206 provides functions of detecting the output voltages V outn and V outp in the amplification phase and resetting the output voltages V outn and V outp in the pre-charge phase.

FIG. 13 illustrates detailed operations of the dynamic amplifier 120 . The operations also include a pre-charge phase and an amplification phase, as similar to those in FIG. 6 . In the pre-charge phase, the voltages of the upper terminal of the capacitors C L1 and C L2 are reset to the power supply voltage V DD . When the amplification phase starts, the discharge current of the VCCS 104 _ 1 discharges the capacitors C L1 and C L2 and the output voltages V outn and V outp correspondingly fall. If the voltage detector and pre-charge module 1206 detects that the common-mode voltage V com of the output voltages V outn and V outp falls to a threshold, the NMOS transistors of the VCCS 104 _ 1 are turned off by the switch SW 2 _ 1 and the PMOS transistors of the VCCS 104 _ 2 are turned on by the switch SW 2 _ 2 . The VCCS 104 _ 2 then outputs a charge current to charge the output capacitors C L1 and C L2 and the output voltages V outn and V outp correspondingly rise. If the voltage detector and pre-charge module 1206 detects that the common-mode voltage V com of the output voltages V outn and V outp rises to another threshold, the voltage detector and pre-charge module 1206 may turn off the cutoff switches SW 1 _ 1 and SW 1 _ 2 . In this embodiment, the voltage detector includes multiple thresholds for controlling the operations of the VCCSs 104 _ 1 and 104 _ 2 and the cutoff switches SW 1 _ 1 and SW 1 _ 2 . The dynamic amplifier 120 is a bidirectional amplifier, where the amplification may be realized with both discharge currents from the NMOS VCCS 104 _ 1 and charge currents from the PMOS VCCS 104 _ 2 . As can be seen, the amplification phase includes a discharging period and a charging period, and thus the integrating time of amplification may increase. Also, the variation of output common-mode voltage ΔV CM is regarded as extending to ΔV CM1 equivalently. The increasing variation of output common-mode voltage leads to increasing gain of the dynamic amplifier 120 .

In addition, at the end of the discharging operation and the start of the charging operation, the level shifters LS 1 and LS 2 respectively shift the level of the output voltages V outn and V outp downwards, as shown in FIG. 13 . This further extends the variation of output common-mode voltage to ΔV CM1,LS , and the integrating time also increases to T int1 +T LS , so as to achieve the gain boosting effect. Note that the level shifting operation is performed before the VCCS 104 _ 2 charges the output capacitors C L1 and C L2 ; hence, the downward shift on the output voltages V outn and V outp may lead to a larger common-mode voltage variation and larger integrating time. In the above embodiments as shown in FIG. 6 , the level shifting operation is an upward shift performed before the VCCS discharges the output capacitors C L1 and C L2 , so as to increase the common-mode voltage variation and the integrating time.

In another embodiment, the level shifting operation may be performed by multiple times, to further boost the gain of the dynamic amplifier. For example, in the dynamic amplifier 120 shown in FIG. 12 , the level shifters LS 1 and LS 2 may shift the output voltages V outn and V out , upwards before the VCCS 104 _ 1 outputs the discharge currents to discharge the output capacitors C L1 and C L2 (i.e., at the end of the pre-charge phase), and then shift the output voltages V outn and V outp downwards before the VCCS 104 _ 2 outputs the charge currents to charge the output capacitors C L1 and C L2 . TO achieve this purpose, the level shifters LS 1 and LS 2 may control the lower terminal of the output capacitors C L1 and C L2 which originally coupled to a first reference voltage node to receive a lower reference voltage switched to be coupled to a second reference voltage node to receive a higher reference voltage, and then switched back to be coupled to the first reference voltage node to receive the lower reference voltage. Furthermore, during the amplification phase, the discharging operation and charging operation may be performed alternately by multiple times; hence, the level shifting operations (with upward shift and downward shift in turn) may be correspondingly performed, to unlimitedly increase the gain of the dynamic amplifier 120 .

In comparison with the dynamic amplifier 100 shown in FIG. 10 , the dynamic amplifier 120 further achieves the benefit of fewer capacitor numbers, which leads to lower circuit costs. There are fewer number of capacitors needing to be pre-charged in each pre-charge phase, and thus less power is consumed accordingly. Moreover, in the dynamic amplifier 120 , the VCCS 104 _ 2 charges the output capacitors C L1 and C L2 during the amplification phase and the charging operation pushes the output voltages V outn and V outp to a level closer to the power supply voltage V DD ; hence, in the next pre-charge phase, the power required for pre-charging the output capacitors C L1 and C L2 may be saved.

Please note that the deployments of level shifters shown in FIGS. 8 and 9 are also applicable to the dynamic amplifiers 100 and 120 . That is, parts of the output capacitors are coupled to the level shifters and other output capacitors are coupled to the ground terminal; and/or a level shifter is coupled to the common-mode detection node of the voltage detector.

The abovementioned gain boosting operations of the present invention may be summarized into a gain boosting process 140 , as shown in FIG. 14 . The gain boosting process 140 may be applied to any of the dynamic amplifiers 40 , 80 , 90 , 100 and 120 , and includes the following steps:

Step 1402 : Reset an output voltage of a first terminal of the output capacitor to a power supply voltage.

Step 1404 : Shift the output voltage upwards by switching a second terminal of the output capacitor coupled to a first reference voltage node to receive a lower reference voltage to be coupled to a second reference voltage node to receive a higher reference voltage.

Step 1406 : Discharge the output capacitor with a discharge current to perform amplification, to decrease the output voltage.

The detailed operations and alternations of the gain boosting process 140 are described in the above paragraphs, and will not be narrated herein. Note that the gain boosting process 140 realizes gain boosting by shifting the output voltage upwards; while in another embodiment, gain boosting may further be realized by shifting the output voltage downwards, and this is applicable to the dynamic amplifier 120 . As shown in FIG. 15 , a gain boosting process 150 , which realizes gain boosting by shifting the output voltage upwards and downwards, includes the following steps:

Step 1502 : Reset an output voltage of a first terminal of the output capacitor to a power supply voltage.

Step 1504 : Shift the output voltage upwards by switching a second terminal of the output capacitor coupled to a first reference voltage node to receive a lower reference voltage to be coupled to a second reference voltage node to receive a higher reference voltage.

Step 1506 : Discharge the output capacitor with a discharge current to perform amplification, to decrease the output voltage.

Step 1508 : Shift the output voltage downwards by switching the second terminal of the output capacitor coupled to the second reference voltage node to receive the higher reference voltage to be coupled to the first reference voltage node to receive the lower reference voltage.

Step 1510 : Charge the output capacitor with a charge current to perform amplification, to increase the output voltage.

Please note that the steps 1504 - 1510 may be performed repeatedly to unlimitedly boost the gain. Other detailed operations and alternations of the gain boosting process 150 are described in the above paragraphs, and will not be narrated herein.

To sum up, the embodiments of the present invention provide a gain boosting method for a dynamic amplifier by shifting the level of an output voltage or an output common-mode voltage of the dynamic amplifier, to increase the variation of output common-mode voltage and also increase the integrating time of amplification. A level shifter having a switch is coupled to the output capacitor or voltage detector to realize the gain boosting method. The gain boosting method of shifting the voltage level may be performed at the end of the pre-charge phase or during the amplification phase, and may be performed by one or more times according to system requirements. The gain boosting method of the present invention may be applied to any types of dynamic amplifiers having any structures, which should not be limited to the embodiments illustrated in this disclosure.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.