Power converter

This application is based on and claims the benefit of priority from earlier Japanese Patent Application No. 2017-105984 filed on May 29, 2017, the description of which is incorporated herein by reference.

The present disclosure relates to a power converter.

Conventionally, a power converter is known which comprises a plurality of switches and freewheeling diodes each electrically connected in anti-parallel with an respective one of the switches (see, for example, Japanese Patent Application Laid-Open Publication No. 2013-17092).

A recovery current flows through each of the freewheeling diodes. Upon completion of passage of the recovery current, a surge voltage may be generated on an electrical path through which the recovery current flows. A potential on an output terminal of one of the plurality of switches connected in parallel with each other, which corresponds to the freewheeling diode where the surge voltage has been generated, may become relatively lower than a potential on an output terminal of another one of the switches. Thus, a potential difference may be generated between the output terminals of different switches. This is because the output terminals of the switches are electrically connected to each other.

The timing of completion of passage of the recovery current may not be matched between at least two of the freewheeling diodes due to a characteristic difference between individual freewheeling diodes. Upon sequential completion of passage of recovery current through the respective freewheeling diodes, the potential difference between the output terminals of the respective switches may significantly vary. Large variations in the potential difference may cause a voltage applied to a terminal of a respective switch, such as a control terminal or an output terminal, to exceed a rated value. This may lead to degradation or malfunctioning of the switches.

In view of the above, a power converter capable of suppressing variations in potential difference between output terminals of a plurality of switches electrically connected in parallel with each other is desired.

One aspect of the disclosure provides a power converter including: a plurality of switches; a plurality of freewheeling diodes, each of which is electrically connected in anti-parallel with a respective one of the switches; a freewheeling current input electrically connected to an output terminal of each of the switches; a freewheeling current output electrically connected to an input terminal of each of the switches. In the power converter, a plurality of freewheeling current paths are defined, each of which is an electrical path passing through a respective one of the freewheeling diodes from the freewheeling current input to the freewheeling current output, at least one of the plurality of freewheeling current paths is a maximum path having a maximum impedance among the freewheeling current paths, and a voltage drop across the freewheeling diode included in the maximum path is less than a voltage drop across each of the other freewheeling diodes when a freewheeling current flows through each of the plurality of freewheeling diodes.

In this aspect, the output terminals of the respective switches are electrically connected to the freewheeling current input, and the input terminals of the respective switches are electrically connected to the freewheeling current output. Therefore, the plurality of switches are electrically connected in parallel with each other.

A value of freewheeling current through each of the plurality of freewheeling diodes may vary due to differences in characteristic between the individual freewheeling diodes, which may give rise to differences in freewheeling current value between the plurality of freewheeling diodes. As the differences in freewheeling current value increase, the timing of completion of passage of recovery current may significantly vary with the freewheeling diodes, which may result in large variations in potential difference between the output terminals of the respective switches.

To suppress variations in potential difference between the output terminals of the respective switches, in this aspect, the power converter is configured as follows. The plurality of freewheeling current paths include at least one freewheeling current path that is a maximum path having a maximum impedance among the freewheeling current paths.

Given such a maximum path having a maximum impedance among the freewheeling current paths, a voltage drop across the freewheeling diode included in the maximum path is less than a voltage drop across each of the other freewheeling diodes when a freewheeling current flows through each of the plurality of freewheeling diodes. This configuration can suppress variations in impedance with the freewheeling current paths, thus suppressing variations in voltage drop generated when a freewheeling current flows through each of the freewheeling current paths with the freewheeling current paths. This can suppress variations in difference between the values of freewheeling currents through the respective freewheeling diodes and can therefore suppress variations in timing of completion of passage of the recovery current with the freewheeling current paths. As a result, variations in potential difference between the output terminals of the respective switches can be suppressed.

FIG. 1 is an overall configuration diagram of a motor control system in accordance with a first embodiment;

FIG. 2 is a perspective view of a semiconductor module;

FIG. 3 is a perspective view of a cooling arrangement for cooling semiconductor modules;

FIG. 4 is a plan view of semiconductor modules and connections;

FIG. 5 is a drive circuit diagram;

FIG. 6 is an example of variations in diode current-voltage characteristics;

FIG. 7 is a circuit diagram for any one of three phases;

FIG. 8 is a timing diagram illustrating mismatched timing of completion of recovery current passages;

FIG. 9 is a circuit diagram illustrating a mechanism generating variations in emitter potential difference;

FIG. 10 is a circuit diagram illustrating a mechanism generating variations in emitter potential difference;

FIG. 11 is a circuit diagram illustrating a mechanism generating variations in emitter potential difference;

FIG. 12 is a circuit diagram illustrating a mechanism generating variations in emitter potential difference;

FIG. 13 is a schematic diagram of a drive circuit in accordance with a first comparative technique;

FIG. 14 is an example of defining diode characteristics in accordance with a second comparative technique;

FIG. 15 is an example of defining impedances in accordance with the first embodiment;

FIG. 16 is an example of defining diode characteristics;

FIG. 17 is an example of defining diode characteristics;

FIG. 18 is an example of defining diode characteristics in accordance with a second embodiment;

FIG. 19 is a circuit diagram of an inverter for one of the three phases in accordance with a third embodiment;

FIG. 20 is an example of defining diode characteristics;

FIG. 21 is an example of defining diode characteristics in accordance with a fourth embodiment;

FIG. 22 is an example of defining diode characteristics in accordance with a fifth embodiment;

FIG. 23 is a perspective view of a semiconductor module in accordance with a sixth embodiment; and

FIG. 24 is a perspective view of connections for semiconductor modules.

With reference to the accompanying drawings, hereinafter are described several embodiments of the present disclosure. Substantially common elements throughout the embodiments are assigned the same numbers and will not be redundantly described.

First Embodiment

A vehicle-mounted motor control system including a power converter in accordance with a first embodiment of the present disclosure will now be described.

As shown in FIG. 1 , the control system includes a battery 10 , an inverter 20 as the power converter, a rotary electric machine 21 , and a controller 22 . The battery 10 has a voltage of 100 V or higher across the terminals. More specifically, the battery 10 may be a lithium-ion battery or a nickel-hydrogen battery. A capacitor 11 , as a DC power source, is connected in parallel with the battery 10 .

The rotary electric machine 21 serves as a vehicle prime mover and can transmit dynamical power to a drive wheel (not shown). In the present embodiment, the rotary electric machine 21 may be a three-phase permanent magnet synchronous machine.

The inverter 20 is configured to convert direct-current (DC) power from the capacitor 11 into alternating-current (AC) power to output the AC power to the rotary electric machine 21 . In the present embodiment, the inverter 20 is a three-phase inverter. The inverter 20 includes, for each of the three phases, a series connection of a first upper arm switch SH 1 and a first lower arm switch SL 1 and a series connection of a second upper arm switch SH 2 and a second lower arm switch SL 2 . The series connection of the first upper arm switch SH 1 and the first lower arm switch SL 1 and the series connection of the second upper arm switch SH 2 and the second lower arm switch SL 2 are electrically connected in parallel with each other. In the present embodiment, each of the switches SH 1 , SH 2 , SL 1 , SL 2 is a voltage control type semiconductor switch element, more specifically, an insulated gate bipolar transistor (IGBT). In each switch, a control terminal is a gate, an input terminal is a collector, and an output terminal is an emitter.

A first upper arm diode DH 1 is electrically connected in anti-parallel with the first upper arm switch SH 1 . A first lower arm diode DL 1 is electrically connected in anti-parallel with the first lower arm switch SL 1 . A second upper arm diode DH 2 is electrically connected in anti-parallel with the second upper arm switch SH 2 . A second lower arm diode DL 2 is electrically connected in anti-parallel with the second lower arm switch SL 2 .

In the present embodiment, each of the diodes DH 1 , DH 2 , DL 1 , DL 2 corresponds to a freewheeling diode. Each of the diodes DH 1 , DH 2 , DL 1 , DL 2 may be integrated within a corresponding one of the switches SH 1 , SH 2 , SL 1 , SL 2 to provide an IGBT with a built-in diode or may be external to a corresponding one of the switches SH 1 , SH 2 , SL 1 , SL 2 .

In the present embodiment, as shown in FIG. 2 , the first upper arm switch SH 1 , the first upper arm diode DH 1 , the first lower arm switch SL 1 , and the first lower arm diode DL 1 are integrated within a body BD to provide a semiconductor module MS. The second upper arm switch SH 2 , the second upper arm diode DH 2 , the second lower arm switch SL 2 , and the second lower arm diode DL 2 are integrated within a body BD to provide a semiconductor module MS. In the present embodiment, each body BD is flattened cuboid shaped.

Each semiconductor module MS has a switch high-voltage terminal TP, a switch low-voltage terminal TN, and an intermediate terminal TO. The switch high-voltage terminal TP, the switch low-voltage terminal TN, and the intermediate terminal TO protrude from the body BD. The switch high-voltage terminal TP is electrically connected to the collector of the upper arm switch. The switch low-voltage terminal TN is electrically connected to the emitter of the lower arm switch. The intermediate terminal TO is electrically connected to the emitter of the upper arm switch and the collector of the lower arm switch.

In each semiconductor module MS, as shown in FIGS. 1-4 , the switch high-voltage terminal TP is electrically connected to a high-voltage conductive member Bp via a conductive high-voltage connection 30 p . The high-voltage conductive member Bp is electrically connected to a high-voltage power source terminal TCP that is a high side terminal of the capacitor 11 . In each semiconductor module MS, the switch low-voltage terminal TN is electrically connected to a low-voltage conductive member Bn via a conductive low-voltage connection 30 n . The low-voltage conductive member Bn is electrically connected to a low-voltage power source terminal TCN that is a low side terminal of the capacitor 11 . A positive terminal of the battery 10 is electrically connected to the high-voltage power source terminal TCP. A negative terminal of the battery 10 is electrically connected to the low-voltage power source terminal TCN.

For each of the three phases, intermediate terminals TO of the two semiconductor modules MS are electrically connected to a first conductive connection Bm 1 . The first connection Bm 1 is electrically connected to a first end of a winding 21 A of the rotary electric machine 21 via a second conductive connection Bm 2 . A second end of the winding 21 A of the rotary electric machine 21 is electrically connected to a neutral point. The winding 21 A is an inductive load. The first connection Bm 1 and the second connection Bm 2 may be integrated with each other or be separate members.

In the present embodiment, the control system includes a cooling arrangement 40 . The cooling arrangement 40 , as shown in FIG. 3 , includes a pair of cooling conduits 41 and a plurality of cooling plates 42 . Each semiconductor module MS is sandwiched between a pair of cooling plates 42 . The cooling conduits 41 and the cooling plates 42 form a cooling passage thorough which a cooling fluid flows.

As shown in FIG. 5 , the inverter 20 includes, for each of the three phases, an upper arm drive circuit DrH configured to drive the first upper arm switch SH 1 and the second upper arm switch SH 2 and a lower arm drive circuit DrL configured to drive the first lower arm switch SL 1 and the second lower arm switch SL 2 .

The controller 22 is configured to on-off drive the respective switches SH 1 , SH 2 , SL 1 , SL 2 of the inverter 20 to control a controlled variable, such as a torque, of the rotary electric machine 21 , to a command value for the controlled variable. The controller 22 outputs, for each of the three phases, an upper arm drive signal GH for the first and second upper arm switches SH 1 , SH 2 to the upper arm drive circuit DrH. The controller 22 outputs, for each of the three phases, a lower arm drive signal GL for the first and second lower arm switches SL 1 , SL 2 to the lower drive circuit DrL. The controller 22 generates the drive signals GH, GL for the respective drive circuits DrH, DrL by pulse width modulation (PWM) processing based on comparing whether each of three-phase command voltages that are 120 degrees in electrical angle out of phase is above or below a carrier signal such as a triangular wave. Each of the drive signals GH, GL takes either an on drive command for instruction to switch to an on state or an off drive command for instruction to switch to an off state. For each of the three phases, the upper arm drive signal GH and the lower arm drive signal GL are complementary to each other. Thus, for each of the three phases, the first and second upper arm switches SH 1 , SH 2 and the first and second lower arm switches SL 1 , SL 2 are alternately put in the on state with a dead time between their on states.

The drive circuits DrH, DrL will now be described with reference to FIG. 5 . In FIG. 5 , for simplification, the intermediate terminal TO of the semiconductor module MS including the first upper and lower arm switches SH 1 , SL 1 and the intermediate terminal TO of the semiconductor module MS including the second upper and lower arm switches SH 2 , SL 2 are represented by a single intermediate terminal TO.

The upper arm drive circuit DrH includes an upper power source 50 , an upper charging switch 51 , and an upper charging resistor 52 . The upper power source 50 is electrically connected to a first end of the upper charging resistor 52 through the upper charging switch 51 . A second end of the upper charging resistor 52 is electrically connected to the gate of the first upper arm switch SH 1 and the gate of the second upper arm switch SH 2 .

The upper arm drive circuit DrH includes an upper discharging resistor 53 and an upper discharging switch 54 . A first end of the upper discharging resistor 53 is electrically connected to the gate of the first upper arm switch SH 1 and the gate of the second upper arm switch SH 2 . A second end of the upper discharging resistor 53 is electrically connected to a ground GNDH of the upper arm drive circuit DrH through the upper discharging switch 54 . The emitter of the first upper arm switch SH 1 and the emitter of the second upper arm switch SH 2 are electrically connected to the ground GNDH.

The upper arm drive circuit DrH includes an upper controller 55 . The upper controller 55 is configured to on-off drive the respective upper arm switches SH 1 , SH 2 by alternately performing charging and discharging processes in response to the upper arm drive signal GH from the controller 22 . More specifically, in the charging process, when the upper controller 55 determines that the upper arm drive signal GH is the on drive command, the upper controller 55 puts the upper charging switch 51 in the on state and puts the upper discharging switch 54 in the off state. This allows a charging current to flow from the upper power source 50 to the gate of each of the upper arm switches SH 1 , SH 2 , such that a gate voltage of each of the upper arm switches SH 1 , SH 2 becomes equal to or greater than a threshold voltage. Thus, each of the upper arm switches SH 1 , SH 2 transitions from the off state to the on state.

In the discharging process, when the upper controller 55 determines that the upper arm drive signal GH is the off drive command, the upper controller 55 puts the upper charging switch 51 in the off state and puts the upper discharging switch 54 in the on state. This allows a discharge current to flow from the gate to the emitter of each of the upper arm switches SH 1 , SH 2 , such that the gate voltage of each of the upper arm switches SH 1 , SH 2 drops below the threshold voltage. Thus, each of the upper arm switches SH 1 , SH 2 transitions from the on state to the off state.

The lower arm drive circuit DrL includes a lower power source 60 , a lower charging switch 61 , a lower charging resistor 62 , a lower discharging resistor 63 , and a lower discharging switch 64 . The lower arm drive circuit DrL is similar in configuration to the upper arm drive circuit DrH and will not thus be redundantly described. In FIG. 5 , a ground for the lower arm drive circuit DrL is denoted by GNDL.

The lower arm drive circuit DrL includes a lower controller 65 . The lower controller 65 is configured to on-off drive the respective lower arm switches SL 1 , SL 2 by alternately performing charging and discharging processes in response to the lower arm drive signal GL from the controller 22 . More specifically, in the charging process, when the lower controller 65 determines that the lower arm drive signal GL is the on drive command, the lower controller 65 puts the lower charging switch 61 in the on state and puts the lower discharging switch 64 in the off state. This allows a charging current to flow from the lower power source 60 to the gate of each of the lower arm switches SL 1 , SL 2 , such that a gate voltage of each of the lower arm switches SL 1 , SL 2 becomes equal to or greater than a threshold voltage. Thus, each of the lower arm switches SL 1 , SL 2 transitions from the off state to the on state.

In the discharging process, when the lower controller 65 determines that the lower arm drive signal GL is the off drive command, the lower controller 65 puts the lower charging switch 61 in the off state and puts the lower discharging switch 64 in the on state. This allows a discharge current to flow from the gate to the emitter of each of the lower arm switches SL 1 , SL 2 , such that the gate voltage of each of the lower arm switches SL 1 , SL 2 drops below the threshold voltage. Thus, each of the lower arm switches SL 1 , SL 2 transitions from the on state to the off state.

Referring to FIG. 6 , each of the diodes DH 1 , DH 2 , DL 1 , DL 2 has a current-voltage characteristic represented by a relationship between freewheeling current and voltage drop Vf. Such a characteristic may vary with individual mass-produced diodes. The mass-produced diodes may include a diode with a maximum characteristic Vfmax and a diode with a minimum characteristic Vfmin as shown in FIG. 6 . The maximum characteristic Vfmax is defined as a current-voltage characteristic of a diode that exhibits a maximum voltage drop at a specific value of freewheeling current. The minimum characteristic Vfmin is defined as a current-voltage characteristic of a diode that exhibits a minimum voltage drop at the specific value of freewheeling current.

Since the current-voltage characteristic varies with the mass-produced diodes, each of the first lower arm diode DL 1 and the second lower arm diode DL 2 may exhibit a different voltage drop at a certain value of freewheeling current. That is, at a certain value of freewheeling current, a voltage drop across one of the first lower arm diode DL 1 and the second lower arm diode DL 2 may be greater than a voltage drop across the other one of the first lower arm diode DL 1 and the second lower arm diode DL 2 . In such a case, an imbalance phenomenon may occur, such that there is a large difference in freewheeling current value between the first and the second lower arm diodes DL 1 , DL 2 . In the following, some issues caused by such an imbalance phenomenon will now be described.

FIG. 7 illustrates switches SH 1 , SL 1 , SH 2 , SL 2 for any one of the three-phases. For sake of simplicity, in FIG. 7 , the intermediate terminal TO of the semiconductor module MS including the first upper and lower arm switches SH 1 , SL 1 and the intermediate terminal TO of the semiconductor module MS including the second upper and lower arm switches SH 2 , SL 2 are represented by a single intermediate terminal TO.

FIG. 7 illustrates a situation where a freewheeling current flows from the low-voltage power source terminal TCN to the intermediate terminal TO through the first lower arm diodes DL 1 and a freewheeling current flows from the low-voltage power source terminal TCN to the intermediate terminal TO through the second lower arm diodes DL 2 . A value of freewheeling current flowing through the first lower arm diodes DL 1 is denoted by IL 1 , and a value of freewheeling current flowing through the second lower arm diodes DL 2 is denoted by IL 2 .

FIG. 7 also illustrates an impedance of each electrical path in the inverter 20 . A first high-voltage impedance RP 1 is an impedance of an electrical path from the high-voltage power source terminal TCP to the collector of the first upper arm switch SH 1 via the high-voltage conductive member Bp, the high-voltage connection 30 p , and the switch high-voltage terminal TP of the semiconductor module MS including the first upper arm diode DH 1 . The second high-voltage impedance RP 2 is an impedance of an electrical path from the high-voltage power source terminal TCP to the collector of the second upper arm switch SH 2 via the high-voltage conductive member Bp, the high-voltage connection 30 p , and the switch high-voltage terminal TP of the semiconductor module MS including the second upper arm diode DH 2 . In FIG. 7 , the magnitude of impedance is determined by magnitude settings of inductance of the electrical path. More specifically, the electrical path impedance increases with increasing electrical path inductance.

A first intermediate voltage impedance RO 1 is an impedance of an electrical path from intermediate terminal TO to the emitter of the first upper arm switch SH 1 or the collector of the first lower arm switch SL 1 in the semiconductor module MS including the first upper arm diode DH 1 . A second intermediate voltage impedance RO 2 is an impedance of an electrical path from the intermediate terminal TO to the emitter of the second upper arm switch SH 2 or the collector of the second lower arm switch SL 2 in the semiconductor module MS including the second upper arm diode DH 2 .

A first low voltage impedance RN 1 is an impedance of an electrical path from the low-voltage power source terminal TCN to the emitter of the first lower arm switch SL 1 via the low voltage conductive member Bn, the low voltage connection 30 n , and the switch low-voltage terminal TN of the semiconductor module MS including the first lower arm diode DL 1 . A second low voltage impedance RN 2 is an impedance of an electrical path from the low-voltage power source terminal TCN to the emitter of the second lower arm switch SL 2 via the low voltage conductive member Bn, the low voltage connection 30 n , and the switch low-voltage terminal TN of the semiconductor module MS including the second lower arm diode DL 2 .

The first lower arm diode DL 1 and the second lower arm diode DL 2 are electrically connected in parallel with each other. In a situation where there is a flow of freewheeling current thorough each of the first and second lower arm diodes DL 1 , DL 2 , a voltage drop Vfl 1 (IL 1 ) across the first lower arm diode DL 1 and a voltage drop Vfl 2 (IL 2 ) across the second lower arm diode DL 2 satisfies the following equation (1).

VfL 1( IL 1)+ IL 1×( RO 1+ RN 1)= VfL 2( IL 2)+ IL 2×( RO 2+ RN 2)  (eq 1)

As shown in FIG. 6 , a larger freewheeling current flows through the first lower arm diode DL 1 having a lower voltage drop than the second lower arm diode DL 2 . Thus, meeting the equation (1) may lead to a large difference between the freewheeling current IL 1 flowing through the first lower arm diode DL 1 and the freewheeling current IL 2 flowing through the second lower arm diode DL 2 , which may cause an imbalance phenomenon.

In a situation where the imbalance phenomenon is occurring, as shown in FIG. 8 , when the first and second upper arm switches SH 1 , SH 2 are put in the on state at time t 1 , the timing of beginning of decrease in absolute value of recovery current, as indicated by times t 1 , t 2 in FIG. 6 , is significantly mismatched. This may cause a large potential difference between the emitters of the first and second lower arm switches SL 1 , SL 2 .

A reason why a potential difference between the emitters of the first and second lower arm switches SL 1 , SL 2 may significantly vary will now be described with reference to FIGS. 9-12 .

FIG. 9 illustrates, for any one of the three phases, a situation where the first and second upper arm switches SH 1 , SH 2 are in the on state and the first and second lower arm switches SL 1 , SL 2 are in the off state. In the example of FIG. 9 , there is a flow of current from the high-voltage power source terminal TCP to the low-voltage power source terminal TCN through the first upper arm switch SH 1 , the intermediate terminal TO, the windings 21 A for two phases of the rotary electric machine 21 , and the first and second lower arm switches for the other phases (not shown). In the example of FIG. 9 , there is another flow of current from the high-voltage power source terminal TCP to the low-voltage power source terminal TCN through the second upper arm switch SH 2 , the intermediate terminal TO, the windings 21 A for two phases of the rotary electric machine 21 , and the first and second lower arm switches for the other phases (not shown).

FIG. 10 illustrates a situation where the first and second upper arm switches SH 1 , SH 2 are put in the off state and the first and second lower arm switches SL 1 , SL 2 are in the on state. In the example of FIG. 10 , the presence of windings 21 A as an inductive load causes a flow of current through a loop path including the first lower arm diode DL 1 , the intermediate terminal TO, the windings 21 A, and the first and second lower arm switches for the other phases (not shown). In the example of FIG. 10 , there is another flow of current through a loop path including the second lower arm diode DL 2 , the intermediate terminal TO, the windings 21 A, and the first and second lower arm switches for the other phases (not shown).

FIG. 11 illustrates a situation where the first and second upper arm switches SH 1 , SH 2 are put again in the on state and the first and second lower arm switches SL 1 , SL 2 are put again in the off state. In the example of FIG. 11 , a reverse voltage applied to the second lower arm diode DL 2 causes a flow of recovery current through the second lower arm diode DL 2 . Upon completion of passage of the recovery current, a surge voltage is thereby generated across the low voltage conductive member Bn. The surge voltage is proportional to a product value of a rate of decrease in recovery current dI/dt and an inductance of the low voltage conductive member Bn or the like. Due to the presence of the surge voltage, a potential VE 2 on the emitter of the second lower arm switch SL 2 becomes relatively lower than a potential VE 1 on the emitter of the first lower arm switch SL 1 .

Thereafter, as shown in FIG. 12 , a reverse voltage applied to the first lower arm diode DL 1 causes a flow of recovery current through the first lower arm diode DL 1 . Upon completion of passage of the recovery current, a surge voltage is thereby generated across the low voltage conductive member Bn. Due to the presence of the surge voltage, a potential VE 1 on the emitter of the first lower arm switch SL 1 becomes relatively lower than a potential VE 2 on the emitter of the second lower arm switch SL 2 . Thus, the completion timing of recovery current is significantly mismatched, which may result in a large variation in potential difference between the emitter of the first lower arm switch SL 1 and the second lower arm switch SL 2 .

Such a large variation in potential difference between the emitter of the first lower arm switch SL 1 and the second lower arm switch SL 2 may cause an applied voltage on the gate terminal or the emitter of at least one of the first and second lower arm switch SL 1 , SL 2 to exceed a rated value. This may result in malfunctioning of the first and second lower arm switches SL 1 , SL 2 or degradation of the first and second lower arm switches SL 1 , SL 2 .

A value of freewheeling current flowing through the first upper arm diode DH 1 is denoted by IH 1 , and a value of freewheeling current flowing through the second upper arm diode DH 2 is denoted by IH 2 . A voltage drop across the first upper arm diode DH 1 , denoted by VfH 1 (IH 1 ), and a voltage drop across the second upper arm diode DL 2 , denoted by VfH 2 (IH 2 ), meet the following equation (2).

VfH 1( IH 1)+ IH 1×( RO 1+ RP 1)= VfH 2( IH 2)+ IH 2×( RO 2+ RP 2)  (eq 2)

It is assumed that the voltage drop VfH 1 (IH 1 ) across the first upper arm diode DH 1 and the voltage drop VfH 2 (IH 2 ) across the second upper arm diode DL 2 are different. In such a case, a large difference between the freewheeling current IH 1 flowing through the first upper arm diode DH 1 and the freewheeling current IH 2 flowing through the second upper arm diode DH 2 may be generated to meet the equation (2), which may cause an imbalance phenomenon. In a situation where the imbalance phenomenon is occurring, also when the first and second lower arm switches SL 1 , SL 2 are put in the on state and the first and second upper arm switched SH 1 , SH 2 are put in the off state, a large variation in potential difference between the emitters of the first and second upper arm switches SH 1 , SH 2 may be generated.

First Comparative Technique

FIG. 13 illustrates a configuration where a pair of upper and lower arm switches are provided for each of the three phases. In such a configuration, even if a surge voltage is generated upon completion of passage of the recovery current, the potential difference between the emitter of the first lower arm switch SL 1 and the emitter of the second lower arm switch SL 2 does not significantly vary. This is because no difference between the potential VE 2 on the emitter of the second lower arm switch SL 2 and the potential VE 3 on the opposite end of the lower discharging switch 64 from the lower discharging resistor 63 is generated even if a surge voltage is generated upon completion of passage of the recovery current.

Continuing with the lower arm example, a difference between freewheeling current values IL 1 , IL 2 , which may cause the imbalance phenomenon, depends on a lower arm potential difference ΔVfL which is an abscissa shown in FIG. 14 . In the present embodiment, the lower arm potential difference ΔVfL is the voltage drop VfL 1 across the first lower arm diode DL 1 minus the voltage drop VfL 2 across the second lower arm diode DL 2 . ΔVfL=0 means that the current-voltage characteristic of the first lower arm diode DL 1 and the current-voltage characteristic of the second lower arm diode DL 2 are the same. ΔVfL=|ΔVfLmax| means that the current-voltage characteristic of the first lower arm diode DL 1 is the maximum characteristic Vfmax and the current-voltage characteristic of the second lower arm diode DL 2 is the minimum characteristic Vfmin. ΔVfLmax is hereinafter referred to as a lower arm maximum potential difference ΔVfLmax.

Second Comparative Technique

FIG. 14 illustrates a relationship between lower arm potential difference ΔVfL in a second comparative technique and the freewheeling current values IL 1 , IL 2 . The second comparative technique is configured such that RP 1 =RP 2 , RO 1 =RO 2 , and RN 1 =RN 2 in the equations (1), (2).

In the second comparative technique, when the first and second lower arm diodes DL 1 , DL 2 that meet ΔVfL=0 are used, the value of freewheeling current IL 1 through the first lower arm diode DL 1 becomes equal to the value of freewheeling current IL 2 through the second lower arm diode DL 2 . Thus, no imbalance phenomenon occurs.

In the second comparative technique, however, when one of the first and second lower arm diodes DL 1 , DL 2 has the minimum characteristic Vfmin and the other one has the maximum characteristic Vfmax, an absolute difference value between the freewheeling current IL 1 through the first lower arm diode DL 1 and the freewheeling current IL 2 through the second lower arm diode DL 2 becomes a lower arm maximum current difference ΔILmax. The lower arm maximum current difference ΔILmax is a maximum value of an absolute difference between the freewheeling current IL 1 through the first lower arm diode DL 1 and the freewheeling current IL 2 through the second lower arm diode DL 2 under assumption that RO 1 =RO 2 and RN 1 =RN 2 .

Thus, in the second comparative technique, the absolute difference value between the freewheeling currents IL 1 , IL 2 may increase.

To reduce the absolute difference value between the freewheeling currents IL 1 , IL 2 , the configuration of the present embodiment will now be described.

For each of the three phases, the lower arm side employs the following conditions (A1)-(C1).

(A1) As shown in FIG. 15 , the first intermediate voltage impedance RO 1 is set less than the second intermediate voltage impedance RO 2 , and the first low voltage impedance RN 1 is set less than the second low voltage impedance RN 2 .

(B1) As shown FIG. 15 , the voltage drop VfL 1 across the first lower arm diode DL 1 is set less than the voltage drop VfL 2 across the second lower arm diode DL 2 when a freewheeling current flows through each of the first and second lower arm diodes DL 1 , DL 2 . This can prevent the current-voltage characteristics of the first and second lower arm diodes DL 1 , DL 2 from becoming VfL 1 >VfL 2 or VfL 2 >VfL 1 , which can reduce factors causing a large variation in difference between the freewheeling current values IL 1 , IL 2 .

(C1) As shown in FIG. 16 , the current-voltage characteristics of the first and second lower arm diodes DL 1 , DL 2 and the respective impedances RO 1 , RO 2 , RN 1 , RN 2 are defined such that an absolute difference value between the voltage drop VfL 1 across the first lower arm diode DL 1 and the voltage drop VfL 2 across the second lower arm diode DL 2 when a freewheeling current flows through each of the first and second lower arm diodes DL 1 , DL 2 is set equal to or less than an absolute difference value between the voltage drop VfL 1 across the first lower arm diode DL 1 and the voltage drop VfL 2 across the second lower arm diode DL 2 under assumption that the freewheeling current flowing through the first lower arm diode DL 1 is as large as the freewheeling current flowing through the second lower arm diode DL 2 . In FIG. 16 , a set range for the current-voltage characteristics of the first and second lower arm diodes DL 1 , DL 2 to meet the condition (C1) is denoted by ADL. In FIG. 16 , a range of ΔVfL in which VfL 1 >VfL 2 consists of ranges ADL and ADX. When the freewheeling current through each of the first and second lower arm diodes DL 1 , DL 2 is IML, the condition (C1) means that the following equation (3) is met.

Δ VfL≤IML ×{( RO 2+ RN 2)−( RO 1+ RN 1)}  (eq 3)

With the conditions (A1)-(C1), as shown in FIG. 16 , the current-voltage characteristics of the first and second lower arm diodes DL 1 , DL 2 and the respective impedances RO 1 , RO 2 , RN 1 , RN 2 are defined such that a maximum value ΔILr of an absolute difference between the voltage drop VfL 1 across the first lower arm diode DL 1 and the voltage drop VfL 2 across the second lower arm diode DL 2 is less than the lower arm maximum current difference ΔILmax.

The current-voltage characteristics of the first and second lower arm diodes DL 1 , DL 2 and the respective impedances RO 1 , RO 2 , RN 1 , RN 2 may be defined as shown in FIG. 17 . In the example of FIG. 17 , (RO 2 +RN 2 ) minus (RO 1 +RN 1 ) is greater than in the example of FIG. 16 .

The current-voltage characteristics of the first and second lower arm diodes DL 1 , DL 2 and the impedances RO 1 , RO 2 , RN 1 , RN 2 may be set in the following manner. For example, given variations in the current-voltage characteristics of the diodes, each impedance may be changed. For example, given variations in the impedances, the current-voltage characteristics of the diodes may be changed.

The upper arm side will now be described. The upper arm side employs the following conditions (A2)-(C2).

(A2) As shown in FIG. 15 , the first intermediate voltage impedance RO 1 is set less than the second intermediate voltage impedance RO 2 , and the first high voltage impedance RP 1 is set less than the second high voltage impedance RP 2 .

(B2) As shown FIG. 15 , the voltage drop VfH 1 across the first upper arm diode DH 1 is set less than the voltage drop VfH 2 across the second upper arm diode DH 2 when a freewheeling current flows through each of the first and second upper arm diodes DH 1 , DH 2 .

(C2) The current-voltage characteristics of the first and second upper arm diodes DH 1 , DH 2 and the respective impedances RO 1 , RO 2 , RP 1 , RP 2 are defined such that an absolute difference value between the voltage drop VfH 1 across the first upper arm diode DH 1 and the voltage drop VfH 2 across the second upper arm diode DH 2 when a freewheeling current flows through each of the first and second upper arm diodes DH 1 , DH 2 is set equal to or less than an absolute difference value between the voltage drop VfH 1 across the first upper arm diode DH 1 and the voltage drop VfH 2 across the second upper arm diode DH 2 under assumption that the freewheeling current flowing through the first upper arm diode DH 1 is as large as the freewheeling current flowing through the second upper arm diode DH 2 . When the freewheeling current through each of the first and second upper arm diodes DH 1 , DH 2 is IML, the condition (C2) means that the following equation (4) is met.

Δ VfH≤IMH ×{( RO 2+ RP 2)−( RO 1+ RP 1)}  (eq 4)

In the equation (4), ΔVfH is an upper arm potential difference. The upper arm potential difference ΔVfH is the voltage drop VfH 1 across the first upper arm diode DH 1 minus the voltage drop VfH 2 across the second upper arm diode DH 2 .

With the conditions (A2)-(C2), the current-voltage characteristics of the first and second upper arm diodes DH 1 , DH 2 and the respective impedances RO 1 , RO 2 , RP 1 , RP 2 are defined such that a maximum value ΔIHr of an absolute difference between the freewheeling current IH 1 through the first upper arm diode DH 1 and the freewheeling current IH 2 through the second upper arm diode DH 2 is less than an upper arm maximum current difference ΔIHmax. The upper arm maximum current difference ΔIHmax is a maximum value of an absolute difference between the freewheeling current IH 1 through the first upper arm diode DH 1 and the freewheeling current IH 2 through the second upper arm diode DH 2 under assumption that RO 1 =RO 2 and RP 1 =RP 2 .

In the present embodiment, on the lower arm side, the low-voltage power source terminal TCN corresponds to a freewheeling current input. The intermediate terminal TO corresponds to a freewheeling current output. The first lower arm diode DL 1 corresponds to a minimum diode. The second lower arm diode DL 2 corresponds to a maximum diode. The electrical path from the low-voltage power source terminal TCN to the intermediate terminal TO of the semiconductor module MS including the second lower arm diode DL 2 via the low voltage conductive member Bn, the low voltage connection 30 n , the switch low-voltage terminal TN, and the second lower arm diode DL 2 , corresponds to a maximum path. The electrical path from the low-voltage power source terminal TCN to the intermediate terminal TO of the semiconductor module MS including the first lower arm diode DL 1 via the low voltage conductive member Bn, the low voltage connection 30 n , the switch low-voltage terminal TN, and the first lower arm diode DL 1 , corresponds to a minimum path.

In the present embodiment, on the upper arm side, the intermediate terminal TO corresponds to a freewheeling current input. The high-voltage power source terminal TCP corresponds to a freewheeling current output. The first upper arm diode DH 1 corresponds to a minimum diode. The second upper arm diode DH 2 corresponds to a maximum diode. The electrical path from the intermediate terminal TO of the semiconductor module MS including the second upper arm diode DH 2 to the high-voltage power source terminal TCP via the second upper arm diode DH 2 , the switch high-voltage terminal TP, the high-voltage connection 30 p , and the high-voltage conductive member Bp, corresponds to a maximum path. The electrical path from the intermediate terminal TO of the semiconductor module MS including the first upper arm diode DH 1 to the high-voltage power source terminal TCP via the first upper arm diode DH 1 , the switch high-voltage terminal TP, the high-voltage connection 30 p , and the high-voltage conductive member Bp, corresponds to a minimum path.

Continuing with the lower arm example, the configuration of the present embodiment set forth above can suppress variations in impedance with the freewheeling current path from the low-voltage power source terminal TCN to the intermediate terminal TO via the first lower arm diode DL 1 and the freewheeling current path from the low-voltage power source terminal TCN to the intermediate terminal TO via the second lower arm diode DL 2 . Therefore, variations in voltage drop generated when a freewheeling current flows through each of the freewheeling current paths with the freewheeling current paths can be suppressed. This can suppress variations in difference between the freewheeling current values IL 1 , IL 2 , and can therefore suppress variations in timing of completion of passage of the recovery current with the freewheeling current paths. As a result, variations in potential difference between the emitters of the first and second lower arm switches SL 1 , SL 2 can be suppressed.

Second Embodiment

A second embodiment is similar in configuration to the first embodiment. Therefore, only differences of the second embodiment from the first embodiment will be described. In the present embodiment, instead of the condition (C 1 ) set forth above, a condition (D 1 ) is employed on the lower arm side.

(D 1 ) As shown in FIG. 18 , the current-voltage characteristics of the first and second lower arm diodes DL 1 , DL 2 and the respective impedances RO 1 , RO 2 , RN 1 , RN 2 are defined such that an absolute difference value between the voltage drop VfL 1 across the first lower arm diode DL 1 and the voltage drop VfL 2 across the second lower arm diode DL 2 when a freewheeling current flows through each of the first and second lower arm diodes DL 1 , DL 2 is set equal to an absolute difference value between the voltage drop VfL 1 across the first lower arm diode DL 1 and the voltage drop VfL 2 across the second lower arm diode DL 2 under assumption that the freewheeling current flowing through the first lower arm diode DL 1 is as large as the freewheeling current flowing through the second lower arm diode DL 2 . Particularly, in the present embodiment, the current-voltage characteristics of the first and second lower arm diodes DL 1 ,DL 2 are defined such that ΔVfL=ΔVfLmax/2, where the following equation (5) is met.

In the present embodiment, the current-voltage characteristics of the first and second lower arm diodes DL 1 , DL 2 and the respective impedances RO 1 , RO 2 , RN 1 , RN 2 are defined such that a maximum value of an absolute difference between the freewheeling current IL 1 and the freewheeling current IL 2 is equal to or less than the lower arm maximum current difference ΔILmax/2.

The upper arm side employs a condition (D2) instead of (C2).

(D2) The current-voltage characteristics of the first and second upper arm diodes DH 1 , DH 2 and the respective impedances RO 1 , RO 2 , RP 1 , RP 2 are defined such that an absolute difference value between the voltage drop VfH 1 across the first upper arm diode DH 1 and the voltage drop VfH 2 across the second upper arm diode DH 2 when a freewheeling current flows through each of the first and second upper arm diodes DH 1 , DH 2 is set equal to an absolute difference value between the voltage drop VfH 1 across the first upper arm diode DH 1 and the voltage drop VfH 2 across the second upper arm diode DH 2 under assumption that the freewheeling current flowing through the first upper arm diode DH 1 is as large as the freewheeling current flowing through the second upper arm diode DH 2 . Particularly, in the present embodiment, the current-voltage characteristics of the first and second upper arm diodes DH 1 , DH 2 are defined such that ΔVfH=ΔVfHmax/2, where the following equation (6) is met.

ΔVfH=|ΔVfHmax| means that the current-voltage characteristic of the first upper arm diode DH 1 is the maximum characteristic Vfmax and the current-voltage characteristic of the second upper arm diode DH 2 is the minimum characteristic Vfmin. ΔVfHmax is hereinafter referred to as an upper arm maximum potential difference ΔVfHmax.

In the present embodiment, the current-voltage characteristics of the first and second upper arm diodes DH 1 , DH 2 and the respective impedances RO 1 , RO 2 , RP 1 , RP 2 are defined such that a maximum value of an absolute difference between the freewheeling current IH 1 and the freewheeling current IH 2 is equal to or less than the upper arm maximum potential difference ΔIHmax/2.

Continuing with the lower arm example, the configuration of the present embodiment set forth above can eliminate imbalances between the freewheeling current values IL 1 , IL 2 . As a result, variations in potential difference between the emitters of the first and second lower arm switches SL 1 , SL 2 can be further suppressed.

Third Embodiment

A third embodiment is similar in configuration to the first embodiment. Therefore, only differences of the third embodiment from the first embodiment will be described. In the present embodiment, as shown in FIG. 19 , for each of the three phases, each of the upper and lower arms includes three switches. FIG. 19 illustrates a circuit diagram of the inverter 20 for one of the three phases. In FIG. 19 , the same elements as shown in FIG. 1 are assigned the same numbers for simplicity.

The inverter 20 further includes, for each of of the three phases, a series connection of a third upper arm switch SH 3 and a third lower arm switch SL 3 . In the present embodiment, each switch SH 3 , SL 3 is a voltage control type semiconductor switch element, more specifically, an insulated gate bipolar transistor (IGBT).

A third upper arm diode DH 3 is electrically connected in anti-parallel with the third upper arm switch SH 3 . A third lower arm diode DL 3 is electrically connected in anti-parallel with the third lower arm switch SL 3 . Each of the diodes DH 3 , DL 3 may be integrated within a corresponding one of the switches SH 3 , SL 3 to provide an IGBT with a built-in diode or may be external to a corresponding one of the switches SH 3 , SL 3 . In the present embodiment, the third upper arm switch SH 3 , the third upper arm diode DH 3 , the third lower arm switch SL 3 , and the third lower arm diode DL 3 are enclosed and integrated within a casing to provide a semiconductor module MS.

For each of the three phases, intermediate terminals TO of the three semiconductor modules MS are electrically connected to a first conductive connection Bm 1 . The first connection Bm 1 is electrically connected to a first end of a winding 21 A of the rotary electric machine 21 via a second conductive connection Bm 2 .

In the present embodiment, an upper arm drive circuit DrH drives the first to third upper arm switches SH 1 -SH 3 . In the present embodiment, the first to third upper arm switches SH 1 -SH 3 are on-off driven in synchronization with each other. The lower arm drive circuit DrL drives the first to third lower arm switches SL 1 -SL 3 . In the present embodiment, the first to third lower arm switches SL 1 -SL 3 are on-off driven in synchronization with each other.

FIG. 20 illustrates a configuration for any one of the three phases. For sake of simplicity, in FIG. 20 , the intermediate terminal TO of the semiconductor module MS including the first upper and lower arm switches SH 1 , SL 1 , the intermediate terminal TO of the semiconductor module MS including the second upper and lower arm switches SH 2 , SL 2 , and the intermediate terminal TO of the semiconductor module MS including the third upper and lower arm switches SH 3 , SL 3 are represented by a single intermediate terminal TO. In addition, in FIG. 20 , a voltage drop across the third lower arm diode DL 3 is denoted by VfL 3 (IL 3 ), a voltage drop across the third upper arm diode DH 3 is denoted by VfH 3 (IH 3 ). IL 3 represents a value of freewheeling current through the third lower arm diode DL 3 . IH 3 represents a value of freewheeling current through the third upper arm diode DH 3 .

FIG. 20 illustrates an impedance of each electrical path. Descriptions of FIG. 20 overlapping with the descriptions of FIG. 7 will be mitted.

As shown in FIG. 20 , a third high-voltage impedance RP 3 is an impedance of an electrical path from the high-voltage power source terminal TCP to the collector of the third upper arm switch SH 3 via the high-voltage conductive member Bp, the high-voltage connection 30 p , and the switch high-voltage terminal TP of the semiconductor module MS including the third upper arm diode DH 3 .

A first intermediate voltage impedance RA 1 is an impedance of an electrical path from the intermediate terminal TO to the emitter of the first upper arm switch SH 1 in the semiconductor module MS including the first upper arm diode DH 1 . A second intermediate voltage impedance RA 2 is an impedance of an electrical path from the intermediate terminal TO to the emitter of second upper arm switch SH 2 in the semiconductor module MS including the second upper arm diode DH 2 . A third intermediate voltage impedance RA 3 is an impedance of an electrical path from the intermediate terminal TO to the emitter of the third upper arm switch SH 3 in the semiconductor module MS including the third upper arm diode DH 3 .

A fourth intermediate voltage impedance RB 1 is an impedance of an electrical path from the intermediate terminal TO to the collector of the first lower arm switch SL 1 in the semiconductor module MS including the first lower arm diode DL 1 . A fifth intermediate voltage impedance RB 2 is an impedance of an electrical path from the intermediate terminal TO to the collector of the second lower arm switch SL 2 in the semiconductor module MS including the second lower arm diode DL 2 . A sixth intermediate voltage impedance RB 3 is an impedance of an electrical path from the intermediate terminal TO to the collector of the third lower arm switch SL 3 in the semiconductor module MS including the third lower arm diode DL 3 .

A third low voltage impedance RN 3 is an impedance of an electrical path from the lower-voltage power source terminal TCN to the emitter of the third lower arm switch SL 3 via the low voltage conductive member Bn, the low voltage connection 30 n , and the switch low-voltage terminal TN of the semiconductor module MS including the third lower arm diode DL 3 .

To reduce a maximum value of an absolute difference between the freewheeling currents, the configuration of the present embodiment will now be described.

For each of the three phases, the lower arm side employs the following conditions (E1)-(G1).

(E1) The impedances are defined such that RB 1 =RB 3 >RB 2 and RN 1 =RN 3 >RN 2 .

(F1) The current-voltage characteristics of the respective lower arm diodes DL 1 -DL 3 are defined such that voltage drops VfL 1 -VfL 3 across the respective lower arm diodes DL 1 -DL 3 when a freewheeling current flows through each of the first to third lower arm diodes DL 1 -DL 3 satisfy the following relation: VfL 1 =VfL 3 <VfL 2 .

(G1) The current-voltage characteristics of the respective lower arm diodes DL 1 -DL 3 and the respective impedances RB 1 -RB 3 and RN 1 -RN 3 are defined such that an absolute difference value between the voltage drop VfL 1 across the first lower arm diode DL 1 and the voltage drop VfL 2 across the second lower arm diode DL 2 when a freewheeling current flows through each of the lower arm diodes DL 1 -DL 3 is set equal to or less than an absolute difference value between the voltage drop VfL 1 across the first lower arm diode DL 1 and the voltage drop VfL 2 across the second lower arm diode DL 2 under assumption that an equal current flows through each of the lower arm diodes DL 1 -DL 3 , i.e., IL 1 =IL 2 =IL 3 . IL 1 represents a value of freewheeling current flowing through the lower arm diode DL 1 . IL 2 represents a value of freewheeling current flowing through the lower arm diode DL 2 . IL 3 represents a value of freewheeling current flowing through the lower arm diode DL 3 .

For each of the three phases, the upper arm side employs the following conditions (E2)-(G2).

(E2) The impedances are defined such that RA 1 =RA 3 >RA 2 and RP 1 =RP 3 >RP 2 .

(F2) The current-voltage characteristics of the respective upper arm diodes DH 1 -DH 3 are defined such that voltage drops VfH 1 -VfH 3 across the respective upper arm diodes DH 1 -DH 3 when a freewheeling current flows through each of the first to third upper arm diodes DH 1 -DH 3 satisfy the following relation: VfH 1 =VfH 3 <VfH 2 .

(G2) The current-voltage characteristics of the respective upper arm diodes DH 1 -DH 3 and the respective impedances RA 1 -RA 3 and RP 1 -RP 3 are defined such that an absolute difference value between the voltage drop VfH 1 across the first upper arm diode DH 1 and the voltage drop VfH 2 across the second upper arm diode DH 2 when a freewheeling current flows through each of the upper arm diodes DH 1 -DH 3 is set equal to or less than an absolute difference value between the voltage drop VfH 1 across the first upper arm diode DH 1 and the voltage drop VfH 2 across the second upper arm diode DH 2 under assumption that an equal current flows through each of the upper arm diodes DH 1 -DH 3 , i.e., IH 1 =IH 2 =IH 3 . IH 1 represents a value of freewheeling current flowing through the upper arm diode DH 1 . IH 2 represents a value of freewheeling current flowing through the upper arm diode DH 2 . IH 3 represents a value of freewheeling current flowing through the upper arm diode DH 3 .

In the present embodiment, on the lower arm side, the second lower arm diode DL 2 corresponds to a minimum diode. Each of the first and third lower arm diodes DL 1 , DL 3 corresponds to a maximum diode. The electrical path from the low-voltage power source terminal TCN to the intermediate terminal TO of the semiconductor module MS including the first lower arm diode DL 1 via the low voltage conductive member Bn, the low voltage connection 30 n , the switch low-voltage terminal TN, and the first lower arm diode DL 1 , corresponds to a maximum path. The electrical path from the low-voltage power source terminal TCN to the intermediate terminal TO of the semiconductor module MS including the third lower arm diode DL 3 via the low voltage conductive member Bn, the low voltage connection 30 n , the switch low-voltage terminal TN, and the third lower arm diode DL 3 , corresponds to a maximum path. The electrical path from the low-voltage power source terminal TCN to the intermediate terminal TO of the semiconductor module MS including the second lower arm diode DL 2 via the low voltage conductive member Bn, the low voltage connection 30 n , the switch low-voltage terminal TN, and the second lower arm diode DL 2 , corresponds to a minimum path.

In the present embodiment, on the upper arm side, the second upper arm diode DH 2 corresponds to a minimum diode. Each of the first and third upper arm diodes DH 1 , DH 3 corresponds to a maximum diode. The electrical path from the intermediate terminal TO of the semiconductor module MS including the first upper arm diode DH 1 to the high-voltage power source terminal TCP via the first upper arm diode DH 1 , the switch high-voltage terminal TP, the high-voltage connection 30 p , and the high-voltage conductive member Bp, corresponds to a maximum path. The electrical path from the intermediate terminal TO of the semiconductor module MS including the third upper arm diode DH 3 to the high-voltage power source terminal TCP via the third upper arm diode DH 3 , the switch high-voltage terminal TP, the high-voltage connection 30 p , and the high-voltage conductive member Bp, corresponds to a maximum path. The electrical path from the intermediate terminal TO of the semiconductor module MS including the second upper arm diode DH 2 to the high-voltage power source terminal TCP via the second upper arm diode DH 2 , the switch high-voltage terminal TP, the high-voltage connection 30 p , and the high-voltage conductive member Bp, corresponds to a minimum path.

With the configuration of the present embodiment set forth above, variations in potential difference between the emitters of the first to third lower arm switches SL 1 -SL 3 and variations in potential difference between the emitters of the first to third upper arm switches SH 1 -SH 3 can be suppressed.

Forth Embodiment

A fourth embodiment is similar in configuration to the third embodiment. Therefore, only differences of the fourth embodiment from the third embodiment will be described. In the present embodiment, as shown in FIG. 21 , settings of the respective impedances and the current-voltage characteristics of the respective diode are modified.

For each of the three phases, the lower arm side employs the following conditions (H1)-(I1) and (G1) set forth above.

(H1) The impedances are defined such that RB 1 =RB 3 <RB 2 and RN 1 =RN 3 <RN 2 .

(I1) The current-voltage characteristics of the respective lower arm diodes DL 1 -DL 3 are defined such that voltage drops VfL 1 -VfL 3 across the respective lower arm diodes DL 1 -DL 3 when a freewheeling current flows through each of the first to third lower arm diodes DL 1 -DL 3 satisfy the following relation: VfL 1 =VfL 3 >VfL 2 .

For each of the three phases, the upper arm side employs the following conditions (H2)-(I2) and (G2) set forth above.

(H2) The impedances are defined such that RA 1 =RA 3 <RA 2 and RP 1 =RP 3 <RP 2 .

(I2) The current-voltage characteristics of the respective upper arm diodes DH 1 -DH 3 are defined such that voltage drops VfH 1 -VfH 3 across the respective upper arm diodes DH 1 -DH 3 when a freewheeling current flows through each of the first to third upper arm diodes DH 1 -DH 3 satisfy the following relation: VfH 1 =VfH 3 >VfH 2 .

In the present embodiment, on the lower arm side, each of the first and third lower arm diodes DL 1 , DL 3 corresponds to a minimum diode. The second lower arm diode DL 2 corresponds to a maximum diode. The electrical path from the low-voltage power source terminal TCN to the intermediate terminal TO of the semiconductor module MS including the second lower arm diode DL 2 via the low voltage conductive member Bn, the low voltage connection 30 n , the switch low-voltage terminal TN, and the second lower arm diode DL 2 , corresponds to a maximum path. The electrical path from the low-voltage power source terminal TCN to the intermediate terminal TO of the semiconductor module MS including the first lower arm diode DL 1 via the low voltage conductive member Bn, the low voltage connection 30 n , the switch low-voltage terminal TN, and the first lower arm diode DL 1 , corresponds to a minimum path. The electrical path from the low-voltage power source terminal TCN to the intermediate terminal TO of the semiconductor module MS including the third lower arm diode DL 3 via the low voltage conductive member Bn, the low voltage connection 30 n , the switch low-voltage terminal TN, and the third lower arm diode DL 3 , corresponds to a minimum path.

In the present embodiment, on the upper arm side, each of the first and third upper arm diodes DH 1 , DH 3 corresponds to a minimum diode. The second upper arm diode DH 2 corresponds to a maximum diode. The electrical path from the intermediate terminal TO of the semiconductor module MS including the second upper arm diode DH 2 to the high-voltage power source terminal TCP via the second upper arm diode DH 2 , the switch high-voltage terminal TP, the high-voltage connection 30 p , and the high-voltage conductive member Bp, corresponds to a maximum path. The electrical path from the intermediate terminal TO of the semiconductor module MS including the first upper arm diode DH 1 to the high-voltage power source terminal TCP via the first upper arm diode DH 1 , the switch high-voltage terminal TP, the high-voltage connection 30 p , and the high-voltage conductive member Bp, corresponds to a maximum path. The electrical path from the intermediate terminal TO of the semiconductor module MS including the third upper arm diode DH 3 to the high-voltage power source terminal TCP via the third upper arm diode DH 3 , the switch high-voltage terminal TP, the high-voltage connection 30 p , and the high-voltage conductive member Bp, corresponds to a minimum path.

The present embodiment can provide similar advantages to those of the third embodiment.

Fifth Embodiment

A fifth embodiment is similar in configuration to the third embodiment. Therefore, only differences of the fifth embodiment from the third embodiment will be described. In the present embodiment, as shown in FIG. 22 , settings of the respective impedances and the current-voltage characteristics of the respective diode are modified.

For each of the three phases, the lower arm side employs the following conditions (J1)-(L1).

(J1) The impedances are defined such that RB 1 >RB 2 >RB 3 and RN 1 >RN 2 >RN 3 .

(K1) The current-voltage characteristics of the respective lower arm diodes DL 1 -DL 3 are defined such that voltage drops VfL 1 -VfL 3 across the respective lower arm diodes DL 1 -DL 3 when a freewheeling current flows through each of the first to third lower arm diodes DL 1 -DL 3 satisfy the following relation: VfL 1 <VfL 2 <VfL 3 .

(L1) The current-voltage characteristics of the respective lower arm diodes DL 1 -DL 3 and the respective impedances RB 1 -RB 3 and RN 1 -RN 3 are defined such that an absolute difference value between the voltage drop VfL 1 across the first lower arm diode DL 1 and the voltage drop VfL 3 across the third lower arm diode DL 3 when a freewheeling current flows through each of the lower arm diodes DL 1 -DL 3 is set equal to or less than an absolute difference value between the voltage drop VfL 1 across the first lower arm diode DL 1 and the voltage drop VfL 3 across the third lower arm diode DL 3 under assumption that an equal current flows through each of the lower arm diodes DL 1 -DL 3 , i.e., IL 1 =IL 2 =IL 3 .

For each of the three phases, the upper arm side employs the following conditions (J2)-(L2).

(J2) The impedances are defined such that RA 1 >RA 2 >RA 3 and RP 1 >RP 2 >RP 3 .

(K2) The current-voltage characteristics of the respective upper arm diodes DH 1 -DH 3 are defined such that voltage drops VfH 1 -VfH 3 across the respective upper arm diodes DH 1 -DH 3 when a freewheeling current flows through each of the first to third upper arm diodes DH 1 -DH 3 satisfy the following relation: VfH 1 <VfH 2 <VfH 3 .

(L2) The current-voltage characteristics of the respective upper arm diodes DH 1 -DH 3 and the respective impedances RA 1 -RA 3 and RP 1 -RP 3 are defined such that an absolute difference value between the voltage drop VfH 1 across the first upper arm diode DH 1 and the voltage drop VfH 3 across the third upper arm diode DH 3 when a freewheeling current flows through each of the upper arm diodes DH 1 -DH 3 is set equal to or less than an absolute difference value between the voltage drop VfH 1 across the first upper arm diode DH 1 and the voltage drop VfH 3 across the third upper arm diode DH 3 under assumption that an equal current flows through each of the upper arm diodes DH 1 -DH 3 , i.e., IH 1 =IH 2 =IH 3 .

In the present embodiment, on the lower arm side, the third lower arm diodes DL 3 corresponds to a minimum diode. The first lower arm diode DL 1 corresponds to a maximum diode. The electrical path from the low-voltage power source terminal TCN to the intermediate terminal TO of the semiconductor module MS including the first lower arm diode DL 1 via the low voltage conductive member Bn, the low voltage connection 30 n , the switch low-voltage terminal TN, and the first lower arm diode DL 1 , corresponds to a maximum path. The electrical path from the low-voltage power source terminal TCN to the intermediate terminal TO of the semiconductor module MS including the third lower arm diode DL 3 via the low voltage conductive member Bn, the low voltage connection 30 n , the switch low-voltage terminal TN, and the third lower arm diode DL 3 , corresponds to a minimum path.

In the present embodiment, on the upper arm side, the third upper arm diodes DH 3 corresponds to a minimum diode. The first upper arm diode DH 1 corresponds to a maximum diode. The electrical path from the intermediate terminal TO of the semiconductor module MS including the first upper arm diode DH 1 to the high-voltage power source terminal TCP via the first upper arm diode DH 1 , the switch high-voltage terminal TP, the high-voltage connection 30 p , and the high-voltage conductive member Bp, corresponds to a maximum path. The electrical path from the intermediate terminal TO of the semiconductor module MS including the third upper arm diode DH 3 to the high-voltage power source terminal TCP via the third upper arm diode DH 3 , the switch high-voltage terminal TP, the high-voltage connection 30 p , and the high-voltage conductive member Bp, corresponds to a maximum path.

The present embodiment set forth above in detail can provide similar advantages to those of the third embodiment.

Sixth Embodiment

A sixth embodiment of the present disclosure will now be described with reference to FIGS. 23 and 24 . In FIGS. 23 and 24 , the configuration of each of the semiconductor module MS and the conductive members Bp, Bn of the first embodiment is modified. In FIG. 24 , an electrically insulating film or sheet (not shown) may be interposed between the high-voltage conductive member Bp and the low voltage conductive member Bn.

The present embodiment can provide similar advantages to those of the first embodiment.

Modifications

It is to be understood that the invention is not to be limited to the specific embodiments disclosed above and that modifications and other embodiments are intended to be included within the scope of the appended claims.

(M1) In a first modification, referring to FIG. 16 , on either or both of the lower and upper arm side, the current-voltage characteristics of the first and second lower arm diodes DL 1 , DL 2 may be set within the range ADX on the condition that a maximum value of an absolute difference between the freewheeling current IL 1 and the freewheeling current IL 2 is less than the lower arm maximum current difference ΔILmax.

(M2) In a second modification, the configuration of the second embodiment may be applied to each of the third to fifth embodiments.

(M3) In a third modification, setting techniques set forth above for the impedances and the diode characteristics to prevent occurrence of the imbalance phenomenon may be applied to only one of the lower and upper arm sides.

(M4) In each of the third to fifth embodiments, the number of switches may be greater than three on each of the upper and lower arm sides.

(M5) In a fifth modification, each of the switches forming the power converter may be an N-channel MOSFET. In this modification, the control terminal is a gate of the N-channel MOSFET, the input terminal is a drain of the N-channel MOSFET, and the output terminal is a source of the N-channel MOSFET. In addition, the freewheeling diode may be a parasitic diode of the N-channel MOSFET or a freewheeling diode external to the N-channel MOSFET.

(M6) In each of the above embodiments, the power converter is a three-phase power converter. In an alternative embodiment, the power converter may be a two-phase or four- or more-phase power converter. The power converter of each of the above embodiments is not limited to a vehicle-mounted power converter.