Anti-floating circuit

The invention relates to an anti-floating circuit, and more particularly to an anti-floating circuit which comprises a pull-high circuit and a pull-low circuit.

With the development of technology, the size of integrated circuits has been greatly reduced. Generally, each integrated circuit operates according to at least one input signal. However, when the input signal is not the correct signal, a false action may be caused in the integrated circuit.

An anti-floating circuit generates a first output signal according to a first input signal in a first mode and sets the first output signal to a first predetermined value in a second mode. The anti-floating circuit comprises a first pull-high circuit, a first pull-low circuit and a first control circuit. The first pull-high circuit comprises a first P-type transistor and a second P-type transistor. The first P-type transistor comprises a source coupled to a first power terminal and a drain outputting the first output signal. The second P-type transistor comprises a source coupled to the first power terminal, a drain coupled to a gate of the first P-type transistor and a gate coupled to the drain of the first P-type transistor. The first pull-low circuit comprises a first N-type transistor and a second N-type transistor. The first N-type transistor comprises a gate receiving a first inverted signal and a source coupled to a second power terminal. The second N-type transistor comprises a gate receiving the first input signal and a source coupled to the second power terminal. The first control circuit is coupled between the first pull-high circuit and the first pull-low circuit. In the first mode, the first control circuit turns on a first path between the first P-type transistor and the first N-type transistor and a second path between the second P-type transistor and the second N-type transistor and turns off a third path between the first P-type transistor and the second power terminal. In the second mode, the first control circuit turns off the first and second paths and turns on the third path.

The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1A is a schematic diagram of an exemplary embodiment of an anti-floating circuit according to various aspects of the present disclosure.

FIG. 1B is a schematic diagram of another exemplary embodiment of the anti-floating circuit according to various aspects of the present disclosure.

FIG. 2A is a schematic diagram of an exemplary embodiment of a signal generator circuit according to various aspects of the present disclosure.

FIG. 2B is a schematic diagram of another exemplary embodiment of the signal generator circuit according to various aspects of the present disclosure.

FIG. 3A is a schematic diagram of an exemplary embodiment of a pulse generator circuit according to various aspects of the present disclosure.

FIG. 3B is a schematic diagram of another exemplary embodiment of the pulse generator circuit according to various aspects of the present disclosure.

FIG. 4 is a schematic diagram of an exemplary embodiment of a delay circuit according to various aspects of the present disclosure.

FIG. 5 is a schematic diagram of another exemplary embodiment of the delay circuit according to various aspects of the present disclosure.

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

FIG. 1A is a schematic diagram of an exemplary embodiment of an anti-floating circuit according to various aspects of the present disclosure. The anti-floating circuit 100 A comprises a signal generator circuit 110 and a core circuit 120 . The signal generator circuit 110 is coupled between a power terminal PW 1 and a power terminal PW 2 and generates an output signal OUT 1 . In one embodiment, the signal generator circuit 110 is a level shifter. In this case, the signal generator circuit 110 transforms an input signal IN 1 to generate the output signal OUT 1 .

When the input signal IN 1 is at a first level, the output signal OUT 1 is at a second level. When the input signal IN 1 is at a third level, the output signal OUT 1 is at a fourth level. In one embodiment, the second level is higher than the first level. For example, the first level is approximately 3.3V and the second level is approximately 6V˜7V. In addition, the third level may be equal to the fourth level, such as 0V.

In another embodiment, the first level is higher than the second level and the fourth level is higher than the third level. In this case, the fourth level may be higher than the first level. For example, the first level is about 3.3V and the fourth level is about 6V˜7V. Additionally, the second level may be equal to the third level, such as 0V.

In another embodiment, when the input signal IN 1 is at a fifth level (e.g. a high level), the output signal OUT 1 is at a sixth level (e.g. a low level). When the input signal IN 1 is at a seventh level (e.g. another low level), the output signal OUT 1 is at an eighth level (e.g. another high level). In this case, the eighth level is higher than the fifth level. For example, the fifth level is about 3.3V and the eighth level is about 6V˜7V. Furthermore, the sixth level may be equal to the seventh level, such as 0V.

The core circuit 120 is coupled between the power terminals PW 1 and PW 2 and receives the output signal OUT 1 . In one embodiment, the core circuit 120 is a non-volatile memory (NVM), but the disclosure is not limited thereto. In other embodiments, the core circuit 120 may be another memory circuit. Generally, the core circuit 120 comprises a plurality of elements. For brevity, only the elements related to the invention are shown in FIG. 1A and the load 122 represent the other elements in the core circuit 120 .

As shown in FIG. 1A , the core circuit 120 at least comprises a switch 121 . In this embodiment, the switch 121 is coupled between the power terminal PW 1 and the load 122 . The switch 122 determines whether to transmit the voltage of the power terminal PW 1 to the load 122 according to the output signal OUT 1 . For example, when the output signal OUT 1 is at a first state (e.g. a low level or a high level), the switch 121 transmits the voltage of the power terminal PW 1 to the load 122 . In this case, when the output signal OUT 1 is at a second state (e.g. a high level or a low level), the switch 121 does not transmit the voltage of the power terminal PW 1 to the load 122 . In one embodiment, the switch 121 is a P-type transistor, but the disclosure is not limited thereto. In other embodiment, the switch 121 may be coupled between the power terminal PW 2 and the load 122 and determines whether to transmit the voltage of the power terminal PW 2 to the load 122 according to the output signal OUT 1 .

Since the signal generator circuit 110 generates the output signal OUT 1 according to the input signal IN 1 , when the input signal IN 1 is not ready to be transmitted to the signal generator circuit 110 , the output signal OUT 1 may be at a floating level. Therefore, because the output signal OUT 1 is at an error level, the switch 121 may be turned on causing a false action to occur in the core circuit 120 . Furthermore, while the switch 121 is turned on, if an electrostatic discharge (ESD) event occurs between the power terminals PW 1 and PW 2 , an ESD current passes from the switch 121 to the core circuit 120 , damaging the core circuit 120 .

Therefore, in a not-ready mode, since the input signal IN 1 has not reached a target level, the signal generator circuit 110 sets the level of the output signal OUT 1 to a predetermined level so that the switch 121 is turned off. Therefore, the false action does not occur in the core circuit 120 . In addition, in this mode, if an ESD event occurs between the power terminals PW 1 and PW 2 , since the switch 121 is turned off, the ESD current does not pass into the core circuit 120 .

In a ready mode, since the input signal IN 1 has reached the target level, the signal generator circuit 110 generates the output signal OUT 1 according to the input signal IN 1 . In this mode, since the power terminals PW 1 and PW 2 have received corresponding operation voltages (e.g. 6V and 0V). Therefore, the signal generator circuit 110 sets the high level of the output signal OUT 1 so that it is equal to the voltage of the power terminal PW 1 and sets the low level of the output signal OUT 1 so that it is equal to the voltage of the power terminal PW 2 .

FIG. 1B is a schematic diagram of another exemplary embodiment of the anti-floating circuit according to various aspects of the present disclosure. FIG. 1B is similar to FIG. 1A except that the anti-floating circuit 100 B shown in FIG. 1B further comprises a signal generator circuit 130 . In this embodiment, the signal generator circuit 130 is also coupled between the power terminals PW 1 and PW 2 and generates an output signal OUT 2 according to an input signal IN 2 . In one embodiment, the signal generator circuit 130 is a level shifter. In this case, the signal generator circuit 130 transforms the input signal IN 2 to generate the output signal OUT 2 . In other embodiments, the input signal IN 1 may be the same as or different from the input signal IN 2 . Since the operation of the signal generator circuit 130 is the same as the operation of the signal generator circuit 110 , the description of the operation of the signal generator circuit 130 is omitted.

In this embodiment, the core circuit 120 further comprises a switch 123 . The switch 123 is coupled to the load 122 in series and determines whether to transmit the voltage of the power terminal PW 2 to the load 122 according to the output signal OUT 2 . For example, when the output signal OUT 2 is at a first state, such as a low level or a high level, the switch 123 does not transmit the power of the power terminal PW 2 to the load 122 . In this case, when the output signal OUT 2 is at a second state, such as a high level or a low level, the switch 123 transmits the voltage of the power terminal PW 2 to the load 122 . In one embodiment, the switch 123 is an N-type transistor, but the disclosure is not limited thereto. In other embodiments, the switch 123 is a P-type transistor.

In some embodiments, the kind of switch 121 and the kind of switch 123 are the same. For example, the switches 121 and 123 are P-type transistors or N-type transistors. In another embodiment, the kind of switch 121 is different from the kind of switch 123 . For example, when the switch 121 is a P-type transistor, the switch 123 is an N-type transistor. When the switch 121 is an N-type transistor, the switch 123 is a P-type transistor. In other embodiments, when the switch 121 is turned on, the switch 123 is also turned on. When the switch 121 is turned off, the switch 123 is also turned off.

In a not-ready mode, since the input signals IN 1 and IN 2 has not reached the corresponding target levels, the signal generator circuit 110 sets the level of the output signal OUT 1 to a first predetermined value and the signal generator circuit 130 sets the level of the output signal OUT 2 to a second predetermined value so that the switches 121 and 123 are turned off. Since the switches 121 and 123 are turned off, a false action does not occur in the core circuit 120 . Furthermore, since the switches 121 and 123 are turned off, an ESD current does not enter the core circuit 120 .

When the input signal IN 1 reaches a first target level and the input signal IN 2 reaches a second target level, the signal generator circuits 110 and 130 operate in a ready mode. In this mode, the signal generator circuit 110 generates the output signal OUT 1 according to the input signal IN 1 to turn on or off the switch 122 . Additionally, the signal generator circuit 130 generates the output signal OUT 2 according to the input signal IN 2 to turn on or off the switch 123 . Since the signal generator circuits 110 and 130 generate the accurate output signals OUT 1 and OUT 2 , the false action does not occur in the core circuit 120 .

FIG. 2A is a schematic diagram of an exemplary embodiment of a signal generator circuit according to various aspects of the present disclosure. The signal generator circuit 200 A comprises a pull-high circuit 210 , a control circuit 220 and a pull-low circuit 230 . The pull-high circuit 210 comprises P-type transistors 211 and 212 . The source of the P-type transistor 211 is coupled to the power terminal PW 1 . The drain of the P-type transistor 212 is coupled to the gate of the P-type transistor 211 and the control circuit 220 . The gate of the P-type transistor 212 is coupled to the drain of the P-type transistor 211 . In one embodiment, when the signal generator circuit 200 A serves as the signal generator circuit 110 or 130 shown in FIG. 1B , the output signal OUT shown in FIG. 2A serves as the output signal OUT 1 or OUT 2 .

The pull-low circuit 230 comprises N-type transistors 231 and 232 . The gate of the N-type transistor 231 receives an inverted signal INB. The source of the N-type transistor 231 is coupled to the power terminal PW 2 . The drain of the N-type transistor 231 is coupled to the control circuit 220 . The gate of the N-type transistor 232 receives the input signal IN. The source of the N-type transistor 232 is coupled to the power terminal PW 2 . The drain of the N-type transistor 232 is coupled to the control circuit 220 . In this embodiment, the inverted signal INB is an inversion signal of the input signal IN.

In one embodiment, when the signal generator circuit 200 A serves as the signal generator circuit 110 or 130 shown in FIG. 1B , the input signal IN shown in FIG. 2A serves as the input signal IN 1 or IN 2 . In other embodiments, the signal generator circuit 200 A further comprises an inverter (not shown), which inverts the input signal IN to generate the inverted signal INB. In some embodiments, the inverter is disposed outside of the signal generator circuit 200 A.

The control circuit 220 is coupled between the pull-high circuit 210 and the pull-low circuit 230 . In a ready mode (e.g. the input signal IN is ready), the control circuit 220 turns on a path PA 1 between the P-type transistor 211 and the N-type transistor 231 and a path PA 2 between the P-type transistor 212 and the N-type transistor 232 . At this time, the control circuit 220 turns off a path PA 3 between the P-type transistor 211 and the power terminal PW 2 . In this mode, the signal generator circuit 200 A generates the output signal OUT according to the input signal IN.

When the input signal IN has not reached a target level or the input signal IN has not entered the signal generator circuit 200 A yet, the signal generator circuit 200 A operates in a not-ready mode. In the not-ready mode, the control circuit 220 turns off the paths PA 1 and PA 2 and turns on the path PA 3 . In this mode, the control circuit 220 sets the level of the output signal OUT to a predetermined value to turn off the switch (e.g. the switch 121 shown in FIG. 1A ) disposed in the core circuit to avoid a false action occurring in the core circuit.

In this embodiment, the control circuit 220 comprises control elements 221 ˜ 223 . The control element 221 is coupled between the drain of the P-type transistor 211 and the drain of the N-type transistor 231 . The control element 221 turns on or off the path PA 1 according to a pulse signal OS_NB. In a ready mode (i.e. the input signal IN is ready), the pulse signal OS_NB is at a first level. Therefore, the control element 221 turns on the path PA 1 . In a not-ready mode (i.e. the input signal IN is not ready), the pulse signal OS_NB is at a second level. Therefore, the control element 221 turns off the path PA 1 .

The kind of control element 221 is not limited in the present disclosure. In this embodiment, the control element 221 is an N-type transistor 224 . The gate of the N-type transistor 224 receives the pulse signal OS_NB. The drain of the N-type transistor 224 is coupled to the drain of the P-type transistor 211 . The source of the N-type transistor 224 is coupled to the drain of the N-type transistor 231 . In the ready mode, the pulse signal OS_NB is at a high level so that the N-type transistor 224 is turned on. Therefore, the path PA 1 is turned on. In the not-ready mode, the pulse signal OS_NB is at a low level so that the N-type transistor 224 is turned off. Therefore, the path PA 1 is turned off. In other embodiments, the control element 221 is a P-type transistor.

The control element 222 is coupled between the drain of the P-type transistor 212 and the drain of the N-type transistor 232 . The control element 222 controls the path PA 2 according to the pulse signal OS_NB. In the ready mode (e.g. the input signal IN has reached a target level), the pulse signal OS_NB is at a first level. Therefore, the control element 222 turns on the path PA 2 . In the not-ready mode (e.g. the input signal IN has not reached the target level), the pulse signal OS_NB is at a second level. Therefore, the control element 222 does not turn on the path PA 2 .

The kind of control element 222 is not limited in the present disclosure. In this embodiment, the control element 222 is an N-type transistor 225 . The gate of the N-type transistor 225 receives the pulse signal OS_NB. The drain of the N-type transistor 225 is coupled to the drain of the P-type transistor 212 . The source of the N-type transistor 225 is coupled to the drain of the N-type transistor 232 . In the ready mode, the pulse signal OS_NB is at a high level so that the N-type transistor 225 is turned on. Therefore, the path PA 2 is turned on. In the not-ready mode, the pulse signal OS_NB is at a low level so that the N-type transistor 225 is turned off. Therefore, the path PA 2 does not be turned on. In some embodiments, the control element is a P-type transistor.

The control element 223 is coupled between the gate of the P-type transistor 211 and the power terminal PW 2 . The control element 223 turns on or off the path PA 3 between the P-type transistor 211 and the power terminal PW 2 according to the pulse signal OS_N. In a not-ready mode, the pulse signal OS_N is at a third level. Therefore, the control element 223 turns on the path PA 3 . In a ready mode, the pulse signal OS_N is at a fourth level. Therefore, the control element does not turn on the path PA 3 .

The invention does not limit the kind of the control element 223 . In this embodiment, the control element 223 is an N-type transistor 226 . The gate of the N-type transistor 226 receives the pulse signal OS_N. The drain of the N-type transistor 226 is coupled to the gate of the P-type transistor 211 . The source of the N-type transistor 226 is coupled to the power terminal PW 2 . In the ready mode, the pulse signal OS_N is at a low level so that the N-type transistor 226 is turned off. Therefore, the path PA 3 is turned off. In the not-ready mode, since the pulse signal OS_N is at a high level, the N-type transistor 226 is turned on. Therefore, the path PA 3 is turned on. In some embodiments, the control element 223 is a P-type transistor.

In one embodiment, the pulse signal OS_N is opposite to the pulse signal OS_NB, but the disclosure is not limited thereto. When the control elements 221 and 222 are N-type transistors and the control element 223 is a P-type transistor, the pulse generator circuit 240 generates a single pulse signal to control the control elements 221 ˜ 223 . In another embodiment, when the control elements 221 and 222 are P-type transistors and the control element 223 is an N-type transistor, the pulse generator circuit 240 only generate a pulse signal to control the control elements 221 ˜ 223 .

In this embodiment, the pulse signals OS_NB and OS_N are generated by the pulse generator circuit 240 . The pulse generator circuit 240 is coupled between the power terminals PW 1 and PW 2 . The pulse generator circuit 240 generates the pulse signals OS_NB and OS_N according to the voltages of the power terminals PW 1 and PW 2 . In some embodiments, different pulse generator circuits may generate different pulse signals.

Taking FIG. 1B as an example, the number of pulse signal generated by the pulse generator circuit of the signal generator circuit 110 may be the same as or different from the number of pulse signal generated by the pulse generator circuit of the signal generator circuit 130 . Additionally, at least one of the pulse signals generated by the pulse generator circuit of the signal generator circuit 110 may be the same as or different from at least one of the pulse signal generated by the pulse generator circuit of the signal generator circuit 130 . The operating configuration of the pulse generator circuit 240 is described in greater detail with reference to FIGS. 3A and 3B .

FIG. 2B is a schematic diagram of another exemplary embodiment of the signal generator circuit according to various aspects of the present disclosure. FIG. 2B is similar to FIG. 2A except that the signal generator circuit 200 B shown in FIG. 2B further comprises an inverter 250 . The inverter 250 is coupled between the power terminals PW 1 and PW 2 . The input terminal of the inverter 250 is coupled to the drain of the P-type transistor 211 to receive the output signal OUT. The output terminal of the inverter 250 is configured to provide the output signal OUTB. In one embodiment, the output signal OUTB is capable of serving as the output signal OUT 1 or OUT 2 in FIG. 1B .

In this embodiment, the inverter 250 comprises a P-type transistor 251 and an N-type transistor 252 . The source of the P-type transistor 251 is coupled to the power terminal PW 1 . The gate of the P-type transistor 251 is coupled to the drain of the P-type transistor 211 . The drain of the P-type transistor 251 provides the output signal OUTB. The gate of the N-type transistor 252 is coupled to the drain of the P-type transistor 211 . The drain of the N-type transistor 252 is coupled to the drain of the P-type transistor 251 . The source of the N-type transistor 252 is coupled to the power terminal PW 2 .

FIG. 3A is a schematic diagram of an exemplary embodiment of a pulse generator circuit according to various aspects of the present disclosure. The pulse generator circuit 300 A comprises a delay circuit 310 and a logic circuit 320 . The delay circuit 310 and the logic circuit 320 are coupled between the power terminals PW 1 and PW 2 . The voltages of the power terminals PW 1 and PW 2 are served as the operation voltages of the delay circuit 310 and the logic circuit 320 .

The delay circuit 310 delays the voltage of the power terminal PW 1 to generate a delay signal VD. The logic circuit 320 generates the pulse signal OS_N according to the level V PW1 of the power terminal PW 1 and the delay signal VD. In this embodiment, when the level V PW1 of the power terminal PW 1 and the delay signal VD are at high levels, the pulse signal OS_N is at a low level. When one of the level V PW1 of the power terminal PW 1 and the delay signal VD is at a low level, the pulse signal OS_N is at a high level.

In one embodiment, the logic circuit 320 is a NAND gate 321 . One input terminal of the NAND gate 321 receives the level V PW1 of the power terminal PW 1 . Another input terminal of the NAND gate 321 receives the delay signal VD. The output terminal of the NAND gate 321 provides the pulse signal OS_N. In other embodiments, other circuit structure can serve as the logic circuit 320 .

Taking FIG. 2A as an example, assume that the control elements 221 and 222 are N-type transistors and the control element 223 is a P-type transistor. In this case, the pulse generator circuit 300 A provides the pulse signal OS_N to the gates of the control elements 221 ˜ 223 . In a ready mode, the pulse signal OS_N is at a high level to turn on the control elements 221 and 222 and turn off the control element 223 . Therefore, the paths PA 1 and PA 2 are turned on and the path PA 3 is turned off. At this time, the signal generator circuit 200 A generates the output signal OUT according to the input signal IN. In a not-ready mode, the pulse signal OS_N is at a low level to turn off the control elements 221 and 222 and turn on the control element 223 . Therefore, the paths PA 1 and PA 2 are turned off and the path PA 3 is turned on. At this time, the signal generator circuit 200 A sets the output signal OUT to a predetermined level to turn off the switch 121 of the core circuit 120 , avoiding a false action in the core circuit 120 and avoiding an ESD current entering the core circuit 120 . In other embodiments, when the control elements 221 and 222 are P-type transistors and the control element 223 is an N-type transistor, the pulse generator circuit 240 only generates a single pulse signal to control the control elements 221 ˜ 223 simultaneously.

FIG. 3B is a schematic diagram of another exemplary embodiment of the pulse generator circuit according to various aspects of the present disclosure. FIG. 3B is similar to FIG. 3A except that the pulse generator circuit 300 B of FIG. 3B further comprises an inverter 330 . The inverter 330 inverts the pulse signal OS_N to generate the pulse signal OS_NB. Taking FIG. 2A as an example, the pulse signal OS_N is at a high level and the pulse signal OS_NB is at a low level in a not-ready mode. Therefore, the paths PA 1 and PA 2 are turned off and the path PA 3 is turned on. In this mode, the signal generator circuit 200 A sets the level of the output signal OUT to a predetermined value. In a ready mode, the pulse signal OS_N is at a low level and the pulse signal OS_NB is at a high level. Therefore, the paths PA 1 and PA 2 are turned on and the path PA 3 is turned off. In this mode, the signal generator circuit 200 A generates the output signal OUT according to the input signal IN.

FIG. 4 is a schematic diagram of an exemplary embodiment of a delay circuit according to various aspects of the present disclosure. The delay circuit 400 comprises inverters 410 and 430 and capacitors 420 and 440 . The number of inverters is not limited in the present disclosure. In one embodiment, the delay circuit 400 comprises even inverters.

In this embodiment, the inverter 410 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 411 and an output terminal 412 . The input terminal 411 is coupled to the power terminal PW 1 . In one embodiment, the inverter 410 comprises a P-type transistor 413 and an N-type transistor 414 . The gate of the P-type transistor 413 is coupled to the input terminal 411 . The source of the P-type transistor 413 is coupled to the power terminal PW 1 . The drain of the P-type transistor 413 is coupled to the output terminal 412 . The gate of the N-type transistor 414 is coupled to the input terminal 411 . The source of the N-type transistor 414 is coupled to the power terminal PW 2 . The drain of the N-type transistor 414 is coupled to the output terminal 412 .

The capacitor 420 is coupled between the power terminal PW 1 and the output terminal 412 . In this embodiment, the capacitor 420 is a P-type transistor 421 . The gate of the P-type transistor 421 is coupled to the output terminal 421 . The drain and the source of the P-type transistor 421 are coupled to the power terminal PW 1 .

The inverter 430 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 431 and an output terminal 432 . The input terminal 431 is coupled to the output terminal 412 . The output terminal 432 is configured to provide the delay signal VD. In one embodiment, the inverter 430 comprises a P-type transistor 433 and an N-type transistor 434 . The gate of the P-type transistor 433 is coupled to the input terminal 431 . The source of the P-type transistor 433 is coupled to the power terminal PW 1 . The drain of the P-type transistor 433 is coupled to the output terminal 432 . The gate of the N-type transistor 434 is coupled to the input terminal 431 . The source of the N-type transistor 434 is coupled to the power terminal PW 2 . The drain of the N-type transistor 434 is coupled to the output terminal 432 .

The capacitor 440 is coupled between the power terminal PW 2 and the output terminal 432 . In this embodiment, the capacitor 440 is an N-type transistor 441 . The gate of the N-type transistor 441 is coupled to the output terminal 432 . The drain and the source of the N-type transistor 441 are coupled to the power terminal PW 2 .

FIG. 5 is a schematic diagram of another exemplary embodiment of the delay circuit according to various aspects of the present disclosure. The delay circuit 500 at least comprises inverters 510 and 520 . The inverter 510 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 511 and an output terminal 512 . The input terminal 511 is coupled to the power terminal PW 1 . In one embodiment, the inverter 510 comprises a P-type transistor 513 and an N-type transistor 514 . The gate of the P-type transistor 513 is coupled to the input terminal 511 . The source of the P-type transistor 513 is coupled to the power terminal PW 1 . The drain of the P-type transistor 513 is coupled to the output terminal 512 . The gate of the N-type transistor 514 is coupled to the input terminal 511 . The source of the N-type transistor 514 is coupled to the power terminal PW 2 . The drain of the N-type transistor 514 is coupled to the output terminal 512 .

The inverter 520 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 521 and an output terminal 522 . The input terminal 521 is coupled to the output terminal 512 . In one embodiment, the inverter 520 comprises a P-type transistor 523 and an N-type transistor 524 . The gate of the P-type transistor 523 is coupled to the input terminal 521 . The source of the P-type transistor 523 is coupled to the power terminal PW 1 . The drain of the P-type transistor 523 is coupled to the output terminal 522 . The gate of the N-type transistor 524 is coupled to the input terminal 521 . The source of the N-type transistor 524 is coupled to the power terminal PW 2 . The drain of the N-type transistor 524 is coupled to the output terminal 522 . In one embodiment, when the delay circuit 500 only comprises the inverters 510 and 520 , the output terminal 522 is configured to provide the delay signal VD.

In other embodiments, the delay circuit 500 further comprises inverters 530 and 540 . The inverter 530 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 531 and an output terminal 532 . The input terminal 531 is coupled to the output terminal 522 . In one embodiment, the inverter 530 comprises a P-type transistor 533 and an N-type transistor 534 . The gate of the P-type transistor 533 is coupled to the input terminal 531 . The source of the P-type transistor 533 is coupled to the power terminal PW 1 . The drain of the P-type transistor 533 is coupled to the output terminal 532 . The gate of the N-type transistor 534 is coupled to the output terminal 531 . The source of the N-type transistor 534 is coupled to the power terminal PW 2 . The drain of the N-type transistor 534 is coupled to the output terminal 532 .

The inverter 540 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 541 and an output terminal 542 . The input terminal 541 is coupled to the output terminal 532 . In one embodiment, the inverter 540 comprises a P-type transistor 543 and an N-type transistor 544 . The gate of the P-type transistor 543 is coupled to the input terminal 541 . The source of the P-type transistor 543 is coupled to the power terminal PW 1 . The drain of the P-type transistor 543 is coupled to the output terminal 542 . The gate of the N-type transistor 544 is coupled to the input terminal 541 . The source of the N-type transistor 544 is coupled to the power terminal PW 2 . The drain of the N-type transistor 544 is coupled to the output terminal 542 to provide the delay signal VD. The number of inverters is not limited in the present disclosure. In one embodiment, the delay circuit 500 comprises even inverters.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). For example, it should be understood that the system, device and method may be realized in software, hardware, firmware, or any combination thereof. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.