Method of adjusting signal to noise ratio of SRAM and invertor structure

1. Field of the Invention

The present invention relates to a method of adjusting a signal to noise ratio (SNR) of a static random access memory (SRAM) and an inverter structure, and more particularly to a method of adjusting the SNR and efficiency of the inverter structure by altering a gate length.

2. Description of the Prior Art

A static random access memory (SRAM) cell comprises a logic circuit connected to a static random access memory. An SRAM is a kind of volatile memory cell, which means it preserves data only while power is continuously applied. An SRAM is built of cross-coupled inverters that store data while power remains applied, unlike a dynamic random access memory (DRAM) which needs to be periodically refreshed. SRAM is also used in computer systems as a cache memory. As the speed of electronic elements increases, however, the SRAM needs to achieve a higher performance.

Accordingly, it is a primary object of the present invention to provide an SRAM with high performance. According to one embodiment of the present invention, an inverter structure includes a substrate divided into a P-type transistor region and an N-type transistor region. A first fin structure is disposed within the P-type transistor region. A second fin structure is disposed within the N-type transistor region, wherein the first fin structure and the second fin structure are parallel. A gate line is disposed within the P-type transistor region and the N-type transistor region, and the gate line is perpendicular to the first fin structure, wherein the gate line includes a first end within the P-type transistor region and a second end within the N-type transistor region. Two first dummy gate lines are respectively disposed at two sides of the gate line, the two first dummy gate lines being perpendicular to the first fin structure, wherein each of the first dummy gate lines includes a third end within the P-type transistor region and a fourth end within the N-type transistor region. A first distance between the first end and the first fin structure is greater than a third distance between the third end and the first fin structure, and a second distance between the second end and the second fin structure is smaller than a fourth distance between the fourth end and the second fin structure.

According to another embodiment of the present invention, a method of adjusting an SNR of an SRAM includes providing a substrate. A first long fin structure and a second long fin structure are disposed on the substrate, and a first short fin structure and a second short fin structure are disposed on the substrate and between the first long fin structure and the second long fin structure. A first gate line crosses the first long fin structure and the first short fin structure. The second long fin structure and the second gate line crosses the first long fin structure, the second short fin structure and the second long fin structure, wherein the first long fin structure comprises a first side and a second side, the second side faces the first short fin structure, the first side is opposite to the second side, the second long fin structure comprises a third side and the fourth side, the fourth side faces the second short fin structure, and the third side is opposite to the fourth side. Later, a gate line cutting step is performed, wherein the gate line cutting step includes removing the second gate line between the first long fin structure and the second short fin structure by a first length, removing the first gate line between the second long fin structure and the first short fin structure by the first length, removing the first gate line at the first side of the first long fin structure by a second length, and removing the second gate line at the third side of the second long fin structure by the second length. An SNR of an SRAM which has the first length greater than the second length is greater than an SNR of an SRAM which has the first length equal to the second length.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 to FIG. 2 depict a method of fabricating an SRAM according to a first preferred embodiment of the present invention.

FIG. 3 to FIG. 4 depict a method of adjusting an SNR of an SRAM according to a second preferred embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of an SRAM in FIG. 4 of the present invention.

FIG. 6 to FIG. 7 depict a method of adjusting an SNR of an SRAM according to a third preferred embodiment of the present invention.

FIG. 8 depicts an inverter structure according to a fourth preferred embodiment of the present invention.

FIG. 9 depicts an N-type transistor structure according to a fifth preferred embodiment of the present invention.

FIG. 10 depicts a P-type transistor structure according to a sixth preferred embodiment of the present invention.

FIG. 1 to FIG. 2 depict a method of fabricating an SRAM according to a first preferred embodiment of the present invention.

As shown in FIG. 1 , a substrate 10 is provided. A first long fin structure 12 a , a second long fin structure 12 b , a first short fin structure 14 a , and a second short fin structure 14 b are disposed on the substrate 10 . The first short fin structure 14 a and the second short fin structure 14 b are disposed between the first long fin structure 12 a and the second long fin structure 12 b . The first long fin structure 12 a , the second long fin structure 12 b , the first short fin structure 14 a and the second short fin structure 14 b are parallel. Furthermore, a first gate line 16 a crosses the first long fin structure 12 a , the first short fin structure 14 a and the second long fin structure 12 b . A second gate line 16 b crosses the first long fin structure 12 a , the second short fin structure 14 b and the second long fin structure 12 b . The first gate line 16 a and the second gate line 16 b are parallel. It is noteworthy that the first short fin 14 a does not overlap or cross the second gate line 16 b , and the second short fin structure 14 b does not overlap or cross the first gate line 16 a . In detail, the first long fin structure 12 a includes a first side 18 and a second side 20 . The second side 20 faces the first short fin structure 14 a . The first side 18 is opposite to the second side 20 . The second long fin structure 12 b includes a third side 22 and a fourth side 24 . The fourth side 24 faces the second short fin structure 14 b . The third side 22 is opposite to the fourth side 24 . The substrate 10 may be a bulk silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate or a silicon carbide substrate. The first long fin structure 12 a , the second long fin structure 12 b , the first short fin structure 14 a and the second short fin structure 14 b may extend from the substrate 10 and are made of the same material as the substrate 10 . The first gate line 16 a and the second gate line 16 b may include a conductive polysilicon and a gate dielectric layer.

Then, a gate line cutting step is performed by the following steps. A basic length L is provided. The basic length L, the first gate line 16 a and the second gate line 16 b are parallel. The second gate line 16 b between the first long fin structure 12 a and the second short fin structure 14 b , the first gate line 16 a between the second long fin structure 12 b and the first short fin structure 14 a , the first gate line 16 a at the first side 18 of the first long fin structure 12 a and the second gate line 16 b at the third side 22 of the second long fin structure 12 b are removed by the basic length L, i.e. the first gate line 16 a and the second gate line 16 b are respectively removed by two discontinuous basic lengths L. As shown in FIG. 2 , after the gate line cutting step, the first gate line 16 a is divided into three first gate line segments 116 a , and the second gate line 16 b is divided into three second gate line segments 116 b . Next, a dielectric layer 26 is formed to encapsulate an end of each of the first gate line segments 116 a , and an end of each of the second gate line segments 116 b.

The gate line cutting step may be performed by a lithographic process and an etching process. For example, a photoresist (not shown) is formed to cover the substrate 10 , the first long fin structure 12 a , the second long fin structure 12 b , the first short fin structure 14 a , the second short fin structure 14 b , the first gate line 16 a and the second gate line 16 b . Later, a photo mask is used to pattern the photoresist and define a region 19 . The region 19 includes the position to be removed from the first gate line 16 a and the second gate line 16 b . Subsequently, the basic length L of the first gate line 16 a and the basic length L of the second gate line 16 b are removed simultaneously by an etching process to form numerous first gate line segments 116 a and numerous second gate line segments 116 b.

Continue to refer to FIG. 2 . The first gate line segments 116 a , the second gate line segments 116 b , the first long fin structure 12 a , the second long fin structure 12 b , the first short fin structure 14 a and the second short fin structure 14 b together form an SRAM structure 100 . The SRAM structure 100 has an initial signal-to-noise ratio (SNR), and an initial read current.

FIG. 3 to FIG. 4 depict a method of adjusting an SNR of an SRAM according to a second preferred embodiment, wherein elements which substantially have the same position and function as those in the first preferred embodiment are denoted by the same reference numerals.

As shown in FIG. 3 , a substrate 10 , a first long fin structure 12 a , a second long fin structure 12 b , a first short fin structure 14 a , a second short fin structure 14 b , a first gate line 16 a and a second gate line 16 b are provided, wherein details of the materials and positions of the substrate 10 , the first long fin structure 12 a , the second long fin structure 12 b , the first short fin structure 14 a , the second short fin structure 14 b , the first gate line 16 a and the second gate line 16 b can be known by referring to the first preferred embodiment.

Next, a gate line cutting step is performed as follows. A first length L 1 and a second length L 2 are provided. The first length L 1 is greater than the basic length L in the first preferred embodiment, and the second length L 2 is smaller than the basic length L in the first preferred embodiment, i.e. the first length L 1 is greater than the second length L 2 . The first length L 1 , the second length L 2 and the basic length L are parallel. The first length L 1 on the first gate line 16 a equals the basic length L plus a first adjusted length d 1 in a direction toward the second long fin structure 12 b . The first length L 1 on the second gate line 16 b equals the basic length L plus the first adjusted length d 1 in a direction toward the first long fin structure 12 a . A second length L 2 on the first gate line 16 a equals the basic length L minus a second adjusted length d 2 in a direction away from the third side 22 . The second length L 2 on the second gate line 16 b equals the basic length L minus the second adjusted length d 2 in a direction away from the first side 18 . The first adjusted length d 1 may be equal to or not equal to the second adjusted length d 2 . As in the first preferred embodiment, the gate line cutting step may be performed by a lithographic process and an etching process.

During the gate line cutting step, the first gate line 16 a between the second long fin structure 12 b and the first short fin structure 14 a , near the second short fin structure 14 b and the second long fin structure 12 b , and away from the first short fin structure 14 a , is removed by the first length L 1 . The second gate line 16 b between the first long fin structure 12 a and the second short fin structure 14 b , near the first long fin structure 12 a and the first short fin structure 14 a , and away from the second short fin structure 14 b , is removed by the first length L 1 . The first gate line 16 a at the first side 18 of the first long fin structure 12 a is removed by the second length L 2 . The second gate line 16 b at the third side 22 of the second long fin structure 12 b is removed by the second length L 2 .

As shown in FIG. 4 , after the gate line cutting step, the first gate line 16 a is divided into three first gate line segments 116 a , and the second gate line 16 b is divided into three second gate line segments 116 b . At this point, two first gate line segments 116 a , two second gate line segments 116 b , the first long fin structure 12 a , the second long fin structure 12 b , the first short fin structure 14 a and the second short fin structure 14 b form an SRAM 200 . Next, a dielectric layer 26 is formed to encapsulate an end of each of the first gate line segments 116 a , and an end of each of the second gate line segments 116 b . The dielectric layer 26 may be silicon nitride, silicon oxide or other insulating materials.

An overlapped region of the first long fin structure 12 a and one of the first gate line segments 116 a forms a first pull-down transistor PD 1 , an overlapped region of the first long fin structure 12 a and one of the second gate line segments 116 b forms a first pass gate transistor PG 1 , an overlapped region of the first short fin structure 14 a and one of the first gate line segments 116 a forms a first pull-up transistor PU 1 , an overlapped region of the second short fin structure 14 b and one of the second gate line segments 116 b forms a second pull-up transistor PU 2 , an overlapped region of the second long fin structure 12 b and one of the first gate line segments 116 a forms a second pass gate transistor PG 2 , and an overlapped region of the second long fin structure 12 b and one of the second gate line segments 116 b forms a second pull-down transistor PD 2 .

The different between the first preferred embodiment and the second preferred embodiment is that the gate lines are removed by different lengths. Furthermore, the gate line segments within the first pass gate transistor PG 1 and the second pass gate transistor PG 2 in the second preferred embodiment is shorter than the gate line segments at the same position in the first preferred embodiment. The gate line segments within the first pull-down transistor PD 1 and the second pull-down transistor PD 2 in the second preferred embodiment is longer than the gate line segments at the same position in the first preferred embodiment. Because the dielectric layer 26 contains stress, stress can be respectively transferred from the end of the first gate line segments 116 a and the end of the second gate line segments 116 b to the first gate line segments 116 a and the second gate line segments 116 b . As a result, the stresses in the first pass gate transistor PG 1 , the second pass gate transistor PG 2 , the first pull-down transistor PD 1 and the second pull-down transistor PD 2 in the second preferred embodiment are different from those in the first preferred embodiment. Therefore, the threshold voltage of each of the transistors in the second preferred embodiment is different from that in the first preferred embodiment. In the end, the SNR of the SRAM 200 is greater than the SRN of the SRAM 100 .

FIG. 5 is an equivalent circuit diagram of an SRAM in FIG. 4 of the present invention. As shown in FIG. 4 and FIG. 5 , a first pull-up transistor PU 1 , a second pull-up transistor PU 2 , a first pull-down transistor PD 1 and a second pull-down transistor PD 2 constitute a latch circuit that stores data in the storage nodes 28 or 30 . The first pull-up transistor PU 1 and the first pull-down transistor PD 1 form an inverter, and respectively electrically connect to a voltage source (voltage node) Vcc and a voltage source (voltage node) Vss. The second pull-up transistor PU 2 and the second pull-down transistor PD 2 form another inverter, and respectively electrically connect to the voltage source Vcc and the voltage source Vss. The aforesaid inverters couple to each other to store data.

Preferably, the first pull-up transistor PU 1 , and the second pull-up transistor PU 2 are composed of p-type metal oxide semiconductor (PMOS) transistors; the first pull-down transistor PD 1 , the second pull-down transistor PD 2 , the first pass gate devices PG 1 and the second pass gate devices PG 2 are composed of n-type metal oxide semiconductor (NMOS) transistors, but the invention is not limited thereto. The storage node 30 electrically connects to a source of the first pass gate transistor PG 1 , and the storage node 28 electrically connects to a source of the second pass gate transistor PG 2 . The gates of the first pass gate transistor PG 1 and the second pass gate transistor PG 2 are respectively coupled to a word line (WL), and the drain of the first pass gate device PG 1 and the second pass gate device PG 2 are respectively coupled to a bit line BL 1 and a bit line BL 2 .

FIG. 6 to FIG. 7 depict a method of adjusting an SNR of an SRAM according to a third preferred embodiment, wherein elements which substantially have the same position and function as those in the first preferred embodiment are denoted by the same reference numerals. In the third preferred embodiment, a third length L 3 replaces the first length L 1 in the second preferred embodiment. Furthermore, in the third preferred embodiment, the second length L 2 is still used in the same position as in the second preferred embodiment. In detail, the third length L 3 equals the basic length L minus a third adjusted length d 3 in a direction away from the first long fin structure 12 a and the second long fin structure 12 b . In other words, the third length L 3 is shorter than the basic length L. An SRAM formed by the method in the third preferred embodiment has a read current greater than the initial read current of the SRAM 100 .

FIG. 8 depicts an inverter structure according to a fourth preferred embodiment of the present invention. The inverter structure can be used in the SRAM. The inverter structure includes a substrate 50 . The substrate includes a P-type transistor region 52 and an N-type transistor region 54 . A first fin structure 56 a is disposed within the P-type transistor region 52 . A second fin structure 56 b is disposed within the N-type transistor region 54 . The first fin structure 56 a and the second fin structure 56 b are parallel. A gate line 58 is disposed within the P-type transistor region 52 and the N-type transistor region 54 , wherein the gate line 58 is perpendicular to the first fin structure 56 a and the second fin structure 56 b . The gate line 58 includes a first end 158 within the P-type transistor region 52 and a second end 258 within the N-type transistor region 54 . Two first dummy gate lines 60 are respectively disposed at two sides of the gate line 58 , and the first dummy gate lines 60 are perpendicular to the first fin structure 56 a and the second fin structure 56 b . Each of the first dummy gate lines 60 includes a third end 160 within the P-type transistor region 52 and a fourth end 260 within the N-type transistor region 54 . It is noteworthy that a first distance S 4 between the first end 158 and the first fin structure 56 a is greater than a third distance S 3 between the third end 160 and the first fin structure 56 a , and a second distance S 2 between the second end 258 and the second fin structure 56 b is smaller than a fourth distance S 4 between the fourth end 260 and the second fin structure 56 b . The first distance S 1 , the second distance S 2 , the third distance S 3 , the fourth distance S 4 , and the gate line 58 are parallel.

An overlapped region of the gate line 58 and the first fin structure 56 a forms a P-type gate. P-type source/drain regions (not shown) are respectively disposed in the first fin structure 56 a at two sides of the P-type gate. The P-type gate, the P-type source/drain doped regions and the first fin structure 56 a form a P-type transistor 62 , an overlapped region of the gate line 58 and the second fin structure 56 b forms an N-type gate, and two N-type source/drain doped regions are respectively disposed in the second fin structure 56 b at two sides of the N-type gate. The N-type gate, the N-type source/drain doped regions and the second fin structure 56 b form an N-type transistor 64 . The P-type transistor 62 and the N-type transistor 64 form an inverter.

Moreover, a dielectric layer 66 encapsulates the first end 158 , the second end 258 , the third end 160 and the fourth end 260 . The dielectric layer 66 can be silicon nitride, silicon oxide or other insulating materials. Moreover, the dielectric layer 66 contains stress, meaning the stress in the dielectric layer 66 can be applied to the first end 158 , the second end 258 , the third end 160 and the fourth end 260 to change the stress in the fin structure directly under the N-type gate or P-type gate. The stress in the dielectric layer 66 is tensile stress. Therefore, in the P-type transistor 62 , the farther the first end 158 is from the first fin structure 56 a of the P-type transistor 62 , the better the efficiency of the P-type transistor 62 can become. In the N-type transistor 64 , the closer the second end 258 is to the second fin structure 56 b of the N-type transistor 64 , the better the efficiency of the N-type transistor 64 can become.

According to another preferred embodiment of the present invention, the inverter structure may include two second dummy gate lines 68 . Each of the second dummy gate lines 68 is respectively disposed at one side of each of the two first dummy gate lines 60 , and is not between one of the first dummy gate lines 60 and the gate line 58 . The first dummy gate lines 60 and the second dummy gate lines 68 are both floating. Only the gate line 58 has a voltage applied. The first dummy gate lines 60 and the second dummy gate lines 68 are formed for preventing the loading effect.

Moreover, each of the second dummy gate lines 68 includes a fifth end 168 within the P-type transistor region 52 and a sixth end 268 within the N-type transistor region 54 , wherein the third distance S 3 is greater than a fifth distance S 5 between the fifth end 168 and the first fin structure 56 a , and the fourth distance S 4 is smaller than a sixth distance S 6 between the sixth end 268 and the second fin structure 56 b . Similarly, the fifth end 168 and the sixth end 268 are both encapsulated by the dielectric layer 66 . The distance between the ends of the first dummy gate lines 60 and the adjacent fin structure, and the distance between the ends of the second dummy gate lines 68 and the adjacent fin structure influences the stress applied to the P-type transistor 62 and N-type transistor 64 . The dummy gate line which is closer to the gate line 58 has a greater influence on the efficiency of the P-type transistor 62 and the N-type transistor 64 . That is, the third distance S 3 between the third end 160 and the first fin structure 56 a has more influence on the P-type transistor 62 than the fifth distance S 5 between the fifth 168 and the first fin structure 56 a . Similarly, the fourth distance S 4 between the fourth end 260 and the second fin structure 56 b has more influence on the N-type transistor 64 than the sixth distance S 6 between the sixth end 268 and the second fin structure 56 b . The distance between the end of the first dummy gate line 60 and the first fin structure 56 a , the distance between the end of the second dummy gate line 68 and the second fin structure 56 b are decided according to the distance between the first and second dummy gate lines 60 / 68 and the gate line 58 , and the ends of the first and second dummy gate lines 60 / 68 are close to the N-type transistor 64 or P-type transistor 62 . Therefore, the size of the distance between the first end 158 and the first fin structure 56 a , the distance between the third end 160 and the first fin structure 56 a , and the distance between the fifth end 168 and the first fin structure 56 a are ordered as: the first distance S 1 is the greatest, the third distance S 3 is the second greatest, and the fifth distance S 5 is the smallest. The size of the distance between the second end 258 and the second fin structure 56 b , the distance between the fourth end 260 and the second fin structure 56 b , and the distance between the sixth end 268 and the second fin structure 56 b are ordered as: the sixth distance S 6 is the greatest, the fourth distance S 4 is the second greatest, and the second distance S 2 is the smallest.

FIG. 9 depict an N-type transistor structure according to a fifth preferred embodiment of the present invention, wherein elements which substantially have the same position and function as those in the fourth preferred embodiment are denoted by the same reference numerals. In contrast to the fourth embodiment, there is only one second fin structure 56 b disposed within the N-type transistor region 54 and there is no P-type transistor region. The second end 258 of the gate line 58 , the fourth end 260 of the first dummy gate line 60 and the sixth end 258 of the second dummy gate line 68 are disposed following the principle in the fourth preferred embodiment, wherein the sixth distance S 6 is the greatest, the fourth distance S 4 is the second greatest and the second distance S 2 is the smallest. Moreover, one end of the gate line 58 , one end of the first dummy gate line 60 and one end of the dummy gate line 68 can be arranged by the principle in the fourth preferred embodiment, wherein the other end of the gate line 58 , the other end of the first dummy gate line 60 and the other end of the dummy gate line 68 can be aligned with each other. In other embodiments, as shown in FIG. 9 , two ends of the gate line 58 , two ends of the first dummy gate line 60 and two ends of the dummy gate line 68 are disposed followed the principle of the fourth preferred embodiment. In this way, the N-type transistor structure will have double the efficiency of the N-type transistor structure which has only one end of the first dummy gate line 60 and one end of the dummy gate line 68 arranged by the principle in the fourth preferred embodiment.

FIG. 10 depicts a P-type transistor structure according to a sixth preferred embodiment of the present invention, wherein elements which substantially have the same position and function as those in the fourth preferred embodiment are denoted by the same reference numerals. In contrast to the fourth embodiment, there is only one first fin structure 56 a disposed within the P-type transistor region 52 and there is no N-type transistor region. The first end 158 of the gate line 58 , the third end 160 of the first dummy gate line 60 and the fifth end 168 of the second dummy gate line 68 are disposed following the principle in the fourth preferred embodiment, wherein the first distance S 1 is the greatest, the third distance S 3 is the second greatest and the fifth distance S 5 is the smallest. One end of the gate line 58 , one end of the first dummy gate line 60 and one end of the dummy gate line 68 can be arranged by the principle in the fourth preferred embodiment, wherein the other end of the gate line 58 , the other end of the first dummy gate line 60 and the other end of the dummy gate line 68 can be aligned with each other. In other embodiments, as shown in FIG. 10 , two ends of the gate line 58 , two ends of the first dummy gate line 60 and two ends of the dummy gate line 68 are disposed followed the principle in the fourth preferred embodiment. In this way, the P-type transistor structure has double the efficiency of the P-type transistor structure which has only one end of the first dummy gate line 60 and one end of the dummy gate line 68 arranged by the principle in the fourth preferred embodiment.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.