Setting device and computer

The present disclosure relates to a setting device and a computer.

In recent years, cars are becoming more functional and diverse, and for example, cars in which motorized movement mechanisms based on motors are installed for doors and seats are being developed. Moreover, there is proposed a technique for controlling a load by using multiplex communication so as to control a motor load as a drive source for such a motorized mechanism.

Furthermore, according to the technique described above, to perform load control by using multiplex communication, a computer to be connected to a load is provided with a communication function, a control function, and an ID identification function.

As a method for setting an ID in the computer mentioned above, it is proposed to set an ID according to operation information of a load which is connected to an in-vehicle connector (computer) (JP 2008-155906 A). The operation information is a lock current of a motor, for example.

However, according to the conventional ID setting method described above, information, such as a lock current of a motor, which is unique to a load which is connected to an in-vehicle connector is set as the operation information. Accordingly, for example, if information such as the number of loads connected to the in-vehicle connector is set as the operation information, IDs are possibly overlapped.

Patent Literature

Patent Literature 1: JP 2008-155906 A

Technical Problem

The present disclosure has been made in view of the above circumstances, and has it object to provide a setting device which is capable of preventing overlapping of identification information of computers, and a computer in which identification information is set by the setting device.

Solution to Problem

A setting device being a first aspect of the present disclosure is a setting device for causing a plurality of computers connected to a load to set identification information, the setting device including: a first setting unit configured to cause each of the computers to set identification information according to first information related to the load; and a second setting unit configured to cause the plurality of computers to set identification information according to second information about the load different from the first information, in a case where pieces of identification information of the plurality of computers set by the first setting unit are overlapped.

Furthermore, a third setting unit configured to cause the computers to set identification information according to third information about the load different from the first information and the second information, in a case where pieces of identification information of the plurality of computers set by the second setting unit are overlapped, may be included.

Furthermore, each of the first information and the second information may be one of the number of loads connected to the computer, the number of parallel connections of loads connected to the computer, and a sum of drive currents flowing through loads connected to the computer.

Furthermore, the third information may be one of the number of loads connected to the computer, the number of parallel connections of loads connected to the computer, and a sum of drive currents flowing through loads connected to the computer.

A computer being a second aspect of the present disclosure is a computer for setting identification information of the computer in response to a request from a setting device, the computer including: a fourth setting unit configured to detect first information about a load connected to the computer, in response to a setting request from the setting device for identification information according to the first information, and to set the identification information of the computer; a fifth setting unit configured to detect second information about the load different from the first information, in response to a setting request from the setting device for identification information according to the second information, and to set the identification information of the computer; and a transmission unit configured to transmit, to the setting device, the identification information of the computer set by the fourth setting unit and the fifth setting unit.

Advantageous Effects of Invention

According to the present disclosure described above, overlapping of identification information of computers may be prevented.

FIG. 1 is a block diagram showing an in-vehicle network where gateways and ECUs are embedded as setting devices and computers, respectively, of the present disclosure;

FIG. 2 is a block diagram showing configurations of the gateway and the ECU shown in FIG. 1 ;

FIG. 3 is a flowchart showing ID setting processing by the gateway and the ECU shown in FIG. 1 ;

FIG. 4 is a flowchart showing following processes of the ID setting processing shown in FIG. 3 ;

FIG. 5 is a flowchart showing first setting processing by the ECU shown in FIG. 1 ;

FIG. 6 is a flowchart showing second setting processing by the ECU shown in FIG. 1 ;

FIG. 7 is a flowchart showing following processes of the second setting processing shown in FIG. 6 ; and

FIG. 8 is a flowchart showing third setting processing by the ECU shown in FIG. 1 .

Hereinafter, an embodiment of the present disclosure will be described with reference to FIGS. 1 and 2 . FIG. 1 is a block diagram showing an in-vehicle network where gateways and ECUs are embedded as setting devices and computers, respectively, of the present disclosure. FIG. 2 is a block diagram showing configurations of the gateway and the ECU shown in FIG. 1 .

An in-vehicle network 1 shown in FIG. 1 is installed in a vehicle 10 . The in-vehicle network 1 includes a plurality of gateways 2 as setting devices having a master function, and a plurality of ECUs 3 as computers having a slave function. The plurality of gateways 2 are disposed in respective areas of the vehicle 10 , and are communicably connected with one another by a communication line L 1 . The gateway 2 is communicably connected by a communication line L 2 to a plurality of ECUs 3 disposed in the area of the gateway 2 in question.

The gateway 2 controls operations of a plurality of ECUs 3 by communicating with the plurality of ECUs 3 . As shown in FIG. 2 , a plurality of loads 20 , such as a valve, a motor, and a lamp, are connected to the ECU 3 , and driving of the loads 20 is controlled by communication with the gateway 2 .

Next, a configuration of the gateway 2 described above will be described. As shown in FIG. 2 , the gateways 2 each include an interface (hereinafter “I/F”) 21 , and a microcomputer 22 . The I/F 21 is a communication interface for performing communication with other gateways 2 , and other ECUs 3 connected by the communication line L 2 . The I/F 21 is an interface allowing input/output of signals according to various communication schemes (such as CAN, LIN, and other communication schemes).

The microcomputer 22 is configured from a known central processing unit (CPU) 22 A, and a flash read only memory (ROM) 22 B. The CPU 22 A controls the entire gateway 2 , and performs various types of processing according to processing programs. The flash ROM 22 B is a memory for storing identification information (hereinafter “ID”) of the belonging gateway 2 , an ID of the ECU 3 connected to the gateway 2 , programs for the processing to be performed by the CPU 22 A, and the like.

Next, a configuration of the ECU 3 described above will be described. The plurality of the ECUs 3 have the same configuration, and the ECUs 3 each include an I/F 31 , a microcomputer 32 , a plurality of local SWs 33 , and a plurality of semiconductor relays CH 1 -CH 4 . The I/F 31 is a communication interface for performing communication with the gateway 2 , and allows input/output of signals according to various communication schemes (such as CAN, LIN, and other communication schemes).

The microcomputer 32 is configured from a CPU 32 A, and a flash ROM 32 B. The CPU 32 A controls the entire ECU 3 , and performs various types of processing according to processing programs. The flash ROM 32 B is a memory for storing an initial ID, programs for the processing to be performed by the CPU 32 A, variables, and set values, and in an initial state, the same contents are written in all the ECUs 3 . The initial ID is a provisional ID before assignment of a dedicated ID, and an initial ID for transmission and an initial ID for reception are set.

For example, in the present embodiment, “01010101” is stored as the initial ID for transmission, and “10101010” is stored as the initial ID for reception. Moreover, the programs for the processing to be performed by the CPU 32 A include a communicate program for communicating with another ECU 3 connected by the communication line L 2 , and system programs necessary for system operation.

The plurality of local SWs 33 are connected to the microcomputer 32 , and are configured to input on/off information to the microcomputer 32 . The plurality of semiconductor relays CH 1 -CH 4 are each connected between the microcomputer 32 and a load 20 , and are each switched on/off according to a drive signal from the microcomputer 32 . Furthermore, the semiconductor relay CH 1 -CH 4 has a current detection function for detecting a current flowing through itself, and inputs the detected current to the microcomputer 32 . In the present embodiment, the number of semiconductor relays CH 1 -CH 4 provided in the ECU 3 is described to be four, but this is not restrictive, and any number of semiconductor relays may be provided. All the ECUs 3 include the same number of semiconductor relays CH 1 -CH 4 .

Each ECU 3 described above has a function for setting an ID by rewriting an initial ID to a dedicated ID by performing ID setting processing with the gateway 2 . After the dedicated ID is set, the ECU 3 receives load control program data, which is transmitted from an external rewriting device by using the dedicated ID, and the ECU 3 is enabled to perform a load operation by writing the load control program data in the corresponding flash ROM 32 B.

Next, a description will be given of the dedicated ID mentioned above. As shown in Table 1 below, the dedicated ID is constructed from 6-bit network information, and 2-bit ECU number. In the present embodiment, the ECU number is composed of 2 bits, and thus, maximum four (=2×2) ECUs 3 can be connected to the gateway 2 , and dedicated IDs may be assigned to the ECUs 3 . In the present embodiment, a case where the ECU number is composed of 2 bits is described, but the number of ECUs that can be set may be increased by increasing the bit length.

As shown in Table 1, the network information is composed of information indicating a system, information indicating an area, information indicating a unit type, and information indicating a communication direction. The information indicating a system (2-bit) is information indicating the type of the load 20 connected to the ECU 3 . In the present embodiment, loads 20 to be connected to the ECU 3 are categorized into three types of a lamp system load, a door system load, and a seat system load. The information indicating an area (2-bit) is information indicating the area where the ECU 3 is disposed. In the present embodiment, areas are categorized into four areas of front, rear, left, and right of the vehicle. The information indicating a unit type is information indicating the type of a unit to which an ID is assigned. In the present embodiment, the ECU 3 is the only unit to which an ID is assigned. The ECU number is a number which is allocated to each ECU 3 connected to the gateway 2 within the area of the gateway 2 in question in a non-overlapping manner.

For example, a dedicated ID for transmission and a dedicated ID for reception as shown in Tables 2 and 3 below are allocated to the ECU 3 to which the lamp system load 20 is connected and which is disposed in a front right area.

Next, an operation of the in-vehicle network 1 configured in the above manner will be described with reference to the flowcharts in FIGS. 3 and 4 . First, after being activated, the microcomputer 32 of the ECU 3 (hereinafter simply “ECU”) checks an ID setting area in the flash ROM 32 B, and if the IDs are not initial IDs (initial ID for transmission: 01010101, initial ID for reception: 10101010) (step S 1 : N), performs normal processing (step S 2 ), and ends the processing.

On the other hand, if the IDs are initial IDs (step S 1 : Y), the ECU 3 transmits, to the gateway 2 , an ID setting signal requesting for setting of an ID with the initial ID for transmission attached thereto (step S 3 ). As shown in Table 4 below, the ID setting signal is an 8-bit signal where bit 7 is “1” and bit 6 -bit 0 are blank, and an initial ID is attached thereto.

After activation, if the ID setting signal from the ECU 3 is not received within a predetermined period of time T 1 (step S 20 : N), the microcomputer 22 of the gateway 2 (hereinafter simply “gateway 2 ”) performs normal processing (step S 21 ), and ends the processing.

On the other hand, after activation, if the ID setting signal from the ECU 3 is received within the predetermined period of time T 1 (step S 20 : Y), the gateway 2 functions as a first setting unit, and broadcasts a first request signal requesting for setting of an ID according to the number of loads 20 (first information) connected to the ECU 3 (step S 22 ). If the first request signal is not received within a predetermined period of time T 2 after transmission of the ID setting signal (step S 4 : N), the ECU 3 stops the processing (step S 5 ), and ends the processing.

If the first request signal is received within the predetermined period of time T 2 after transmission of the ID setting signal (step S 4 : Y), the ECU 3 acts as a fourth setting unit, and performs first setting processing for setting an ID according to the number of loads 20 (first information) connected to the ECU 3 (step S 6 ).

The first setting processing will be described below with reference to the flowchart in FIG. 5 . In the first setting processing, the ECU 3 switches on the semiconductor relay CH 1 (step S 601 ). Then, the ECU 3 determines whether or not a detected current detected by the semiconductor relay CH 1 is at or above a determination current (step S 602 ). If the detected current of the semiconductor relay CH 1 is at or above a predetermined threshold (step S 602 : Y), the ECU 3 determines that a load 20 is connected to the semiconductor relay CH 1 (downstream connection present) (step S 605 ). On the other hand, if the detected current of the semiconductor relay CH 1 is below the determination current (step S 602 : N), the ECU 3 determines that a load 20 is not connected to the semiconductor relay CH 1 (downstream connection absent) (step S 606 ).

The ECU 3 sequentially switches on the semiconductor relays CH 2 -CH 4 in a similar manner, and determines whether or not a load 20 is connected to the semiconductor relay CH 2 -CH 4 . After determining whether or not a load 20 is connected to each of the semiconductor relays CH 2 -CH 4 provided in the ECU 3 , the ECU 3 proceeds to step S 607 .

In step S 607 , if the number of semiconductor relays CH 1 -CH 4 to which a load 20 is connected is one (step S 607 : Y), the ECU 3 sets the ECU number to No 1 (bit 1 =0, bit 2 =0) (step S 608 ), and then proceeds to step S 7 in FIG. 3 . Furthermore, if the number of semiconductor relays CH 1 -CH 4 to which a load 20 is connected is two (step S 609 : Y), the ECU 3 sets the ECU number to No 2 (bit 1 =0, bit 2 =1) (step S 610 ), and then proceeds to step S 7 in FIG. 3 .

Furthermore, if the number of semiconductor relays CH 1 -CH 4 to which a load 20 is connected is three (step S 611 : Y), the ECU 3 sets the ECU number to No 3 (bit 1 =1, bit 2 =0) (step S 612 ), and then proceeds to step S 7 in FIG. 3 . Moreover, if the number of semiconductor relays CH 1 -CH 4 to which a load 20 is connected is four (step S 611 : N), the ECU 3 sets the ECU number to No 4 (bit 1 =1, bit 2 =1) (step S 613 ), and then proceeds to step S 7 in FIG. 3 .

Next, in step S 7 in FIG. 3 , the ECU 3 acts as a transmission unit, and attaches the initial ID to an ECU number signal and transmits the same to the gateway 2 . As shown in Table 5 below, the ECU number signal is a signal where bit 7 -bit 2 are blank, and the ECU number is written in bit 1 , bit 0 .

If the ECU number signal is not received from all the ECUs 3 connected by the communication line L 2 within a predetermined period of time T 3 from transmission of the first request signal (step S 23 : N), the gateway 2 stops the processing (step S 24 ), and ends the processing.

When the ECU number signal is received from all the ECUs 3 connected by the communication line L 2 within the predetermined period of time T 3 from transmission of the first request signal (step S 23 : Y), the gateway 2 determines whether or not an overlapping ECU number is non-existent (step S 25 ). If an overlapping ECU number is non-existent (step S 25 : Y), the gateway 2 broadcasts a network information signal (step S 26 ).

If the network information signal is received from the gateway 2 within a predetermined period of time T 4 after transmitting the ECU number signal (step S 8 : Y), the ECU 3 performs an ID rewrite process (step S 9 ). In the ID rewrite process, the ECU 3 rewrites the initial ID to a dedicated ID including the ECU number set by itself and the received network information. Then, the ECU 3 transmits, to the gateway 2 , a completion signal indicating that setting of an ID using the dedicated ID is completed (step S 10 ), and ends the processing. As shown in Table 6 below, the completion signal is a signal where bit 7 is 1 and bit 6 -bit 0 are blank, to which the dedicated ID is attached.

If the completion signal is not received within a predetermined period of time T 5 from transmission of the network information signal (step S 27 : N), the gateway 2 stops the processing (step S 24 ), and ends the processing. On the other hand, if the completion signal is received (step S 27 : Y), the gateway 2 immediately ends the processing.

If the number of connected loads 20 overlaps between a plurality of ECUs 3 connected to the gateway 2 , this results in an overlapping ECU number. In the case where there is an overlapping ECU number (step S 25 : N), if a second request signal is yet to be transmitted (step S 28 : Y), the gateway 2 acts as a second setting unit, and broadcasts the second request signal (step S 29 ). The second request signal is a signal requesting for setting of an ID according to the number of parallel connections of loads 20 (second information) connected to the ECU 3 . If the second request signal is received within a predetermined period of time T 4 from transmission of the ECU number signal (step S 11 : Y), the ECU 3 acts as a fifth setting unit, and performs second setting processing (step S 12 ).

The second setting processing is processing for setting an ID according to the number of parallel connections of loads 20 connected to the ECU 3 . The number of parallel connections is the number of groups of the semiconductor relays CH 1 -CH 4 which are connected in parallel with one another. That is, the semiconductor relays CH 1 -CH 4 in the same group are connected in parallel with one another, but the semiconductor relays CH 1 -CH 4 in different groups are not connected in parallel with one another.

In the second setting processing, a detected current from each semiconductor relay CH 1 -CH 4 when all the semiconductor relays CH 1 -CH 4 are on is captured. For example, the detected current is assumed to be 10 A for the semiconductor relay CH 1 , 10 A for the semiconductor relay CH 2 , 10 A for the semiconductor relay CH 3 , and 5 A for the semiconductor relay CH 4 .

Next, the semiconductor relay CH 1 , which is one of all the semiconductor relays CH 1 -CH 4 , is switched off, and the detected current is captured at this time from each semiconductor relay CH 1 -CH 4 . At this time, the detected current is assumed to be OA for the semiconductor relay CH 1 , 15 A for the semiconductor relay CH 2 , 15 A for the semiconductor relay CH 3 , and 5 A for the semiconductor relay CH 4 . It can thus be seen that semiconductor relays CH 2 , CH 3 , where the detected currents were increased when the semiconductor relay CH 1 was switched from on to off, are connected in parallel with the semiconductor relay CH 1 . On the other hand, it can be seen that the semiconductor relay CH 4 , where the detected current is unchanged, is not connected in parallel with the semiconductor relay CH 1 . When the above is repeated for the semiconductor relays CH 2 -CH 4 , the connection relationship among the semiconductor relays C 1 -C 4 can be grasped.

Next, a specific operation of the ECU 3 in the second setting processing will be described with reference to the flowcharts in FIGS. 6 and 7 . The ECU 3 switches on all the semiconductor relays CH 1 -CH 4 , and captures detected currents from all the semiconductor relays CH 1 -CH 4 (step S 1201 ). Next, the ECU 3 switches off the semiconductor relay CH 1 , and captures the detected currents from all the semiconductor relays CH 1 -CH 4 (step S 1202 ).

Next, if the detected current of the semiconductor relay CH 1 is not zero (step S 1203 : N), the ECU 3 stops control of the semiconductor relay CH 1 , assuming that the semiconductor relay CH 1 cannot be controlled in a normal manner (step S 1204 ), and proceeds to step S 1219 shown in FIG. 7 . If the detected current of the semiconductor relay CH 1 is zero (step S 1203 : Y), and if the detected currents of the semiconductor relays CH 2 -CH 4 are increased (steps S 1204 -S 1206 : Y), the ECU 3 determines that the semiconductor relays CH 2 -CH 4 are connected in parallel with the semiconductor relay CH 1 (step S 1207 ).

Furthermore, if the detected currents of the semiconductor relays CH 2 , CH 3 are increased but the detected current of the semiconductor relay CH 4 remains unchanged (steps S 1204 and S 1205 : Y, and step S 1206 : N), the ECU 3 determines that the semiconductor relays CH 2 , CH 3 are connected in parallel with the semiconductor relay CH 1 , and that the semiconductor relay CH 4 is not connected in parallel with the semiconductor relay CH 1 (step S 1207 ).

Furthermore, if the detected currents of the semiconductor relays CH 2 , CH 4 are increased but the detected current of the semiconductor relay CH 3 remains unchanged (step S 1204 : Y, step S 1205 : N, step S 1209 : Y), the ECU 3 determines that the semiconductor relays CH 2 , CH 4 are connected in parallel with the semiconductor relay CH 1 , and that the semiconductor relay CH 3 is not connected in parallel with the semiconductor relay CH 1 (step S 1210 ).

Furthermore, if the detected current of the semiconductor relay CH 2 is increased but the detected currents of the semiconductor relays CH 3 , CH 4 remain unchanged (step S 1204 : Y, step S 1205 : N, step S 1209 : N), the ECU 3 determines that the semiconductor relay CH 2 is connected in parallel with the semiconductor relay CH 1 , and that the semiconductor relays CH 3 , CH 4 are not connected in parallel with the semiconductor relay CH 1 (step S 1211 ).

Furthermore, if the detected currents of the semiconductor relays CH 3 , CH 4 are increased but the detected current of the semiconductor relay CH 2 remains unchanged (step S 1204 : N, step S 1212 : Y, step S 1213 : Y), the ECU 3 determines that the semiconductor relays CH 3 , CH 4 are connected in parallel with the semiconductor relay CH 1 , and that the semiconductor relay CH 2 is not connected in parallel with the semiconductor relay CH 1 (step S 1214 ).

Furthermore, if the detected current of the semiconductor relay CH 3 is increased but the detected currents of the semiconductor relays CH 2 , CH 4 remain unchanged (step S 1204 : N, step S 1212 : Y, step S 1213 : N), the ECU 3 determines that the semiconductor relay CH 3 is connected in parallel with the semiconductor relay CH 1 , and that the semiconductor relays CH 2 , CH 4 are not connected in parallel with the semiconductor relay CH 1 (step S 1215 ).

Furthermore, if the detected current of the semiconductor relay CH 4 is increased but the detected currents of the semiconductor relays CH 2 , CH 3 remain unchanged (step S 1204 : N, step S 1212 : N, step S 1216 : Y), the ECU 3 determines that the semiconductor relay CH 4 is connected in parallel with the semiconductor relay CH 1 , and that the semiconductor relays CH 2 , CH 3 are not connected in parallel with the semiconductor relay CH 1 (step S 1217 ).

Furthermore, if the detected current of each semiconductor relay CH 2 -CH 4 remains unchanged without being increased (step S 1204 : N, step S 1212 : N, step S 1216 : N), the ECU 3 determines that there is no semiconductor relay which is connected in parallel with the semiconductor relay CH 1 (step S 1218 ).

In a similar manner, which semiconductor relay is connected in parallel is determined for the semiconductor relays CH 2 -CH 4 (steps S 1219 -S 1224 ). Then, the ECU 3 determines the number of parallel connections based on the determination result (step S 1225 ).

If, according to the determination result, the number of parallel connections is one (step S 1226 : Y), the ECU 3 sets the ECU number to No 1 (bit 1 =0, bit 2 =0) (step S 1227 ), and returns to step S 7 in FIG. 3 . Furthermore, if the number of parallel connections is two (step S 1228 : Y), the ECU number is set to No 2 (bit 1 =0, bit 2 =1) (step S 1229 ), and step S 7 in FIG. 3 is performed. Furthermore, if the number of parallel connections is three (step S 1230 : Y), the ECU number is set to No 3 (bit 1 =1, bit 2 =0) (step S 1231 ), and step S 7 in FIG. 3 is performed. If the number of parallel connections is four (step S 1230 : N), the ECU number is set to No 4 (bit 1 =1, bit 2 =1) (step S 1232 ), and step S 7 in FIG. 3 is performed.

As shown in FIG. 3 , if there is an overlapping ECU number even when the ID is determined based on the number of parallel connections described above (step S 25 : N, and step S 28 : Y), the gateway 2 acts as a third setting unit, and broadcasts a third request signal requesting for setting of an ID according to a sum of drive currents of loads 20 (third information) connected to the ECU 3 (step S 31 ). If the third request signal is received within a predetermined period of time T 4 from transmission of the ECU number (step S 13 : Y), the ECU 3 performs third setting processing for setting an ID according to the sum of drive currents of loads 20 connected to the ECU 3 (step S 14 ).

Next, the third setting processing mentioned above will be described with reference to FIG. 8 . In the third setting processing, the ECU 3 switches on all the semiconductor relays CH 1 -CH 4 , and captures detected currents from all the semiconductor relays CH 1 -CH 4 (step S 141 ). The detected current is a drive current that flows through the load 20 connected to each semiconductor relay CH 1 -CH 4 . Then, if the sum of the detected currents is equal to or lower than a first determination current (step S 142 : Y), the ECU 3 sets the ECU number to No 1 (bit 1 =0, bit 2 =0) (step S 143 ), and returns to step S 7 in FIG. 3 .

Furthermore, if the sum of the detected currents is higher than the first determination current and equal to or lower than a second determination current (step S 142 : N, and step S 144 : Y), the ECU 3 sets the ECU number to No 2 (bit 1 =0, bit 2 =1) (step S 145 ), and proceeds to step S 7 in FIG. 3 . Furthermore, if the sum of the detected currents is higher than the second determination current and equal to or lower than a third determination current (step S 146 : Y), the ECU 3 sets the ECU number to No 3 (bit 1 =1, bit 2 =0) (step S 147 ), and proceeds to step S 7 in FIG. 3 . Moreover, if the sum of the detected currents is higher than the third determination current (step S 146 : N), the ECU 3 sets the ECU number to No 4 (bit 1 =1, bit 2 =1) (step S 148 ), and proceeds to step S 7 in FIG. 3 .

According to the embodiment described above, the gateway 2 causes each ECU to set an ID according to the number of loads 20 connected to the ECU 3 . Moreover, in the case where the IDs of a plurality of ECUs 3 set according to the number of loads 20 are overlapped, the gateway 2 causes the ECUs 3 to set an ID according to the number of parallel connections of loads 20 , instead of the number of loads 20 . The IDs of the ECUs 3 may thus be prevented from being overlapped with each other. Moreover, ID setting of the ECU 3 may be easily performed.

Moreover, according to the embodiment described above, in the case where the IDs of a plurality of ECUs 3 set based on the number of parallel connections are overlapped, the gateway 2 causes the ECUs 3 to set an ID according to the sum of drive currents that flow through the loads 20 connected to the ECU 3 , instead of the number of loads 20 and the number of parallel connections. Overlapping of IDs of the ECUs 3 is thus further prevented. That is, according to the present embodiment, IDs can be set in the ECUs 3 connected to the gateway 2 if there is no overlap with respect to at least one of the number of connected loads 20 , the number of parallel connections, and the sum of drive currents.

Moreover, according to the embodiment described above, IDs of the ECUs 3 connected to a plurality of gateways 2 disposed in respective areas may be set at the same time, and thus, ID setting time may be reduced.

Moreover, according to the embodiment described above, the ECU 3 sets an ID by determining the number of loads 20 , the number of parallel connections, or the sum of drive currents based on the detected currents of the semiconductor relays CH 1 -CH 4 . Accordingly, continuity check may also be performed at the time of ID setting.

Moreover, according to the embodiment described above, in the ID setting processing, the status of a load 20 connected to the ECU 3 may be grasped by determining the number of loads 20 , the number of parallel connections, or the sum of drive currents. Accordingly, when a new ECU 3 is connected to the in-vehicle network 1 , a load control program suitable for load control may be selected and written.

Additionally, according to the embodiment described above, the number of loads 20 is used as the first information, but this is not restrictive. The first information may be any one of the number of loads 20 , the number of parallel connections, and the sum of drive currents, and it may be the number of parallel connections or the sum of drive currents. Furthermore, the second information may be any one of the number of loads 20 , the number of parallel connections, and the sum of drive currents which is not used as the first information, as long as the second information is different from the first information. Moreover, the third information may be any one of the number of loads 20 , the number of parallel connections, and the sum of drive currents which are not used as the first information and the second information, as long as the third information is different from the first information and the second information.

Furthermore, according to the embodiment described above, one of the number of loads 20 , the number of parallel connections, and the sum of drive currents is used as the first information, but this is not restrictive. The first information may be information other than those mentioned above, and for example, the first information may be a lock current of a motor, as in a conventional case.

Moreover, according to the embodiment described above, in the case where IDs according to the first information and the second information are overlapped, the gateway 2 causes an ID according to the third information to be set, but this is not restrictive. In the case where IDs according to the first information and the second information are overlapped, the gateway 2 may immediately stop the processing, assuming that IDs cannot be set, without performing ID setting according to the third information.

Additionally, the present invention is not limited to the embodiment described above. That is, various modifications may be made within the gist of the present invention.

2 gateway (setting device)

3 ECU (computer)

20 load

21 A CPU (first setting unit, second setting unit, third setting unit)

32 A CPU (fourth setting unit, fifth setting unit, transmission unit)