Liquid crystal display device

This application claims priority from Japanese application JP 2017-057034, filed Mar. 23, 2017. This Japanese application is incorporated herein by reference.

The present invention relates to a liquid crystal display device.

A technology, in which two display panels overlap each other and an image is displayed on each display panel based on an input video signal, is conventionally proposed to improve contrast of a liquid crystal display device (for example, see WO2007/040127). Specifically, for example, a color image is displayed on a front-side (observer-side) display panel in two display panels disposed back and forth, and a black-and-white image is displayed on a rear-side (backlight-side) display panel, thereby improving contrast. In the liquid crystal display device, to decrease the number of source drivers for a purpose of cost reduction, one pixel of a black-and-white image display panel overlaps with respect to three pixels (a red pixel, a green pixel, a blue pixel) of a color image display panel.

For example in the case that one pixel of the black-and-white image display panel is defective, three pixels (a red pixel, a green pixel, a blue pixel) of the color image display panel, which overlap with said one pixel, can become distorted (ex. dark spot). The more number of pixels of the color image display panel that overlap with said one pixel of black-and-white image display panel, the worse the distortion of said pixels of the color image display panel. For example in the case that twenty-seven pixels of the color image display panel overlaps with one defective pixel of the black-and-white image display panel, the twenty-seven pixels of the color image display panel can become distorted.

The present disclosure is made in consideration of such a situation, and an object of the present disclosure is to improve an image degradation due to defective pixels in a liquid crystal display device in which the plurality of display panels overlap each other.

To solve the above problem, a liquid crystal display device according to a first disclosure comprises: a first display panel that includes a plurality of first source lines extending in a first direction and a plurality of first gate lines extending in a second direction different from the first direction; and a second display panel opposing the first display panel that includes a plurality of second source lines extending in the first direction and a plurality of second gate lines extending in the second direction. Each of the first display panel and the second display panel includes a plurality of thin film transistors, and a plurality of pixel electrodes of which each is electrically connected to a corresponding one of the plurality of thin film transistors. In the second display panel, at least two thin film transistors of the plurality of thin film transistors are electrically connected to a same second source line among the plurality of second source lines and a same second gate line among the plurality of second gate lines.

In the liquid crystal display device according to the first disclosure, the thin film transistors of the first display panel may include first thin film transistors, the pixel electrodes of the first display panel may include first pixel electrodes that are electrically connected to a corresponding one of the first thin film transistors, each of a plurality of first pixels may be defined by a driving area of a corresponding one of the plurality of first pixel electrodes in the first display panel, the thin film transistors of the second display panel may include second thin film transistors and third thin film transistors, the pixel electrodes of the second display panel may include second pixel electrodes that are electrically connected to a corresponding one of the second thin film transistors and third pixel electrodes that are electrically connected to a corresponding one of the third thin film transistors, each of a plurality of second pixels may be defined by a driving area of a corresponding one of the plurality of second pixel electrodes in the second display panel, each of a plurality of third pixels may be defined by a driving area of a corresponding one of the plurality of third pixel electrodes in the second display panel, the plurality of first pixels may include a plurality of first color pixels corresponding to a first color, a plurality of second color pixels corresponding to a second color different from the first color, and a plurality of third color pixels corresponding to a third color different from the first color and the second color, a first pixel group that includes one first color pixel of the plurality of first color pixels, one second color pixel of the plurality of second color pixels and one third color pixel of the plurality of third color pixels may overlap with a second pixel group that includes one second pixel of the plurality of second pixels and one third pixel of the plurality of third pixels in planar view, and one second thin film transistor of the plurality of second thin film transistors and one third thin film transistor of the plurality of the third thin film transistors may be electrically connected to a same second source line of the plurality of second source lines and a same second gate line of the plurality of second gate lines.

In the liquid crystal display device according to the first disclosure, each of the plurality of first color pixels, each of the plurality of second color pixels and each of the plurality of third color pixels may be arranged in the second direction, and each of the plurality of second pixels and each of the plurality of third pixels may be arranged in the first direction or the second direction.

In the liquid crystal display device according to the first disclosure, the thin film transistors of the second display panel may further include a plurality of fourth thin film transistors, a plurality of fifth thin film transistors, a plurality of fourth pixel electrodes of which each is electrically connected to a corresponding one of the fourth thin film transistors, and a plurality of fifth pixel electrodes of which each is electrically connected to a corresponding one of the fifth thin film transistors. Each of a plurality of fourth pixels may be defined by a driving area of a corresponding one of the plurality of fourth pixel electrodes in the second display panel. Each of a plurality of fifth pixels may be defined by a driving area of a corresponding one of the plurality of fifth pixel electrodes in the second display panel. The second pixel group may include one of the plurality of fourth pixels and one of the plurality of fifth pixels in addition to one of the plurality of second pixels and one of the plurality of third pixels, and one second pixel electrode of the plurality of second pixel electrodes, one third pixel electrode of the plurality of third pixel electrodes, one fourth pixel electrode of the plurality of fourth pixel electrodes and one fifth pixel electrode of the plurality of fifth pixel electrodes may be electrically connected to a same second gate line and a same second source line.

In the liquid crystal display device according to the first disclosure, the thin film transistors of the first display panel may include a plurality of first thin film transistors, the pixel electrodes of the first display panel may include first pixel electrodes that are electrically connected to a corresponding one of the first thin film transistors. Each of a plurality of first pixels may be defined by a driving area of a corresponding one of the plurality of first pixel electrodes in the first display panel. The thin film transistors of the second display panel may include a plurality of second thin film transistors and a plurality of third thin film transistors. Each of the plurality of second pixel electrodes may be electrically connected to a corresponding one of the plurality of second thin film transistors and a corresponding one of the plurality of third thin film transistors. Each of a plurality of second pixels may be defined by a driving area of a corresponding one of plurality of second pixel electrodes in the second display panel. One second thin film transistor of the plurality of second thin film transistors and one third thin film transistor of the plurality of third thin film transistors may be electrically connected to a same second source line and a same second gate line.

In the liquid crystal display device according to the first disclosure, the plurality of first pixels may include a plurality of first color pixels corresponding to a first color, a plurality of second color pixels corresponding to a second color different from the first color, and a plurality of third color pixels corresponding to a third color different from the first color and the second color, and a first pixel group that includes one first color pixel of the plurality of first color pixels, one second color pixel of the plurality of second color pixels and one third color pixel of the plurality of third color pixels may overlap with the second pixel in planar view.

To solve the above problem, a liquid crystal display device according to a second disclosure comprises: a first display panel; and a second display panel opposing to the first display panel. The first display panel includes a plurality of first source lines extending in a first direction, a plurality of first gate lines extending in a second direction different from the first direction, a plurality of first thin film transistors of which each is electrically connected to a corresponding one of the plurality of first source lines and a corresponding one of the plurality of first gate lines, and a plurality of first pixel electrodes of which each is electrically connected to a corresponding one of the plurality of first thin film transistors. Each of a plurality of first pixels are defined by a driving area of a corresponding one of the plurality of first pixel electrodes in the first display panel. The second display panel includes a plurality of second source lines extending in the first direction, a plurality of second gate lines extending in the second direction, a plurality of second thin film transistors, and a plurality of second pixel electrodes of which each is electrically connected to a corresponding one of the second thin film transistors. Each of a plurality of second pixels are defined by a driving area of a corresponding one of the plurality of second pixel electrodes in the second display panel. Each of the plurality of the second thin film transistors includes a first conductive electrode electrically connected to a corresponding one of the plurality of source lines, a second conductive electrode including a first branch electrode and a second branch electrode, and a control electrode electrically connected to a corresponding one of the plurality of gate lines, and the first branch electrode and the second branch electrode are electrically connected to a same second pixel electrode.

FIG. 1 is a perspective view illustrating a schematic configuration of a liquid crystal display device according to a first exemplary embodiment;

FIG. 2 is a plan view illustrating the schematic configuration of the liquid crystal display device according to the first exemplary embodiment;

FIG. 3 is a plan view illustrating a schematic configuration of a first display panel according to the first exemplary embodiment;

FIG. 4 is a plan view illustrating a schematic configuration of a second display panel according to the first exemplary embodiment;

FIG. 5 is a sectional view taken along line A-A′ in FIGS. 3 and 4 ;

FIGS. 6A and 6B are plan views of the first exemplary embodiment, illustrating a relationship between a first pixel group of the first display panel and a second pixel group of the second display panel, the first pixel group and the second pixel group overlapping to each other;

FIG. 7 is a sectional view taken along line B-B′ in FIGS. 6A and 6B ;

FIG. 8 is a plan view illustrating the schematic configuration of the liquid crystal display device according to a second exemplary embodiment;

FIGS. 9A and 9B are plan views of the second exemplary embodiment, illustrating a relationship between a first pixel group of the first display panel and a second pixel group of the second display panel, the first pixel group and the second pixel group overlapping to each other;

FIG. 10 is a plan view illustrating a first pixel group of the first display panel according to a third exemplary embodiment;

FIG. 11 is a plan view illustrating a second pixel group of the second display panel according to the third exemplary embodiment;

FIG. 12 is a plan view illustrating arrangement of the second pixel group of the second display panel according to the third exemplary embodiment;

FIG. 13 is a plan view illustrating a variation of the second display panel according to the third exemplary embodiment;

FIGS. 14A and 14B are plan views of a forth exemplary embodiment, illustrating a relationship between a first pixel group of the first display panel and a second pixel group of the second display panel;

FIGS. 15A and 15B are plan views illustrating a variation of the second pixel group of the second display panel according to the forth exemplary embodiment;

FIGS. 16A and 16B are plan views illustrating a variation of the second pixel group of the second display panel according to the forth exemplary embodiment;

FIG. 17 is a plan view illustrating a variation of the second pixel group of the second display panel according to the forth exemplary embodiment; and

FIG. 18 is a plan view illustrating a variation of the second pixel group of the second display panel according to the forth exemplary embodiment.

Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings. A liquid crystal display device of each exemplary embodiment described below includes a plurality of display panels that display images, a plurality of driving circuits (a plurality of source drivers and a plurality of gate drivers) that drive the display panels, a plurality of timing controllers that control the driving circuits, an image processor that performs image processing on an input video signal input from an outside and outputs image data to each of the timing controllers, and a backlight that irradiates the plurality of display panels with light from a rear surface side. There is no limitation to the number of display panels, but it is only necessary to provide at least two display panels. When viewed from the observer side, the plurality of display panels are disposed while overlapping each other in a front-back direction. An image is displayed on each of the display panels. Liquid crystal display device LCD including two display panels will be described below by way of example.

First Exemplary Embodiment

FIG. 1 is a perspective view illustrating a schematic configuration of a liquid crystal display device LCD of a first exemplary embodiment. As illustrated in FIG. 1 , the liquid crystal display device LCD includes a first display panel LCP 1 which is disposed at a position (front side) closer to an observer, a second display panel LCP 2 which is disposed at a position (rear side) farther away from the observer than the first display panel LCP 1 is, an adhesive layer SEFIL in which the first display panel LCP 1 and the second display panel LCP 2 adhere to each other, a backlight BL disposed on the rear surface side of the second display panel LCP 2 , and a front chassis FS that covers the first display panel LCP 1 and the second display panel LCP 2 from the display surface side. The second display panel LCP 2 may be disposed on the front side while the first display panel LCP 1 may be disposed on the rear side.

FIG. 2 is a view illustrating the schematic configuration of the liquid crystal display device LCD of the first exemplary embodiment. As illustrated in FIG. 2 , the first display panel LCP 1 includes a first source driver SD 1 and a first gate driver GD 1 , and the second display panel LCP 2 includes a second source driver SD 2 and a second gate driver GD 2 . In addition, the liquid crystal display device LCD includes a first timing controller TCON 1 that controls the first source driver SD 1 and the first gate driver GD 1 , a second timing controller TCON 2 that controls the second source driver SD 2 and the second gate driver GD 2 , and an image processor IPU that outputs image data to the first timing controller TCON 1 and the second timing controller TCON 2 . For example, the first display panel LCP 1 displays a color image in a first image display region DISP 1 according to the input video signal, and the second display panel LCP 2 displays a black-and-white (monochrome) image in a second image display region DISP 2 according to the input video signal. The image processor IPU receives input video signal Data transmitted from an external system (not illustrated), performs known image processing on input video signal Data, outputs first image data DAT 1 to the first timing controller TCON 1 , and outputs second image data DAT 2 to the second timing controller TCON 2 . The image processor IPU also outputs a control signal CS 1 , CS 2 (see, FIGS. 3 and 4 ) such as a synchronizing signal to the first timing controller TCON 1 and the second timing controller TCON 2 . For example, the first image data DAT 1 is image data for displaying the color image, and the second image data DAT 2 is image data for displaying the black-and-white image. FIG. 3 is a plan view illustrating a schematic configuration of the first display panel LCP 1 according to the first exemplary embodiment, and FIG. 4 is a plan view illustrating a schematic configuration of the second display panel LCP 2 according to the first exemplary embodiment. FIG. 5 is a sectional view taken along line A-A′ in FIGS. 3 and 4 .

The schematic configuration of first display panel LCP 1 will be described with reference to FIGS. 3 and 5 . As illustrated in FIG. 5 , the first display panel LCP 1 includes a thin film transistor substrate TFTB 1 disposed on the side of the backlight BL, an opposing substrate CF 1 which is disposed on the observer side while being opposite to the thin film transistor substrate TFTB 1 , and a liquid crystal layer LC 1 disposed between the thin film transistor substrate TFTB 1 and the opposing substrate CF 1 . A polarizing plate POL 2 is disposed on the side of the first display panel LCP 1 near the backlight BL, and a polarizing plate POL 1 is disposed on the observer side of the first display panel LCP 1 .

In the thin film transistor substrate TFTB 1 , as illustrated in FIG. 3 , a plurality of first source lines SL 1 extending in a first direction (for example, a column direction), and a plurality of first gate lines GL 1 extending in a second direction (for example, a row direction) different from the first direction are formed, and a plurality of first thin film transistors TFT 1 are formed close to an intersection between a corresponding one of the plurality of the first source lines SL 1 and a corresponding one of the plurality of the first gate lines GL 1 . In the first display panel LCP 1 , a driving area (dot image area) of a first pixel electrode PIT 1 electrically connected to the thin film transistor TFT 1 is defined as one first pixel PIX 1 , and a plurality of pixels PIX 1 are disposed in a matrix form (the row direction and the column direction). The plurality of the first source lines SL 1 are disposed at equal intervals in the row direction, and the plurality of the first gate lines GL 1 are disposed at equal intervals in the column direction. In the thin film transistor substrate TFTB 1 , each first pixel electrode PIT 1 is formed in a corresponding one of the pixels PIX 1 , and one common electrode (not illustrated in FIGS.) common to the plurality of the pixels PIX 1 is formed. The thin film transistor TFT 1 includes a drain electrode electrically connected to the source line SL 1 , a source electrode electrically connected to the first pixel electrode PIT 1 , and a gate electrode electrically connected to the gate line GL 1 .

As illustrated in FIG. 5 , a plurality of color filter layers FIL (colored portions) are formed on the opposing substrate CF 1 according to each first pixel PIX 1 . Each color filter layer FIL is surrounded by black matrix BM 1 blocking light transmission. For example, each color filter layer FIL is formed into a rectangular shape. The plurality of the color filter layers FIL include red color filter layers (red portion) made of a red (R color) material to transmit red light, green color filter layers (green portion) made of a green (G color) material to transmit green light, and blue color filter layers (blue portion) made of a blue (B color) material to transmit blue light. The red color filter layers, green color filter layers, and blue color filter layers are repeatedly arrayed in the row direction in this order, identical-color filter layers are arrayed in the column direction, and the black matrix BM is formed at a boundary between color filter layers adjacent to each other in the row direction and the column direction. In accordance with the color filter layers, as illustrated in FIG. 3 , the plurality of the pixels PIX 1 include red pixels PIXR corresponding to the red color filter layers, green pixels PIXG corresponding to the green color filter layers, and blue pixels PIXB corresponding to the blue color filter layers. In the first display panel LCP 1 , the red pixels PIXR, the green pixels PIXG, and the blue pixels PIXB are repeatedly arrayed in the row direction in this order, and pixels PIX 1 having the identical color are arrayed in the column direction.

As illustrated in FIG. 3 , based on the first image data DAT 1 and first control signals CS 1 (such as a clock signal, a vertical synchronizing signal, and a horizontal synchronizing signal), which are output from the image processor IPU, the first timing controller TCON 1 generates various timing signals (data start pulse DSP 1 , data clock DCK 1 , gate start pulse GSP 1 , and gate clock GCK 1 ) to control first image data DA 1 and drive of a first source driver SD 1 and a first gate driver GD 1 (see FIG. 3 ). The first timing controller TCON 1 outputs the first image data DA 1 , a data start pulse DSP 1 , and a data clock DCK 1 to the first source driver SD 1 , and outputs a gate start pulse GSP 1 and a gate clock GCK 1 to the first gate driver GD 1 .

The first source driver SD 1 outputs a data signal (data voltage, i.e. gradation voltage) corresponding to the first image data DA 1 to the source line SL 1 based on the data start pulse DSP 1 and the data clock DCK 1 . The first gate driver GD 1 outputs a gate signal (gate voltage) to the first gate lines GL 1 based on the gate start pulse GSP 1 and the gate clock GCK 1 .

The first source driver SD 1 supplies the data voltage to the first source lines SL 1 , and the first gate driver GD 1 supplies the gate voltage to the first gate lines GL 1 . Common voltage Vcom is supplied from a common driver (not illustrated) to the common electrode. When the gate voltage (gate-on voltage) is supplied to a gate line GL 1 , a thin film transistor TFT 1 connected to the gate line GL 1 is turned on, and the data voltage is supplied to a first pixel electrode PIT 1 through a source line SL 1 connected to said thin film transistor TFT 1 . An electric field is generated by a difference between the data voltage supplied to the first pixel electrode PIT 1 and the common voltage Vcom supplied to the common electrode. A liquid crystal is driven by the electric field, and transmittance of the light emitted from the backlight BL is controlled, thereby displaying an image. In the first display panel LCP 1 , a color image is displayed by the supply of a desired data voltage to the source lines SL 1 connected to the first pixel electrodes PIT 1 included in either red pixel PIXR, green pixel PIXG, or blue pixel PIXB.

The schematic configuration of the second display panel LCP 2 will be described with reference to FIGS. 4 and 5 . As illustrated in FIG. 5 , the second display panel LCP 2 includes a thin film transistor substrate TFTB 2 disposed on the backlight side, an opposing substrate CF 2 , which is disposed on the observer side while being opposite to the thin film transistor substrate TFTB 2 , and a liquid crystal layer LC 2 disposed between the thin film transistor substrate TFTB 2 and the opposing substrate CF 2 . A polarizing plate POL 4 is disposed on the backlight side of the second display panel LCP 2 , and a polarizing plate POL 3 is disposed on the observer side of the second display panel LCP 2 . An adhesive layer SEFIL is disposed between the polarizing plate POL 2 of the first display panel LCP 1 and the polarizing plate POL 3 of the second display panel LCP 2 .

In the thin film transistor substrate TFTB 2 , as illustrated in FIG. 4 , a plurality of second source lines SL 2 extending in the column direction, and a plurality of second gate lines GL 2 extending in the row direction are formed, and a plurality of thin film transistors TFT 2 is formed close to the intersection between a corresponding one of the plurality of the second source lines SL 2 and a corresponding one of the plurality of the second gate lines GL 2 . In the second display panel LCP 2 , a driving area (dot image area) of a pixel electrode PIT 2 electrically connected to the thin film transistor TFT 2 is defined as one pixel PIX 2 . In this exemplary embodiment, two pixels PIX 2 (PIX 2 a, PIX 2 b ) adjacent in the row direction are provided in a region surrounded by two second source lines SL 2 adjacent to each other and two second gate lines GL 2 adjacent to each other in planar view. A plurality of pixels PIX 2 are disposed in a matrix form (the row direction and the column direction). The plurality of the second source lines SL 2 are disposed at equal intervals in the row direction, and the plurality of the second gate lines GL 2 are disposed at equal intervals in the column direction. In the thin film transistor substrate TFTB 2 , each pixel electrode PIT 2 is formed in a corresponding one of the pixels PIX 2 , and one common electrode (not illustrated in FIGS.) common to the plurality of the pixels PIX 2 is formed. Two thin film transistors TFT 2 adjacent in the row direction through the source line SL 2 are connected to a same gate line GL 2 and a same source line SL 2 . In other words, two thin film transistors TFT 2 disposed on either side of one source line SL 2 are connected to that source line SL 2 and to the same gate line GL 2 . The thin film transistor TFT 2 includes a drain electrode electrically connected to the source line SL 2 , a source electrode electrically connected to the pixel electrode PIT 2 , and a gate electrode electrically connected to the gate line GL 2 . Drain electrodes of the two thin film transistors TFT 2 adjacent in the row direction through the source line SL 2 are connected to each other and to the source line SL 2 .

As illustrated in FIG. 5 , in opposing substrate CF 2 , black matrix BM 2 is formed at a position corresponding to a boundary of each pixel PIX 2 . The color filter layer (colored portion) is not formed in a region surrounded by black matrix BM 2 . For example, overcoat film OC is formed in the region.

As shown in FIG. 4 , based on second image data DAT 2 and second control signals CS 2 (such as a clock signal, a vertical synchronizing signal, and a horizontal synchronizing signal), which are output from the image processor IPU, the second timing controller TCON 2 generates various timing signals (data start pulse DSP 2 , data clock DCK 2 , gate start pulse GSP 2 , and gate clock GCK 2 ) to control second image data DA 2 and drive of the second source driver SD 2 and the second gate driver GD 2 . The second timing controller TCON 2 outputs second image data DA 2 , a data start pulse DSP 2 , and a data clock DCK 2 to the second source driver SD 2 , and outputs a gate start pulse GSP 2 and a gate clock GCK 2 to the second gate driver GD 2 .

The second source driver SD 2 outputs the data voltage corresponding to second image data DA 2 to the second source lines SL 2 based on the data start pulse DSP 2 and the data clock DCK 2 . The second gate driver GD 2 outputs the gate voltage to the second gate lines GL 2 based on the gate start pulse GSP 2 and the gate clock GCK 2 .

The second source driver SD 2 supplies the data voltage to the second source lines SL 2 , and the second gate driver GD 2 supplies the gate voltage to the second gate lines GL 2 . Common voltage Vcom is supplied from a common driver (not illustrated) to the common electrode. When the gate voltage (gate-on voltage) is supplied to the gate line GL 2 , the thin film transistor TFT 2 connected to the gate line GL 2 is turned on, and the data voltage is supplied to the pixel electrode PIT 2 through the source line SL 2 connected to said thin film transistor TFT 2 . An electric field is generated by a difference between the data voltage supplied to the pixel electrode PIT 2 and the common voltage Vcom supplied to the common electrode. A liquid crystal is driven by the electric field, and transmittance of the light emitted from the backlight BL is controlled, thereby displaying an image. In the second display panel LCP 2 , a monochrome image is displayed. In the second display panel LCP 2 , data voltage is simultaneously supplied with two pixel electrodes PIT 2 connected to one gate line GL 2 and one source line SL 2 .

In the liquid crystal display device LCD, the number of pixels PIX 2 per area of second display panel LCP 2 is smaller than the number of pixels PIX 1 per area of first display panel LCP 1 . FIGS. 6A and 6B are plan views illustrating a relationship between a first pixel group PG 1 of the first display panel LCP 1 and a second pixel group PG 2 of the second display panel LCP 2 , with the first pixel group PG 1 and the second pixel group PG 2 overlapping to each other. Each first pixel PIX 1 is provided with a corresponding first pixel electrode PIT 1 , and each pixel PIX 2 is provided with a corresponding second pixel electrode PIT 2 .

As shown in FIG. 6 , the number of first pixels PIX 1 of the first display panel LCP 1 and the number of pixels PIX 2 of the second display panel LCP 2 are satisfied with a three-to-two relationship. In this exemplary embodiment, the first pixel group PG 1 of the first display panel LCP 1 includes the red pixel PIXR, the green pixel PIXG and the blue pixel PIXB. The second pixel group PG 2 of the second display panel LCP 2 includes a second pixel PIX 2 a and a third pixel PIX 2 b. The first pixel group PG 1 overlaps with the second pixel group PG 2 in planar view. Namely, the red pixel PIXR, the green pixel PIXG and the blue pixel PIXB overlap with the second pixel PIX 2 a and the third pixel PIX 2 b in planar view. A total area of three first pixels PIX 1 are almost same as a total area of two pixels PIX 2 .

In the example in FIG. 6 , the second pixel PIX 2 a included in the second pixel group PG 2 overlaps with the red pixel PIXR and the green pixel PIXG included in the first pixel group PG 1 in planar view. The third pixel PIX 2 b included in the second pixel group PG 2 overlaps with the green pixel PIXG and the blue pixel PIXB included in the first pixel group PG 1 in planar view. Specifically, the second pixel PIX 2 a overlaps with a whole of the red pixel PIXR and a part of the green pixel PIXG. The third pixel PIX 2 b overlaps with the rest of the green pixel PIXG and a whole of the blue pixel PIXB included in the first pixel group PG 1 in planar view.

In the second pixel PIX 2 a of the second display panel LCP 2 , a drain electrode of the second pixel electrode PIT 2 a and a drain electrode of the third pixel electrode PIT 2 b are electrically connected to the same second source line SL 2 . A gate electrode of the second pixel electrode PIT 2 a and a gate electrode of the third pixel electrode PIT 2 b are electrically connected to the same second gate line GL 2 . The second pixel electrode PIT 2 a is electrically connected to a source electrode of the second thin film transistor TFT 2 a, and the third pixel electrode PIT 2 b is electrically connected to a source electrode of the third thin film transistor TFT 2 b.

FIG. 7 is a sectional view taken along line B-B′ in FIGS. 6A and 6B . Sectional structures of the pixels PIX 1 and PIX 2 will be described below with reference to FIG. 7 .

In the thin film transistor substrate TFTB 1 forming the first pixel PIX 1 of the first display panel LCP 1 , the first gate lines GL 1 (see FIG. 6 ) are formed on a transparent substrate SUB 2 (glass substrate), and a gate insulating film GSN is formed so as to cover the first gate lines GL 1 . The first source lines SL 1 are formed on the gate insulating film GSN, and a protective film PAS and an organic film OPAS are formed so as to cover the first source lines SL 1 . A common electrode CIT 1 is formed on the organic film OPAS, and a protective film UPAS is formed so as to cover the common electrode CT 1 . The first pixel electrodes PIT 1 are formed on the protective film UPAS, and an alignment film (not illustrated) is formed so as to cover the first pixel electrodes PIT 1 . The first pixel electrode PIT 1 is electrically connected to a source electrode of the first thin film transistor TFT 1 (see, FIG. 6 ) via a contact hole (not shown). A plurality of slits extending in the column direction or the row direction may be formed in the first pixel electrode PIT 1 . In the opposing substrate CF 1 , the black matrix BM and the color filter layers FIL (red color filter layer FILR, green color filter layer FILG, and blue color filter layer FILB) are formed on a transparent substrate SUB 1 (glass substrate). An overcoat film OC 1 covers a surface of the color filter layers FIL, and an alignment film (not illustrated) is formed on the overcoat film OC 1 . Boundaries between color filter layers FIL adjacent to each other overlap with the first source lines SL 1 in planar view.

In the thin film transistor substrate TFTB 2 forming the pixel PIX 2 of the second display panel LCP 2 , the second gate lines GL 2 (see FIG. 6 ) are formed on a transparent substrate SUB 4 (glass substrate), and a gate insulating film GSN is formed so as to cover the second gate lines GL 2 . The second source lines SL 2 are formed on the gate insulating film GSN, and a protective film PAS and an organic film OPAS are formed so as to cover the second source lines SL 2 . A common electrode CIT 2 is formed on the organic film OPAS, and a protective film UPAS is formed so as to cover the common electrode CIT 2 . The pixel electrodes PIT 2 are formed on the protective film UPAS, and an alignment film (not illustrated) is formed so as to cover the pixel electrodes PIT 2 . The pixel electrode PIT 2 is electrically connected to a source electrode of the first thin film transistor TFT 2 (see, FIG. 6 ) via a contact hole (not shown). A second source line SL 2 disposed between the second pixel PIX 2 a and the third pixel PIX 2 b is positioned at the center of the first pixel PIX 1 of the first display panel LCP 1 in the row direction. In this exemplary embodiment, said second source line SL 2 disposed between the second pixel PIX 2 a and the third pixel PIX 2 b is positioned at the center of the green pixel PIXG in the row direction. A plurality of slits extending in the column direction or the row direction may be formed in the pixel electrode PIT 2 . In the opposing substrate CF 2 , the black matrix BM 2 is formed on a transparent substrate SUB 3 (glass substrate). An overcoat film OC 2 covers the black matrix BM 2 , and an alignment film (not illustrated) is formed on the overcoat film OC 2 . The black matrix BM 2 overlap with the second source lines SL 2 in planar view.

As described above, according to the first exemplary embodiment, the second pixel group PG 2 of the second display panel LCP 2 overlaps with a first pixel group PG 1 of the first display panel LCP 1 that includes the first color pixel PIXR, the second color pixel PIXG and the third color pixel PIXB in planar view. The second pixel group PG 2 includes the second pixel PIX 2 a and the third pixel PIX 2 b. The second thin film transistor TFT 2 a of the second pixel PIX 2 a and the third thin film transistor TFT 2 b of the third pixel PIX 2 b are electrically connected to the same second source line SL 2 and the same second gate line GL 2 . For example in the case that one pixel PIX 2 a of the second display panel LCP 2 is defective, the other pixel PIX 2 b of the second display panel LCP 2 can operate properly. Therefore, almost half of the first pixel group PG 1 can continue to display the image. That is to say, a whole of the first pixel group PG 1 can be prevented from becoming distorted.

Note that although a second source line SL 2 disposed between the second pixel PIX 2 a and the third pixel PIX 2 b is positioned at the center of the green pixel PIXG in the row direction, said second source line SL 2 may also be positioned at the center of the red pixel PIXR or the blue pixel PIXB in the row direction.

Second Exemplary Embodiment

A second exemplary embodiment of the present disclosure will be described below with reference to the drawings. For convenience, the same component as that of the first exemplary embodiment is designated by the same numeral, and the description will be omitted. In the second exemplary embodiment, the term defined in the first exemplary embodiment is used according to the definition of the first exemplary embodiment unless otherwise noted. The same holds true for the following exemplary embodiments.

The first display panel LCP 1 according to the second exemplary embodiment has a same structure as that of the first exemplary embodiment. FIG. 8 is a plan view illustrating the schematic configuration of the liquid crystal display device LCP 2 according to the second exemplary embodiment. FIGS. 9A and 9B are plan views of the second exemplary embodiment, illustrating a relationship between a first pixel group PG 1 of the first display panel LCP 1 and the second pixel group PG 2 of the second display panel LCP 2 .

In this exemplary embodiment, two pixels PIX 2 (PIX 2 a, PIX 2 b ) adjacent in the column direction are provided in a region surrounded by two second source lines SL 2 adjacent to each other and two second gate lines GL 2 adjacent to each other in planar view. Two thin film transistors TFT 2 adjacent in the column direction sandwiching the gate line GL 2 are electrically connected to a same gate line GL 2 and a same source line SL 2 . In other words, two thin film transistors TFT 2 disposed on either side of one gate line GL 2 are electrically connected to the same source line SL 2 and that gate line GL 2 . The thin film transistor TFT 2 includes a drain electrode electrically connected to the source line SL 2 , a source electrode electrically connected to the pixel electrode PIT 2 , and a gate electrode electrically connected to the gate line GL 2 . Drain electrodes of the two thin film transistors TFT 2 adjacent in the column direction through (sandwiching) the gate line GL 2 are electrically connected to each other and to the same source line SL 2 . In the second display panel LCP 2 , data voltage is simultaneously supplied with two pixel electrodes PIT 2 electrically connected to the one gate line GL 2 and the one source line SL 2 .

As shown in FIGS. 9A and 9B , the number of first pixels PIX 1 of the first display panel LCP 1 and the number of pixels PIX 2 of the second display panel LCP 2 are satisfied with a three-to-two relationship. In this exemplary embodiment, a first pixel group PG 1 of the first display panel LCP 1 includes the red pixel PIXR, the green pixel PIXG and the blue pixel PIXB, and a second pixel group PG 2 of the second display panel LCP 2 includes a second pixel PIX 2 a and a third pixel PIX 2 b. The first pixel group PG 1 overlaps with the second pixel group PG 2 in planar view. Namely, the red pixel PIXR, the green pixel PIXG and the blue pixel PIXB overlaps with the second pixel PIX 2 a and the third pixel PIX 2 b in planar view. A total area of three first pixels PIX 1 are almost same as a total area of two pixels PIX 2 .

In the example in FIGS. 9A and 9B , the second pixel PIX 2 a included in the second pixel group PG 2 overlaps with a part of the red pixel PIXR, a part of the green pixel PIXG and a part of the blue pixel PIXB included in the first pixel group PG 1 in planar view. The third pixel PIX 2 b included in the second pixel group PG 2 overlaps with the rest of the red pixel PIXR, the rest of the green pixel PIXG and the rest of the blue pixel PIXB included in the first pixel group PG 1 in planar view.

In the second pixel PIX 2 a of the second display panel LCP 2 , a drain electrode of the second pixel electrode PIT 2 a and a drain electrode of the third pixel electrode PIT 2 b are electrically connected to the same second source line SL 2 . A gate electrode of the second pixel electrode PIT 2 a and a gate electrode of the third pixel electrode PIT 2 b are electrically connected to the same second gate line GL 2 . The second pixel electrode PIT 2 a is electrically connected to a source electrode of the second thin film transistor TFT 2 a, and the third pixel electrode PIT 2 b is electrically connected to a source electrode of the third thin film transistor TFT 2 b.

According to the second exemplary embodiment, the second pixel group PG 2 of the second display panel LCP 2 , overlaps with the first pixel group PG 1 of the first display panel LCP 1 that includes the first color pixel PIXR, the second color pixel PIXG and the third color pixel PIXB in planar view. The second pixel group PG 2 includes the second pixel PIX 2 a and the third pixel PIX 2 b. The second thin film transistor TFT 2 a of the second pixel PIX 2 a and the third thin film transistor TFT 2 b of the third pixel PIX 2 b are electrically connected to the same second source line SL 2 and the same second gate line GL 2 . For example in the case that one pixel PIX 2 a of the second display panel LCP 2 is defective, the other pixel PIX 2 b of the second display panel LCP 2 can operate properly. Therefore, almost half of the first pixel group PG 1 can continue to display the image. That is to say, a whole of the first pixel group PG 1 can be prevented from becoming distorted when a defective pixel arises in the second display panel LCP 2 . In addition, because the almost half of the first pixel group PG 1 includes a half of the first color pixel PIXR, a half of the second color pixel PIXG and a half of the third color pixel PIXB, a color balance is maintained even if a defective pixel arises in the second display panel LCP 2 .

Third Exemplary Embodiment

FIG. 10 is a plan view illustrating the schematic configuration of the first pixel group PG 1 of the first display panel LCP 1 according to a third exemplary embodiment. FIG. 11 is a plan view illustrating the schematic configuration of the second pixel group PG 2 of the liquid crystal display device LCP 2 according to the third exemplary embodiment. FIG. 12 is a plan view illustrating arrangement of pixels in the second display panel LCP 2 according to the third exemplary embodiment.

In this exemplary embodiment, the number of first pixels PIX 1 of the first display panel LCP 1 and the number of pixels PIX 2 of the second display panel LCP 2 are satisfied with a twenty-seven-to-four relationship. As shown in FIG. 10 , one first pixel group PG 1 of the first display panel LCP 1 includes twenty-seven first pixels PIX 1 including nine red pixels PIXR, nine green pixels PIXG and nine blue pixels PIXB. As shown in FIG. 11 , one second pixel group PG 2 of the second display panel LCP 2 includes four pixels PIX 2 including a second pixel PIX 2 a, a third pixel PIX 2 b, a fourth pixel PIX 2 c and a fifth pixel PIX 2 d. One first pixel group PG 1 of the first display panel LCP 1 overlaps with one second pixel group PG 2 of the second display panel LCP 2 in planar view.

As shown in FIG. 11 , the second pixel PIX 2 a and the third pixel PIX 2 b are adjacent in the row direction through (sandwiching) a second source line SL 2 , the fourth pixel PIX 2 c and the fifth pixel PIX 2 d are adjacent in the row direction through (sandwiching) a second source line SL 2 . The second pixel PIX 2 a and the fourth pixel PIX 2 c are adjacent in the column direction through (sandwiching) a second gate line GL 2 , the third pixel PIX 2 c and the fifth pixel PIX 2 d are adjacent in the column direction through (sandwiching) a second gate line GL 2 . Each of gate electrodes (control electrodes) of the second thin film transistor TFT 2 a, the third thin film transistor TFT 2 b, the fourth thin film transistor TFT 2 c and the fifth thin film transistor TFT 2 d are electrically connected to a same second gate line GL 2 . Each of drain electrodes of the second thin film transistor TFT 2 a, the third thin film transistor TFT 2 b, the fourth thin film transistor TFT 2 c and the fifth thin film transistor TFT 2 d are electrically connected to a same second source line SL 2 . A source electrode of the second thin film transistor TFT 2 a is electrically connected to the second pixel electrode PIT 2 a. A source electrode of the third thin film transistor TFT 2 b is electrically connected to the third pixel electrode PIT 2 b. A source electrode of the fourth thin film transistor TFT 2 c is electrically connected to the fourth pixel electrode PIT 2 c. A source electrode of the fifth thin film transistor TFT 2 d is electrically connected to the fifth pixel electrode PIT 2 d. In the second display panel LCP 2 , data voltage is simultaneously supplied with four pixel electrodes PIT 2 a -PIT 2 d connected to the one gate line GL 2 and the one source line SL 2 .

According to the third exemplary embodiment, the second pixel group PG 2 of the second display panel LCP 2 , overlaps with the first pixel group PG 1 of the first display panel LCP 1 that includes the first color pixel PIXR, the second color pixel PIXG and the third color pixel PIXB. The second pixel group PG 2 includes the second pixel PIX 2 a, the third pixel PIX 2 b, the fourth pixel PIX 2 c and the fifth pixel PIX 2 d. The second thin film transistor TFT 2 a of the second pixel PIX 2 a, the third thin film transistor TFT 2 b of the third pixel PIX 2 b, the fourth thin film transistor TFT 2 c of the fourth pixel PIX 2 c and the fifth thin film transistor TFT 2 d of the fifth pixel PIX 2 d are electrically connected to the same second source line SL 2 and the same second gate line GL 2 . For example in the case that one pixel PIX 2 a of the second display panel LCP 2 is defective, the other pixels PIX 2 b - 2 d of the second display panel LCP 2 can operate properly. Therefore, almost three quarters of the first pixel group PG 1 can continue to display the image. That is to say, a whole of the first pixel group PG 1 can be prevented from becoming distorted when a defective pixel arises in the second display panel LCP 2 .

The second display panel LCP 2 according to the third exemplary embodiment is not limited to above structures. FIG. 13 is a plan view illustrating a variation of the second display panel LCP 2 according to the third exemplary embodiment. As shown in FIG. 13 , each second gate line GL 2 includes a first branch gate line GL 2 a and a second branch gate line GL 2 b. Each of gate electrodes of a thin film transistor TFT 2 a and a thin film transistor TFT 2 b are electrically connected to the first branch gate line GL 2 a. Each of gate electrodes of a thin film transistor TFT 2 c and a thin film transistor TFT 2 d are electrically connected to the second branch gate line GL 2 b.

Fourth Exemplary Embodiment

FIGS. 14A and 14B are plan views of a fourth exemplary embodiment illustrating a relationship between a first pixel group PG 1 of the first display panel LCP 1 and a second pixel group PG 2 of the second display panel LCP 2 , with the first pixel group PG 1 and the second pixel group PG 2 overlapping to each other. The first display panel LCP 1 according to the fourth exemplary embodiment has a same structure as that of the first exemplary embodiment (see, FIG. 3 ).

In this exemplary embodiment, two thin film transistors TFT 2 a and TFT 2 b disposed on either side of one source line SL 2 are connected to one pixel electrode PIT 2 that crosses over that source line SL 2 . Each of gate electrodes (control electrodes) of two thin film transistors TFT 2 a and TFT 2 b which are adjacent in the row direction through (sandwiching) a second source line SL 2 is electrically connected to a same second gate line GL 2 . Each of drain electrodes of the two thin film transistors TFT 2 a and TFT 2 b is electrically connected to said second source line SL 2 . Each of source electrodes of the two thin film transistors TFT 2 a and TFT 2 b is electrically connected to a same pixel electrode PIT 2 . In the second display panel LCP 2 , data voltage is supplied with one pixel electrode PIT 2 connected to the one gate line GL 2 and the one source line SL 2 , via two thin film transistors TFT 2 a and TFT 2 b.

As shown in FIGS. 14A and 14B , the number of first pixels PIX 1 of the first display panel LCP 1 and the number of pixels PIX 2 of the second display panel LCP 2 are satisfied with a three-to-one relationship. One first pixel group PG 1 of the first display panel LCP 1 includes a red pixel PIXR, a green pixel PIXG and a blue pixel PIXB. One second pixel group PG 2 of the second display panel LCP 2 includes one pixel PIX 2 . One first pixel group PG 1 of the first display panel LCP 1 overlaps with one second pixel group PG 2 of the second display panel LCP 2 in planar view. A total area of three first pixels PIX 1 are almost same as a total area of one pixel PIX 2 .

According to the forth exemplary embodiment, the second pixel group PG 2 of the second display panel LCP 2 , overlaps with a first pixel group PG 1 of the first display panel LCP 1 that includes the first color pixel PIXR, the second color pixel PIXG and the third color pixel PIXB. The second pixel group PG 2 includes one pixel PIX 2 . The thin film transistors TFT 2 a and TFT 2 b are electrically connected to the same second source line SL 2 and the same second gate line GL 2 . For example in the case that one thin film transistor TFT 2 a of the second display panel LCP 2 is defective, the other thin film transistor TFT 2 b of the second display panel LCP 2 can operate properly. Therefore, the pixel electrode PIT 2 electrically connected to the two thin film transistors TFT 2 a and TFT 2 b can receive data voltage via the other thin film transistor TFT 2 b, thus, the first pixel group PG 1 can continue to display the image. That is to say, a whole of the first pixel group PG 1 can be prevented from becoming distorted when a defective thin film transistor TFT 2 arises in the second display panel LCP 2 .

The second display panel LCP 2 according to the forth exemplary embodiment is not limited to above structures. FIGS. 15A and 15B are plan views illustrating a variation of the second display panel LCP 2 according to the forth exemplary embodiment. As shown in FIGS. 15A and 15B , each of gate electrodes (control electrodes) of two thin film transistors TFT 2 a and TFT 2 b which are adjacent in the column direction through (sandwiching) a second gate line GL 2 is electrically connected to said second gate line GL 2 . Each of drain electrodes of the two thin film transistors TFT 2 a and TFT 2 b is electrically connected to a same second source line SL 2 . Each of source electrodes of the two thin film transistors TFT 2 a and TFT 2 b is electrically connected to a same pixel electrode PIT 2 . In the second display panel LCP 2 shown in FIG. 15 , data voltage is supplied with one pixel electrode PIT 2 electrically connected to the one gate line GL 2 and the one source line SL 2 , via two thin film transistors TFT 2 a and TFT 2 b.

FIGS. 16A and 16B are plan views illustrating another variation of the second display panel LCP 2 according to the forth exemplary embodiment. As shown in FIGS. 16A and 16B , one pixel electrode PIT 2 (one pixel PIX 2 ) and one thin film transistor TFT 2 are provided in a region surrounded by two second source lines SL 2 adjacent to each other and two second gate lines GL 2 adjacent to each other in planar view. A gate electrode (control electrode) of the thin film transistor TFT 2 is electrically connected to the second gate line GL 2 , a drain electrode (first conductive electrode) of the thin film transistor TFT 2 is electrically connected to the second source line SL 2 . A source electrode (second conductive electrode) of the thin film transistor TFT 2 includes a first branch electrode SE 1 and a second branch electrode SE 1 . The first branch electrode SE 1 and the second branch electrode SE 1 are electrically connected to a same pixel electrode PIT 2 . In the second display panel LCP 2 shown in FIG. 16 , data voltage is supplied with one pixel electrode PIT 2 connected to the one gate line GL 2 and the one source line SL 2 , via the first branch electrode SE 1 and the second branch electrode SE 1 of the thin film transistor TFT 2 .

According to the variation shown in FIG. 16 , the second pixel group PG 2 of the second display panel LCP 2 overlaps with a first pixel group PG 1 of the first display panel LCP 1 that includes the first color pixel PIXR, the second color pixel PIXG and the third color pixel PIXB in planar view. The second pixel group PG 2 consists of one pixel PIX 2 . A source electrode (second conductive electrode) of the thin film transistor TFT 2 includes a first branch electrode SE 1 and a second branch electrode SE 1 which are electrically connected to the same pixel electrode PIT 2 . For example in the case that a contact area between the first branch electrode SE 1 and the pixel electrode PIT 2 is defective, the second branch electrode SE 2 can supply data voltage with the pixel electrode PIT 2 . Thus, a whole of the first pixel group PG 1 can be prevented from becoming distorted when a defective branch electrode SE 1 arises in the second display panel LCP 2 .

FIG. 17 is a plan view illustrating another variation of the second display panel LCP 2 according to the forth exemplary embodiment. As shown in FIG. 17 , a second pixel group PG 2 of the second display panel LCP 2 may include two pixels PIX 2 (PIX 2 a, PIX 2 b ). The second pixel PIX 2 a and the third pixel PIX 2 b are adjacent to each other in the column direction through (sandwiching) a second gate line GL 2 . Each of gate electrodes (control electrodes) of a second thin film transistor TFT 2 a, a third thin film transistor TFT 2 b, a fourth thin film transistor TFT 2 c and a fifth thin film transistor TFT 2 d are electrically connected to a same second gate line GL 2 . Each of drain electrodes of the second thin film transistor TFT 2 a, the third thin film transistor TFT 2 b, the fourth thin film transistor TFT 2 c and the fifth thin film transistor TFT 2 d are electrically connected to a same second source line SL 2 . Each of source electrodes of the second thin film transistor TFT 2 a and the third thin film transistor TFT 2 b is electrically connected to the second pixel electrode PIT 2 a. Each of source electrodes of the fourth thin film transistor TFT 2 c and the fifth thin film transistor TFT 2 d is electrically connected to the third pixel electrode PIT 2 b. In the second display panel LCP 2 , data voltage is supplied with the second pixel electrode PIT 2 a via the second thin film transistor TFT 2 a and the third thin film transistor TFT 2 b, and data voltage is supplied with the third pixel electrode PIT 2 b via the fourth thin film transistor TFT 2 c and the fifth thin film transistor TFT 2 d.

According to the variation shown in FIG. 17 , the second pixel group PG 2 of the second display panel LCP 2 overlaps with the first pixel group PG 1 of the first display panel LCP 1 that includes the first color pixel PIXR, the second color pixel PIXG and the third color pixel PIXB in planar view. The second pixel group PG 2 includes the second pixel PIX 2 a and the third pixel PIX 2 b. The thin film transistors TFT 2 a, TFT 2 b of the second pixel PIX 2 a and the thin film transistors TFT 2 c, TFT 2 d of the third pixel PIX 2 b are electrically connected to the same second source line SL 2 and the same second gate line GL 2 . For example in the case that one pixel PIX 2 a of the second display panel LCP 2 is defective, the other pixel PIX 2 b of the second display panel LCP 2 can operate properly. Therefore, almost half of the first pixel group PG 1 can continue to display the image. Also, for example in the case that one thin film transistor TFT 2 a of the second display panel LCP 2 is defective, the other thin film transistors TFT 2 b - 2 d of the second display panel LCP 2 can operate properly. Therefore, the pixel electrodes PIT 2 a, PIT 2 b electrically connected to these thin film transistors TFT 2 a -TFT 2 d can receive data voltage via the other thin film transistors TFT 2 b -TFT 2 d. thus, the first pixel group PG 1 can continue to display the image. That is to say, a whole of the first pixel group PG 1 can be prevented from becoming distorted.

FIG. 18 is a plan view illustrating another variation of the second display panel LCP 2 according to the forth exemplary embodiment. As shown in FIG. 18 , a second pixel group PG 2 of the second display panel LCP 2 may consist of one pixel PIX 2 , and the one pixel PIX 2 is connected to four thin film transistors TFT 2 a -TFT 2 d. Each of gate electrodes (control electrodes) of a second thin film transistor TFT 2 a, a third thin film transistor TFT 2 b, a fourth thin film transistor TFT 2 c and a fifth thin film transistor TFT 2 d are electrically connected to the a second gate line GL 2 . Each of drain electrodes of the second thin film transistor TFT 2 a, the third thin film transistor TFT 2 b , the fourth thin film transistor TFT 2 c and the fifth thin film transistor TFT 2 d are electrically connected to a same second source line SL 2 . Each of source electrodes of the second thin film transistor TFT 2 a, the third thin film transistor TFT 2 b, the fourth thin film transistor TFT 2 c and the fifth thin film transistor TFT 2 d is electrically connected to the pixel electrode PIT 2 . In the second display panel LCP 2 , data voltage is supplied with the pixel electrode PIT 2 via four thin film transistors TFT 2 a -TFT 2 d.

According to the variation shown in FIG. 18 , the second pixel group PG 2 of the second display panel LCP 2 overlaps with the first pixel group PG 1 of the first display panel LCP 1 that includes the first color pixel PIXR, the second color pixel PIXG and the third color pixel PIXB in plenary view. The second pixel group PG 2 includes one pixel PIX 2 . The thin film transistors TFT 2 a -TFT 2 d of the pixel PIX 2 are electrically connected to the same second source line SL 2 and the same second gate line GL 2 . For example in the case that one thin film transistor TFT 2 a of the second display panel LCP 2 is defective, the other thin film transistors TFT 2 b - 2 d of the second display panel LCP 2 can operate properly. Therefore, the pixel electrode PIT 2 electrically connected to these thin film transistors TFT 2 a -TFT 2 d can receive data voltage via the other thin film transistors TFT 2 b -TFT 2 d. Thus, the first pixel group PG 1 can continue to display the image. That is to say, a whole of the first pixel group PG 1 can be prevented from becoming distorted when a defective thin film transistor TFT 2 arises in the second display panel LCP 2 .

In the above, the specific embodiments of the present application have been described, but the present application is not limited to the above-mentioned embodiments, and various modifications may be made as appropriate without departing from the spirit of the present application.