Semiconductor circuit

This application claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2017-059970 filed on Mar. 24, 2017, the entire content of which is hereby incorporated by reference.

1. Field of the Invention

The present invention relates to a semiconductor circuit.

2. Background Art

In screening of a semiconductor circuit, there is a case where a high voltage is applied to a MOS transistor included in the semiconductor circuit. In general, a gate terminal of a MOS transistor is controlled by a control circuit in such a manner that a prescribed voltage is applied to the gate terminal. There has therefore been a case where in order to apply the high voltage to the MOS transistor, an additional circuit and an additional terminal have been used in addition to a circuit used for the normal operation of the semiconductor circuit.

There has heretofore been known a method of inserting an additional circuit between a protection circuit connected to a gate terminal of a MOS transistor and protecting a high voltage of a predetermined voltage or more to be applied thereto, and the gate terminal, prohibiting the operation of the protection circuit by the additional circuit, and applying an inspection voltage of a predetermine voltage or more (Japanese Patent Application Laid-Open H2-288366, for example).

There has been also known a method of connecting an additional gate terminal which is a terminal used only upon an inspection such as screening and is provided without via a control circuit, between a gate terminal of a MOS transistor and the control circuit, and applying an inspection voltage of a predetermined voltage or more to the additional gate terminal (Japanese Patent Application Laid-Open H7-283370, for example).

In a related art, however, since a gate terminal of a MOS transistor for an output driver is provided with an additional circuit and an additional terminal, these additions may affect the original operation of the MOS transistor.

The present invention has been made to provide a semiconductor circuit which is configured to control the resistance value of a voltage division resistor by a control signal from the outside and which can be inspected with a simple configuration without affecting the original operation of a MOS transistor.

According to one embodiment of the present invention there is provided a semiconductor circuit converting an input voltage applied thereto to a predetermined output voltage and supplying the same from a voltage output terminal, the semiconductor circuit, comprising: a MOS transistor; an operational amplifier; a first resistor; a second resistor; a third resistor; an external terminal; and a switch,

the first resistor, the second resistor, and the third resistor being connected in series between the voltage output terminal and a ground terminal in this order,

the MOS transistor having a source terminal connected to an input voltage terminal to which the input voltage is applied, and a drain terminal connected to the voltage output terminal,

the operational amplifier having a non-inversion input terminal to which a reference voltage is applied, an inversion input terminal to which a voltage of a connection point of the first resistor and the second resistor is applied, and an output terminal to which a gate terminal of the MOS transistor is connected,

the switch having a control terminal connected to the external terminal and being connected in parallel with the third resistor,

an open state of the switch brought by a signal input to the external terminal, permitting an output of the output voltage from the voltage output terminal based on a voltage divided between the first resistor and a combined resistance of the second resistor the third resistor, and

a closed state of the switch brought by the signal input to the external terminal, permitting an output of the output voltage from the voltage output terminal based on a voltage divided between the first resistor and the second resistor.

According to the present invention, there can be provided a semiconductor circuit which is configured to control the resistance value of a voltage division resistor by a control signal from the outside and which can be inspected with a simple configuration without affecting the original operation of a MOS transistor.

FIG. 1 is a circuit diagram illustrating a semiconductor circuit according to a first embodiment;

FIG. 2 is a circuit diagram illustrating the configuration of a semiconductor circuit according to a second embodiment;

FIG. 3 is a circuit diagram illustrating a semiconductor circuit according to a third embodiment; and

FIG. 4 is a table illustrating the relationship between each state according to the third embodiment, the operation of an operational amplifier, and a state of a MOS transistor.

First Embodiment

A first embodiment of the present invention will hereinafter be described with reference to the accompanying drawings.

<Configuration of Semiconductor Circuit>

FIG. 1 is a circuit diagram illustrating a semiconductor circuit 1 according to the first embodiment.

As illustrated in FIG. 1 , the semiconductor circuit 1 is equipped with an operational amplifier OP, a MOS (Metal-Oxide-Semiconductor) transistor Tr 1 , a MOS transistor Tr 2 , a fuse F 1 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , and an external terminal P 1 . The MOS transistor Tr 1 is, for example, a P-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Further, the MOS transistor Tr 2 is, for example, an N-type MOSFET.

The operational amplifier OP is equipped with a non-inversion input terminal, an inversion input terminal, and an output terminal. The MOS transistor Tr 1 is equipped with a gate terminal, a source terminal, and a drain terminal. The MOS transistor Tr 2 is equipped with a gate terminal, a source terminal, and a drain terminal. The fuse F 1 is equipped with a first terminal (terminal F 1 a hereinafter) and a second terminal (terminal F 1 b hereinafter). The first resistor R 1 is equipped with a first terminal (terminal R 1 a hereinafter) and a second terminal (terminal R 1 b hereinafter). The second resistor R 2 is equipped with a first terminal (terminal R 2 a hereinafter) and a second terminal (terminal R 2 b hereinafter). The third resistor R 3 is equipped with a first terminal (terminal R 3 a hereinafter) and a second terminal (terminal R 3 b hereinafter).

The first resistor R 1 , the second resistor R 2 , and the third resistor R 3 are connected in series. Specifically, the terminal R 1 b and the terminal R 2 a are connected. Further, the terminal R 2 b and the terminal R 3 a are connected. The terminal R 3 b is grounded through the ground terminal GND. The third resistor R 3 and the MOS transistor Tr 2 are connected to each other in parallel through the fuse F 1 . Specifically, the drain terminal of the MOS transistor Tr 2 and the terminal R 3 b are connected. The source terminal of the MOS transistor Tr 2 and the terminal F 1 a are connected. The terminal F 1 b and the terminal R 3 a are connected. Further, the gate terminal of the MOS transistor Tr 2 and the external terminal P 1 are connected.

A reference voltage Vref used for comparison with a feedback voltage of the operational amplifier OP is connected to the non-inversion input terminal of the operational amplifier OP. The gate terminal of the MOS transistor Tr 1 is connected to the output terminal of the operational amplifier OP. The source terminal of the MOS transistor Tr 1 is connected to the Vdd terminal which is an input voltage terminal to which an input voltage Vdd to the semiconductor circuit 1 is applied. The drain terminal of the MOS transistor Tr 1 is connected to the terminal R 1 a . A potential of a connection point (connection point of the terminals R 1 b and R 2 a ) of the first resistor R 1 and the second resistor R 2 is applied (connected) to the inversion input terminal of the operational amplifier OP. Further, a potential of a connection point (connection point of the drain terminal of the MOS transistor Tr 1 and terminal R 1 a ) of the MOS transistor Tr 1 and the first resistor R 1 is supplied as an output voltage Vout of the semiconductor circuit 1 . Here, a voltage output terminal P 2 from which the output voltage Vout is supplied is connected to the connection point of the drain terminal of the MOS transistor Tr 1 and the terminal R 1 a.

<Operation of Semiconductor Circuit 1 >

The operation of the semiconductor circuit 1 will hereinafter be described.

The semiconductor circuit 1 is a circuit which supplies a desired output voltage (output voltage Vout 1 hereinafter) from the voltage output terminal P 2 . The desired voltage is obtained by conversion of the input voltage Vdd applied to the semiconductor circuit 1 through the Vdd terminal which is the input voltage terminal. The output voltage Vout 1 is a voltage at which a voltage obtained by dividing the output voltage Vout by a combined resistance (combined resistance Rc hereinafter) of the second resistor R 2 and the third resistor R 3 , and the first resistor R 1 , and the reference voltage Vref become equal.

When the resistance value of the first resistor R 1 is assumed to be R 1 , the resistance value of the second resistor R 2 is assumed to be R 2 , the resistance value of the third resistor R 3 is assumed to be R 3 , the voltage value of the reference voltage Vref is assumed to be Vref, and the voltage value of the output voltage Vout 1 is assumed to be Vout 1 , the relationship between Vout, R 1 , R 2 , R 3 and Vref is represented by an equation (1):

V out1=( V ref/( R 2+ R 3))×( R 1+ R 2+ R 3)  (1)

Here, when the fuse F 1 is not cut through melting, the MOS transistor Tr 2 is controlled in terms of its ON and OFF states according to a voltage value of a signal (signal S 1 hereinafter) input from the external terminal P 1 to the gate terminal of the MOS transistor Tr 2 . When the MOS transistor Tr 2 is controlled to the ON state, the MOS transistor Tr 2 short-circuits both ends of the third resistor R 3 . In other words, when the MOS transistor Tr 2 is in the ON state, the terminal R 2 b of the second resistor R 2 is grounded through the ground terminal GND. In this case, the semiconductor circuit 1 outputs an output voltage Vout (output voltage Vout 2 hereinafter) in such a manner that a voltage obtained by dividing the output voltage Vout by the first resistor R 1 and the second resistor R 2 , and the reference voltage Vref become equal to each other. When the voltage value of the output voltage Vout 2 is assumed to be Vout 2 , the relationship between Vout 2 , R 1 , R 2 and Vref is represented by an equation (2).

V out2=( V ref/ R 2)×( R 1+ R 2)  (2)

Here, each of the first resistor R 1 and the second resistor R 2 has a resistance value at which the voltage obtained by dividing the input voltage Vdd by the first resistor R 1 and the second resistor R 2 becomes lower than the reference voltage Vref. Thus, the operational amplifier OP continues to output a signal of a low level (the same potential as ground) from its output terminal to the gate terminal of the MOS transistor Tr 1 . That is, the input voltage Vdd continues to be applied between the gate terminal of the MOS transistor Tr 1 and the source terminal thereof, and hence the MOS transistor Tr 1 is screened.

Accordingly, the semiconductor circuit 1 is capable of screening the MOS transistor Tr 1 without providing an additional circuit and an additional terminal at the gate terminal of the MOS transistor Tr 1 .

When the fuse F 1 is cut through melting, the connection between the third resistor R 3 and the MOS transistor Tr 2 is cut off. In other words, when the fuse F 1 is cut through melting, both ends of the third resistor R 3 are not short-circuited even though the MOS transistor Tr 2 is brought into the ON state. Thus, when the fuse F 1 is cut through melting, the semiconductor circuit 1 outputs the output voltage Vout 1 irrespective of the operating state of the MOS transistor Tr 2 .

<Summary of First Embodiment>

As described above, when the MOS transistor Tr 2 is controlled to the OFF state, the semiconductor circuit 1 according to the present embodiment applies an inspection voltage higher than a normal voltage between the gate terminal of the MOS transistor Tr 1 and the source terminal thereof. Thus, the semiconductor circuit 1 according to the present embodiment is capable of applying an inspection voltage higher than a prescribed voltage between the gate terminal of the MOS transistor Tr 1 and the source terminal thereof upon execution of an inspection such as screening.

Thus, according to the semiconductor circuit 1 according to the present embodiment, the inspection of the MOS transistor Tr 1 can be carried out with a simple configuration without affecting the original operation of the MOS transistor Tr 1 .

Also, when the MOS transistor Tr 2 is controlled to the OFF state, the semiconductor circuit 1 according to the present embodiment outputs a desired output voltage (output voltage Vout 1 ). According to the semiconductor circuit 1 according to the present embodiment, it is possible to confirm whether the first resistor R 1 , the second resistor R 2 , and the third resistor R 3 are set (trimmed) to a resistance value at which the desired output voltage can be supplied.

Further, the semiconductor circuit 1 according to the present embodiment is equipped with the fuse F 1 connected in series between the MOS transistor Tr 2 and the third resistor R 3 . The connection between the third resistor R 3 and the MOS transistor Tr 2 is cut off accompanied by the melting of the fuse F 1 .

Here, only upon execution of the inspection such as screening, the semiconductor circuit 1 preferably outputs an inspection voltage (output voltage Vout 2 ) and outputs a desired output voltage (output voltage Vout 1 ) after the inspection. According to the semiconductor circuit 1 according to the present embodiment, the output voltage after the inspection (cutting of fuse F 1 through melting) can be made to be a desired output voltage by cutting the fuse F 1 after the inspection such as screening.

Second Embodiment

A second embodiment of the present invention will hereinafter be described with reference to the accompanying drawings.

Here, an external terminal P 1 is preferably an external terminal used for the normal operation of a semiconductor circuit. The second embodiment will describe the case where the external terminal P 1 is a chip enable terminal which switches the operation of a semiconductor circuit 2 between effective and ineffective.

Incidentally, configurations similar to those in the aforementioned embodiment are assigned the same reference numerals, and their description will be omitted.

<Configuration of Semiconductor Circuit 2 >

FIG. 2 is a circuit diagram illustrating the configuration of the semiconductor circuit 2 according to the second embodiment.

As illustrated in FIG. 2 , the semiconductor circuit 2 according to the present embodiment is equipped with an operational amplifier OP, a MOS transistor Tr 1 , a MOS transistor Tr 2 , a fuse F 1 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , the external terminal P 1 , a voltage output terminal P 2 , a first logic circuit RG 1 , a second logic circuit RG 2 , and a fuse F 2 . The first logic circuit RG 1 is equipped with a first terminal (terminal RG 1 a hereinafter), a second terminal (terminal RG 1 b hereinafter), and a third terminal (terminal RG 1 c hereinafter). The second logic circuit RG 2 is equipped with a first terminal (terminal RG 2 a hereinafter) and a second terminal (terminal RG 2 b hereinafter). The fuse F 2 is equipped with a first terminal (terminal F 2 a hereinafter) and a second terminal (terminal F 2 b hereinafter).

Further, in the present embodiment, the operational amplifier OP is equipped with a fourth terminal (terminal OPd hereinafter). The terminal OPd is an input terminal input with a control signal (control signal S 2 hereinafter) which controls the operation of the operational amplifier OP (semiconductor circuit 2 ) to be effective or ineffective.

The terminal OPd and the external terminal P 1 are connected through the first logic circuit RG 1 . Specifically, the external terminal P 1 and the terminal RG 1 b are connected through a Schmidt trigger ST 1 . The terminal RG 1 c and the terminal OPd are connected. An input voltage Vdd is applied to the first logic circuit RG 1 through the fuse F 2 . Specifically, the terminal F 2 a and the Vdd terminal which is the input voltage terminal are connected. The terminal F 2 b and the terminal RG 1 a are connected.

Further, a gate terminal of the MOS transistor Tr 2 and the external terminal P 1 are connected through the second logic circuit RG 2 . Specifically, the external terminal P 1 and the terminal RG 2 a are connected through the Schmidt trigger ST 1 . The terminal RG 2 b and the gate terminal of the MOS transistor Tr 2 are connected.

The first logic circuit RG 1 is equipped with a MOS transistor Tr 3 , an OR circuit OR 1 , and a NOT circuit NT 1 . The MOS transistor Tr 3 is, for example, a depletion type N type MOSFET. A gate terminal of the MOS transistor Tr 3 and a source terminal thereof are grounded. A drain terminal of the MOS transistor Tr 3 and the terminal RG 1 a are connected. The potential of the terminal RG 1 b and the potential of the drain terminal of the MOS transistor Tr 3 are input to the OR circuit OR 1 as signals.

The second logic circuit RG 2 is equipped with a NOT circuit NT 2 . Specifically, the NOT circuit NT 2 is connected between the terminal RG 2 a and the terminal RG 2 b.

Incidentally, the NOT circuit NT 1 and the NOT circuit NT 2 are provided corresponding to the operation logic of the terminal OPd of the operational amplifier OP and the MOS transistor Tr 2 .

<Operation of Semiconductor Circuit 2 >

The operation of the semiconductor circuit 2 will be described below.

As described above, the external terminal P 1 is of the chip enable terminal. When the semiconductor circuit 2 is made effective in one example of the present embodiment, a high level potential is applied to the external terminal P 1 as the control signal S 2 . Further, when the semiconductor circuit 2 is made ineffective, a low level potential is applied to the external terminal P 1 as the control signal S 2 . In other words, when a high level signal is provided to the terminal OPd of the operational amplifier OP, the operation of the operational amplifier OP is effective. Further, when a low level signal is provided to the terminal OPd of the operational amplifier OP, the operation of the operational amplifier OP is ineffective.

<Operation of First Logic Circuit RG 1 Based on Control Signal S 2 >

When the semiconductor circuit 2 is in an operating state (state with the input voltage Vdd being applied) and the fuse F 2 is not cut through melting, the potential of the drain terminal of the MOS transistor Tr 3 is the same potential (high level) as the input voltage Vdd. Thus, when the semiconductor circuit 2 is in the operating state and the fuse F 2 is not cut through melting, the output of the OR circuit OR 1 is always at the high level irrespective of the control signal S 2 input to the external terminal P 1 . That is, when the fuse F 2 is not cut through melting and the semiconductor circuit 2 is in the operating state, the operation of the operational amplifier OP is always effective.

Further, when the semiconductor circuit 2 is in a stop state (state with no input voltage Vdd being applied) or the fuse F 2 is cut through melting, the potential of the drain terminal of the MOS transistor Tr 3 is the same potential (low level) as the ground. Thus, the output of the OR circuit matches with the control signal S 2 input to the external terminal P 1 . That is, when the fuse F 2 is cut through melting, the operation of the operational amplifier OP (semiconductor circuit 2 ) is controlled effectively or ineffectively based on the control signal S 2 input to the external terminal P 1 .

<Operation of Second Logic Circuit RG 2 Based on Control Signal S 2 >

The NOT circuit NT 2 included in the second logic circuit RG 2 inverts the control signal S 2 input to the external terminal P 1 and outputs it as a signal S 1 . Specifically, when a low-level control signal S 2 is applied to the external terminal P 1 (terminal RG 2 a ), the second logic circuit RG 2 outputs a high level signal S 1 from the terminal RG 2 b . Further, when a high-level control signal S 2 is applied to the external terminal P 1 , the second logic circuit RG 2 outputs a low level signal S 1 from the terminal RG 2 b.

Since subsequent configurations are similar to those in the above-described embodiment, their description will be omitted.

<Summary of Second Embodiment>

As described above, the semiconductor circuit 2 according to the present embodiment is further equipped with the fuse F 2 . The operational amplifier OP is equipped with the terminal OPd input with the control signal S 2 which controls the operation of the operational amplifier OP to be effective or ineffective. The control signal S 2 input from the external terminal P 1 is provided to the terminal OPd through the first logic circuit RG 1 .

In the semiconductor circuit 2 according to the present embodiment, the operation of the operational amplifier OP is always controlled effectively irrespective of the control signal S 2 input to the external terminal P 1 until cutting of the fuse F 2 . After the cutting of the fuse F 2 , the operation of the operational amplifier OP is controlled based on the signal S 1 input to the external terminal P 1 .

Thus, in the semiconductor circuit 2 according to the present embodiment, the external terminal P 1 can be used as the input terminal for the signal (signal S 1 ) which switches between the desired output voltage and the inspection voltage until the cutting of the fuse F 2 through melting. After the cutting of the fuse F 2 (e.g., after the inspection such as screening is done), the external terminal P 1 can be used as the chip enable terminal. Therefore, according to the semiconductor circuit 2 according to the present embodiment, it is possible to inspect the MOS transistor Tr 1 with a simple configuration by using the terminal (external terminal P 1 being the chip enable terminal in this one example) used for the normal operation of the semiconductor circuit 2 .

Third Embodiment

A third embodiment of the present invention will hereinafter be described with reference to the accompanying drawings.

The second embodiment has described the semiconductor circuit 2 which switches between the desired output voltage and the inspection voltage by using the external terminal P 1 being the chip enable terminal as the input terminal for the signal S 1 .

The third embodiment will describe a semiconductor circuit 3 which switches between a desired output voltage and an inspection voltage by using an external terminal P 1 and which is capable of confirming whether the external terminal P 1 functions as a chip enable terminal.

Incidentally, configurations similar to those in the above-described embodiment are assigned the same reference numerals, and their description will be omitted.

<Configuration of Semiconductor Circuit>

FIG. 3 is a circuit diagram illustrating the semiconductor circuit 3 according to the third embodiment.

As illustrated in FIG. 3 , the semiconductor circuit 3 according to the present embodiment is equipped with an operational amplifier OP, a MOS transistor Tr 1 , a MOS transistor Tr 2 , a fuse F 1 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , the external terminal P 1 , a voltage output terminal P 2 , a third logic circuit RG 3 , and a fourth logic circuit RG 4 .

The third logic circuit RG 3 is equipped with a first terminal (terminal RG 3 a ) and a second terminal (terminal RG 3 b ). The fourth logic circuit RG 4 is equipped with a first terminal (terminal RG 4 a ) and a second terminal (terminal RG 4 b ).

A terminal OPd and the external terminal P 1 are connected through the third logic circuit RG 3 . Specifically, the external terminal P 1 and the terminal RG 3 a are connected. The terminal RG 3 b and the terminal OPd are connected. Further, a gate terminal of the MOS transistor Tr 2 and the external terminal P 1 are connected through the fourth logic circuit RG 4 . Specifically, the external terminal P 1 and the terminal RG 4 a are connected. The terminal RG 4 b and the gate terminal of the MOS transistor Tr 2 are connected.

The third logic circuit RG 3 is equipped with a Schmidt trigger ST 2 and a NOT circuit NT 3 . The Schmidt trigger ST 2 and the NOT circuit NT 3 are connected in series between the terminal RG 3 a and the terminal RG 3 b in the order of the Schmidt trigger ST 2 and the NOT circuit NT 3 . The Schmidt trigger ST 2 inverts a control signal S 2 input thereto and outputs the same therefrom.

The fourth logic circuit RG 4 is equipped with a Schmidt trigger ST 3 , a NOT circuit NT 4 , and a NOT circuit NT 5 . The Schmidt trigger ST 3 , the NOT circuit NT 4 , and the NOT circuit NT 5 are connected in series between the terminal RG 4 a and the terminal RG 4 b in the order of the Schmidt trigger ST 3 , the NOT circuit NT 4 , and the NOT circuit NT 5 . The Schmidt trigger ST 3 inverts the control signal S 2 input thereto and outputs the same therefrom.

Incidentally, the NOT circuit NT 3 , the NOT circuit NT 4 , and the NOT circuit NT 5 are provided corresponding to the operation logic of the terminal OPd of the operational amplifier OP and the MOS transistor Tr 2 .

<Operation of Semiconductor Circuit 3 >

A description will be made below about the operation of the semiconductor circuit 3 .

As described above, the external terminal P 1 is of the chip enable terminal. Further, when the semiconductor circuit 2 is made effective, a high level potential is applied to the external terminal P 1 as the control signal S 2 . Also, when the semiconductor circuit 2 is made ineffective, a low level potential is applied to the external terminal P 1 as the control signal S 2 .

Here, the Schmidt trigger ST 2 and the Schmidt trigger ST 3 are respectively different in terms of a threshold value relative to the input signal (control signal S 2 in this example). In the subsequent description, the threshold value of the Schmidt trigger ST 2 is described as a threshold value TH 2 , and the threshold value of the Schmidt trigger ST 3 is described as a threshold value TH 3 . One example of the present embodiment will describe a case where the threshold value TH 3 is larger than the threshold value TH 2 between the threshold values TH 2 and TH 3

Further, one example of the present embodiment will describe a case where the voltage (control signal S 2 ) input to the external terminal P 1 as the control signal S 2 is transitioned in the order of a first state, a second state, and a third state. Specifically, the control signal S 2 is a voltage larger than the threshold value TH 3 and the threshold value TH 2 in the first state. Also, the control signal S 2 is a voltage smaller than the threshold value TH 3 and larger than the threshold value TH 2 in the second state. Further, the control signal S 2 is a voltage smaller than the threshold value TH 3 and the threshold value TH 2 in the third state.

<Operation of Third Logic Circuit RG 3 Based on Control Signal S 2 >

When the voltage of the control signal S 2 is larger than the threshold value TH 2 , the Schmidt trigger ST 2 outputs a high level signal. Further, when the voltage of the control signal S 2 is smaller than the threshold value TH 2 , the Schmidt trigger ST 2 outputs a low level signal. Thus, when the voltage of the control signal S 2 input to the external terminal P 1 is larger than the threshold value TH 2 , the high level signal is supplied from the terminal RG 3 b and input to the terminal OPd. Further, when the voltage of the control signal S 2 input to the external terminal P 1 is smaller than the threshold value TH 2 , the low level signal is supplied from the terminal RG 3 b and input to the terminal OPd.

<Operation of Fourth Logic Circuit RG 4 Based on Control Signal S 2 >

When the voltage of the control signal S 2 is larger than the threshold value TH 3 , the Schmidt trigger ST 3 outputs a high level signal. Further, when the voltage of the control signal S 2 is smaller than the threshold value TH 3 , the Schmidt trigger ST 3 outputs a low level signal. Thus, when the voltage of the control signal S 2 input to the external terminal P 1 is larger than the threshold value TH 3 , the low level signal is supplied from the terminal RG 4 b and input to the gate terminal of the MOS transistor Tr 2 . Further, when the voltage of the control signal S 2 input to the external terminal P 1 is smaller than the threshold value TH 3 , the high level signal is supplied from the terminal RG 4 b and input to the gate terminal of the MOS transistor Tr 2 .

<Concerning the Details of Each State>

A description will be made below about the details of the first state, second state, and third state with reference to FIG. 4 .

FIG. 4 is a table illustrating the relationship between each state according to the third embodiment, the operation of the operational amplifier OP, and the state of the MOS transistor Tr 2 .

As illustrated in FIG. 4 , in the first state, the operation of the operational amplifier OP is controlled effectively, and the state of the MOS transistor Tr 2 is controlled to an OFF state. Also, in the second state, the operation of the operational amplifier OP is controlled effectively, and the state of the MOS transistor Tr 2 is controlled to an ON state. Further, in the third state, the operation of the operational amplifier OP is controlled ineffectively, and the state of the MOS transistor Tr 2 is controlled to the ON state.

<Summary of Third Embodiment>

As described above, the semiconductor circuit 3 according to the present embodiment is equipped with the third logic circuit RG 3 equipped with the Schmidt trigger ST 2 , and the fourth logic circuit RG 4 equipped with the Schmidt trigger ST 3 . In the semiconductor circuit 3 according to the present embodiment, the threshold values of the Schmidt triggers ST 2 and ST 3 are respectively different. Accompanying the action of changing the voltage applied to the external terminal P 1 as the control signal S 2 , the semiconductor circuit 3 according to the present embodiment outputs the desired output voltage (output voltage Vout 1 ) and outputs the inspection voltage (output voltage Vout 2 ) to thereby bring the operation of the semiconductor circuit 3 (operational amplifier OP) to the ineffective state.

When the voltage of the control signal S 2 is higher than the threshold value TH 2 and the threshold value TH 3 , the semiconductor circuit 3 according to the present embodiment outputs the desired output voltage (output voltage Vout 1 ). Thus, the semiconductor circuit 3 according to the present embodiment is capable of confirming whether the desired output voltage (output voltage Vout 1 ) is supplied from the semiconductor circuit 3 .

Also, when the voltage of the control signal S 2 is higher than the threshold value TH 2 and is lower than the threshold value TH 3 , the semiconductor circuit 3 according to the present embodiment applies an inspection voltage higher than a normal voltage between the gate terminal of the MOS transistor Tr 1 and the source terminal thereof. Thus, when performing an inspection such as screening on the semiconductor circuit 3 , the semiconductor circuit 3 according to the present embodiment is capable of applying an inspection voltage higher than a desired output voltage between the gate terminal of the MOS transistor Tr 1 and the source terminal thereof.

Further, when the voltage of the control signal S 2 is a voltage lower than the threshold value TH 2 and the threshold value TH 3 , the semiconductor circuit 3 according to the present embodiment controls the operation of the operational amplifier OP to be ineffective. Thus, the semiconductor circuit 3 according to the present embodiment is capable of inspecting based on the input from the chip enable terminal (external terminal P 1 in this one example) whether the operation of the operational amplifier OP is controlled.

Thus, according to the semiconductor circuit 3 according to the present embodiment, the semiconductor circuit 3 switches between the desired output voltage and the inspection voltage by using the external terminal P 1 and is capable of confirming whether the external terminal P 1 functions as the chip enable terminal.

Incidentally, although the above description has been made about the case where the voltage (control signal S 2 ) input to the external terminal P 1 as the control signal S 2 is transitioned in the order of the first, second and third states, the present invention is not limited to it. The control signal S 2 may be configured to be transitioned in the order of the third, second and first states.