Semiconductor device including integrated circuit of flip-flops and switches

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-170045, filed on Sep. 5, 2017; the entire contents of which are incorporated herein by reference.

Embodiments generally relate to a semiconductor device and a method for manufacturing the same.

A circuit such as a counter circuit has a configuration in which a plurality of flip-flops are connected in series. Each flip-flop is sequentially operated from the initial stage in the operation test of this circuit. Thus, it takes a long test time to verify the operation of all the flip-flops.

FIG. 1 is a block diagram showing a circuit configuration of a semiconductor device according to an embodiment;

FIGS. 2A and 2B are circuit diagrams showing a switch circuit according to the embodiment;

FIGS. 3A and 3B are circuit diagrams showing another switch circuit according to the embodiment;

FIGS. 4A and 4B are schematic diagrams showing a circuit operation according to the embodiment;

FIG. 5 is a flow chart showing a manufacturing method of the semiconductor device according to the embodiment;

FIGS. 6A to 6C are schematic views showing the manufacturing method of the semiconductor device according to the embodiment; and

FIGS. 7A and 7B are circuit diagrams showing a switch circuit according to a variation of the embodiment.

According to one embodiment, a method for manufacturing a semiconductor device includes forming a circuit including a plurality of flip-flops, a plurality of first switches, a second switch and a signal line on a wafer, the flip-flops being connected in series through the first switches, respectively, and the signal line being connected to the second switch, and being configured to supply a signal in parallel to the flip-flops; testing the flip-flops by turning off the first switches, turning on the second switch, and supplying a test signal in parallel through the signal line to the flip-flops; and cutting at least one interconnect of a switch portion in the circuit, the switch portion including the first switches and the second switch, so that the first switches are turned on and the second switch is turned off.

Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.

There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward.

FIG. 1 is a block diagram showing a circuit configuration of a semiconductor device according to an embodiment. A circuit shown in FIG. 1 is e.g. an asynchronous counter circuit 1 . The circuit has a configuration in which flip-flops FF 1 -FF N (N: an integer of two or more) are connected in series. Each flip-flop FF has a data input D, a clock input CK, an output Q, and an inverted output QB. The flip-flop FF has a configuration in which the inverted output QB is fed back to the data input D. In the following description, there is a case where the flip-flops FF 1 -FF N are described individually, or collectively referred to as “flip-flop FF”.

As shown in FIG. 1 , a switch SW 1 and a logical sum gate OR are each placed between the flip-flop FF P-1 and the flip-flop FF P (P: an integer of two or more and N or less). The input of the switch SW 1 is connected to the inverted output QB of the flip-flop FF. The output of the switch SW 1 is connected to the input of the logical sum gate OR. The output of the logical sum gate OR is connected to the clock input CK of the flip-flop FF.

The counter circuit 1 further includes a signal line SL connected in parallel to the input of each logical sum gate OR. A signal supplied to the clock input CK of the first stage flip-flop FF 1 is also supplied in parallel by the signal line SL to each clock input CK of the flip-flops FF 2 -FF N through a switch SW 2 .

FIGS. 2A and 2B are circuit diagrams showing the switch circuit SW 1 . FIG. 2A is a circuit diagram showing the switch SW 1 provided on a wafer. FIG. 2B is a circuit diagram showing the switch SW 1 included in a semiconductor device after being divided into chips.

As shown in FIG. 2A , the switch SW 1 includes transistors Tr 1 -Tr 3 , inverters NT 1 and NT 2 . The transistors Tr 1 and Tr 3 are e.g. N-channel MOS (hereinafter NMOS) transistors. The transistor Tr 2 is e.g. a P-channel MOS (hereinafter PMOS) transistor.

The input (IN) of the switch SW 1 is connected to the drains of the transistors Tr 1 and Tr 2 , for example. The output (OUT) of the switch SW 1 is connected to the sources of the transistors Tr 1 and Tr 2 , for example. The output of the switch SW 1 is grounded through the transistor Tr 3 . That is, the transistor Tr 3 has the drain connected to the output of the switch SW 1 , and the source of ground potential.

A gate potential is supplied to the gate of the transistor Tr 1 through the inverters NT 1 and NT 2 . The gate potential is also supplied to each gate of the transistors Tr 2 and Tr 3 through the inverter NT 1 .

As shown in FIG. 2A , the power supply line Vdd is grounded through a resistor R. A potential on the GND side of the resistor R is inputted to the inverter NT 1 . Thus, the potential Low is inputted to the inverter NT 1 . Accordingly, the output potential of the inverter NT 1 is High, and supplied to each gate of the transistors Tr 2 and Tr 3 . Thus, the transistor Tr 2 is turned to the OFF state, and the transistor Tr 3 is turned to the ON state. On the other hand, the output potential High of the inverter NT 1 is inputted to the inverter NT 2 . Thus, the output potential of the inverter NT 2 is Low, and inputted to the gate of the transistor Tr 1 . Thus, the transistor Tr 1 is turned to the OFF state.

Thus, in the wafer state, the input/output path of the switch SW 1 is turned OFF. The output of the switch SW 1 is placed at the GND potential, i.e. Low.

In the example shown in FIG. 2B , the interconnect WR 1 between the resistor R and GND is cut such that a part of the interconnect WR 1 on the resistor R side is connected to the input of the inverter NT 1 . The interconnect WR 1 connected to the input of the inverter NT 1 includes a cut end TM 1 on the resistor R side.

As described later, the interconnect WR 1 is cut in the process for forming the semiconductor device chip. Thus, in the semiconductor device after being diced, the potential High of the power supply line Vdd is inputted to the inverter NT 1 through the resistor R. Accordingly, the output potential of the inverter NT 1 is Low, and supplied to each gate of the transistors Tr 2 and Tr 3 . Then, the transistor Tr 2 is turned to the ON state, and the transistor Tr 3 is turned to the OFF state. Moreover, the output potential of the inverter NT 2 is High, and supplied to the gate of the transistor Tr 1 . Then, the transistor Tr 1 is turned to the ON state. As a result, in the semiconductor device after being diced, the input/output path of the switch SW 1 is in the ON state.

FIGS. 3A and 3B are circuit diagrams showing the switch SW 2 . FIG. 3A is a circuit diagram showing the switch SW 2 provided on a wafer. FIG. 3B is a circuit diagram showing the switch SW 2 included in a semiconductor device after being diced.

As shown in FIGS. 3A and 3B , the switch SW 2 includes transistors Tr 1 -Tr 3 , inverters NT 1 and NT 2 . The switch SW 2 is different from the switch SW 1 shown in FIG. 2A in that the input of the inverter NT 1 is connected to Vdd side of the resistor R.

As shown in FIG. 3A , the potential High of the power supply line Vdd is inputted to the inverter NT 1 of the switch SW 2 . Thus, the output potential of the inverter NT 1 is Low, and supplied to each gate of the transistors Tr 2 and Tr 3 . Then, the transistor Tr 2 is turned to the ON state, and the transistor Tr 3 is turned to the OFF state. Moreover, the output potential of the inverter NT 2 is High, and supplied to the gate of the transistor Tr 1 . Then, the transistor Tr 1 is turned to the ON state. As a result, in the wafer state, the switch SW 2 is in the ON state.

As shown in FIG. 3B , the interconnect WR 2 is cut between the power supply line Vdd and the resistor R. A part of the interconnect WR 2 on the resistor R side is connected to the input of the inverter NT 1 . The part of the interconnect WR 2 connected to the input of the inverter NT 1 includes an end TM 2 on the resistor side.

The interconnect WR 2 is also cut in the process of forming the semiconductor device chip. In the semiconductor device after being diced, the potential Low of GND is inputted to the inverter NT 1 of the switch SW 2 through the resistor R. Accordingly, the output potential of the inverter NT 1 is High, and supplied to each gate of the transistors Tr 2 and Tr 3 . Then, the transistor Tr 2 is turned to the OFF state, and the transistor Tr 3 is turned to the ON state. The output of the switch SW 2 is the GND potential, i.e. Low.

On the other hand, the output potential of the inverter NT 2 is Low, and supplied to the gate of the transistor Tr 1 . Then, the transistor Tr 1 is turned to the OFF state. As a result, in the semiconductor device after being diced, the input/output path of the switch SW 2 is in the OFF state. The output of the switch SW 2 is Low.

FIGS. 4A and 4B are schematic diagrams showing an operation of the counter circuit 1 . FIG. 4A is a block diagram showing the configuration of the counter circuit 1 included in the semiconductor device after being diced. FIG. 4B is a time chart showing the operation of the counter circuit 1 .

As described above, in the semiconductor device after being diced, the switch SW 1 is in the ON state, and the switch SW 2 is in the OFF state. The output of the switch SW 2 is Low, and the input from the signal line SL to the logical sum gate OR is constantly Low. Thus, as shown in FIG. 4A , the counter circuit 1 may be considered to operate in the configuration in which the switches SW 1 , SW 2 , the logical sum gate OR, and the signal line SL are omitted.

FIG. 4B shows a clock signal supplied to the clock input CK of flip-flop FF 1 at the first stage, and outputs Q 1 , Q 2 , Q 3 , QN of the flip-flops FF 1 , FF 2 , FF 3 , FF N . Each flip-flop FF detects e.g. the rising from Low to High of the clock signal supplied to the clock input CK, and inverts the output thereof.

As shown in FIG. 4B , at the rising timing of count 1 of the clock signal, the flip-flop FF 1 at the first stage inverts the output Q 1 thereof from Low to High. Then, the inverted output QB of the flip-flop FF 1 is Low. Thus, the clock input CK of the second stage flip-flop FF 2 is Low, and the output Q 2 thereof is held Low.

Subsequently, at the rising timing of count 2 of the clock signal, the flip-flop FF 1 inverts the output Q 1 thereof from High to Low. At this time, the inverted output QB of the flip-flop FF 1 is turned to High and inputted to the clock input CK of the flip-flop FF 2 at the second stage. Then, the output Q 2 of the flip-flop FF 2 is inverted from Low to High. The inverted output QB of the flip-flop FF 2 is Low. The output Q 3 of the flip-flop FF 3 at the third stage is held Low.

Subsequently, at the rising timing of count 3 of the clock signal, the flip-flop FF 1 at the initial stage inverts the output Q 1 thereof from Low to High. Then, the inverted output QB of the flip-flop FF 1 is inverted from High to Low. However, the output Q 2 of the flip-flop FF 2 at the second stage is held High. Thus, the inverted output QB of the flip-flop FF 2 is Low. The output Q 3 of the third stage flip-flop FF 3 is held Low.

Subsequently, at the rising timing of count 4 of the clock signal, the flip-flop FF 1 at the initial stage inverts the output Q 1 thereof from High to Low. Then, the inverted output QB of the flip-flop FF 1 is inverted from Low to High. The output Q 2 of the flip-flop FF 2 at the second stage is inverted from High to Low. The inverted output QB of the flip-flop FF 2 is inverted from Low to High. According to the inverted output QB of the flip-flop FF 2 , the output Q 3 of the flip-flop FF 3 at the third stage is inverted from Low to High.

Thus, the outputs Q of the flip-flops FF 1 -FF N are sequentially inverted from Low to High. The timing of inverting the output Q of the n-th stage flip-flop FF is 2 n-1 ×Tc seconds later. Here, Tc (seconds) is the clock cycle. For instance, the output Q of the last stage flip-flop FF N is inverted at the timing of 2 N-1 ×Tc seconds later after the first clock count 1 is inputted. Furthermore, it requires 2 N -1 clock counts until the outputs of all the flip-flops FF are inverted from Low to High, and all the output states are verified, which complete at (2 N -1)×Tc seconds later.

For instance, when the counter circuit having the configuration shown in FIG. 4A is formed on a wafer in place of the counter circuit 1 shown in FIG. 1 , the time required to complete the operation test becomes longer as the number of stages increases in the flip-flops FF connected in series. Thus, it takes a longer time in an operation test of the semiconductor device in the wafer state to check the counter circuit. As a result, the throughput time of the manufacturing process may increase significantly.

In contrast, in the counter circuit 1 according to this embodiment, the switch SW 1 is placed to operate each flip-flop FF independently. Thus, the clock signal can be inputted in parallel to the clock input CK of each flip-flop through the signal line SL. Accordingly, the operation test can be completed in a short time irrespective of the number of stages of flip-flops FF.

Furthermore, the interconnects WR 1 and WR 2 of the switches SW 1 and SW 2 are cut in the semiconductor device after being diced. Thus, the switch SW 1 is turned to the ON state, and the switch SW 2 is turned to the OFF state. Thereby, it is possible to achieve the operation similar to that of the simplified circuit shown in FIG. 4A .

Next, a manufacturing method of the semiconductor device according to the embodiment is described with reference to FIGS. 5 to 6C . FIG. 5 is a flow chart showing a method for manufacturing the semiconductor device according to the embodiment. FIGS. 6A to 6C are schematic views showing the method for manufacturing the semiconductor device according to the embodiment.

Step S 01 : An integrated circuit IC including a plurality of flip-flops FF is formed on a wafer 10 . As shown in FIG. 6A , the integrated circuits IC are arranged with a constant pitch in the X-direction and the Y-direction on the front surface of the wafer 10 . Each integrated circuit IC includes a plurality of flip-flops FF, switches SW 1 , SW 2 , a signal line SL, and a logical sum gate OR (see FIG. 1 ).

The plurality of flip-flops FF are connected in series via the switch SW 1 and the logical sum gate OR. The inverted output QB of each flip-flop FF is inputted to the switch SW 1 placed between each flip-flop FF and the flip-flop FF at the next stage. The output of the switch SW 1 is connected to the input of the logical sum gate OR. The output of the logical sum gate OR is connected to the clock input CK of the flip-flop FF at the next stage. A clock signal is inputted by the signal line SL through the switch SW 2 . The signal line SL is connected to the input of each logical sum gate OR. The signal line SL supplies the clock signal in parallel through the logical sum gate OR to the clock input CK of each flip-flop FF.

The integrated circuit IC 1 includes interconnects WR 1 and WR 2 of the switches SW 1 and SW 2 (see FIGS. 2 and 3 ). As shown in FIG. 6B , parts of the interconnects WR 1 and WR 2 is provided in a space 13 between the integrated circuit IC 1 and an integrated circuit IC 2 adjacent thereto.

Step S 02 : The operation test of each integrated circuit IC is performed in the wafer state. At this time, the switch SW 1 is in the OFF state, and the switch SW 2 is in the ON state. A clock signal is inputted to the terminal connected to the clock input CK of the initial stage flip-flop FF 1 to check inversion of the output Q of each flip-flop FF. The clock signal is also supplied in parallel to the flip-flops FF of the second and subsequent stages through the switch SW 2 , the signal line SL, and the logical sum gate OR.

Step S 03 : The wafer 10 is divided into chips each including the integrated circuit IC. For instance, a dicing saw is used to cut the wafer 10 along the space 13 between the adjacent integrated circuits IC. Thereby, each semiconductor device is diced into chip. At this time, as shown in FIG. 6C , parts of the interconnects WR 1 and WR 2 are cut in the switches SW 1 and SW 2 . The ends TM 1 and TM 2 of the interconnects of the switches SW 1 and SW 2 are exposed at the outer edge of each integrated circuit IC diced into chip.

The dicing process of the integrated circuit IC is not limited to the above method. For instance, the wafer 10 may be divided using a dicing saw or a scriber after the part of the space 13 exposed in the wafer 10 is selectively etched. In this case, the interconnects WR 1 and WR 2 are cut by the etching in the wafer 10 .

In the embodiment, it is possible to reduce the time required to complete the operation test, in the wafer state, of the flip-flops FF connected in series. Furthermore, the switches SW 1 and SW 2 can be turned to the ON state and the OFF state, respectively, and thus, the flip-flops FF can operate as intended after being diced without an additional step for cutting the interconnects WR 1 and WR 2 . The integrated circuit IC includes both cut ends of the interconnects WR 1 and WR 2 , and the end surfaces thereof are placed at the outer edge of the integrated circuit IC.

FIGS. 7A and 7B are circuit diagrams showing a switch circuit SC according to a variation of the embodiment. FIG. 7A is the circuit diagram showing the switch circuit SC in a wafer state. FIG. 7B is the circuit diagram showing the switch circuit SC included in a semiconductor device after being diced.

As shown in FIG. 7A , the switch circuit SC includes a plurality of switches SW 1 and a switch SW 2 . The switches SW 1 are placed respectively between flip-flops connected in series. The switch SW 2 is placed between a terminal connected to the clock input CK of the flip-flop FF 1 at the initial stage and a signal line SL.

A gate bias is supplied from a power supply line Vdd through inverters NT 1 , NT 2 , and NT 3 to the gates of transistors Tr 1 , Tr 2 , and Tr 3 included in the switches SW 1 and SW 2 (see FIGS. 2 and 3 ).

As shown in FIG. 7A , potential Low is inputted from the power supply line Vdd side to the inverter NT 1 . The output potential High of the inverter NT 1 is supplied to the gate of the transistors Tr 2 and Tr 3 of each switch SW 1 . Furthermore, according to the output of the inverter NT 1 , the inverter NT 2 outputs potential Low. The output of the inverter NT 2 is supplied to the transistor Tr 1 of each switch SW 1 . Thus, each switch SW 1 is turned to the OFF state, and the output potential thereof is Low.

Furthermore, the output of the inverter NT 2 is inputted to the inverter NT 3 . The inverter NT 3 outputs potential High. The output of the inverter NT 3 is supplied to the gate of the transistor Tr 1 of the switch SW 2 and turns the transistor Tr 1 to the ON state. On the other hand, the output potential Low of the inverter NT 2 is supplied to each gate of the transistors Tr 2 and Tr 3 of the switch SW 2 . Thus, the transistor Tr 2 is turned to the ON state, and the transistor Tr 3 is turned to the OFF state. As a result, the test operation mode of the wafer state is achieved in the counter circuit shown in FIG. 1 .

As shown in FIG. 7B , the semiconductor device after being diced includes an interconnect WR 3 connected to the input of the inverter NT 1 . The interconnect WR 3 is connected between a resistor R and GND. The interconnect WR 3 is cut in the semiconductor device after being diced. A part of the interconnect WR 3 after cutting includes an end TM 3 , and is connected to the input of the inverter NT 1 . A potential High of the power supply line Vdd is supplied to the inverter NT 1 after the interconnect WR 3 is cut. Thus, the output of the inverters NT 1 , NT 2 , and NT 3 is inverted. The switches SW 1 are all turned to the ON state, and the switch SW 2 is turned to the OFF state. Thus, the counter circuit 1 is placed in the normal operation mode.

A part of the interconnect WR 3 is provided in a space 13 between the integrated circuits IC as shown in e.g. FIG. 6B . Thus, without an additional step for cutting the interconnect WR 3 , the counter circuit 1 can be switched from the test operation mode to the normal operation mode. In this example, one counter circuit has one cutting location of the interconnect. Thus, the interconnect WR 3 may be cut by e.g. a method in which the interconnect WR 3 is melted by laser irradiation.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.