Bit-line repeater insertion architecture

The present application claims priority to U.S. Provisional Patent Application No. 62/460,078, filed on Feb. 16, 2017 and incorporates that application by reference in its entirety.

The present invention relates to static random access memory (SRAM) arrays, and more particularly to improving the access time of SRAM arrays with limited bit-cell read current or suffering from transmission line effects prevalent in advanced technology nodes.

Efficient memory design is centered on optimizing the multiplexing scheme of large arrays in the presence of a limited bit-cell current determining the rate of discharge of a bit-line and thus the speed of the SRAM. At nominal operating voltage bit-cell current is always limited by the limitations of any particular technology. Also, the percentage of manufacturing related random and systematic variability increases with every new advanced node. The resistivity and per length capacitance of interconnect have been going up simultaneously with every new technology node, rendering the discharge of bit-lines slower.

Memories are often required to operate significantly below nominal voltage. At sub-nominal supply voltages, the bit-cell read current deteriorates significantly and the impact of higher variability is exacerbated and amplified. Therefore, to keep the density of a memory array high an efficient multiplexing scheme is essential

One prior art method to mitigate limited bit-cell current is through bit-cell current amplification, using a local amplifier connected to a global bit-fine. However, this solution has its own drawbacks as the amplifier input capacitance increases with the amplifier's larger current capabilities rendering the effective gains limited. Furthermore, the length of the global bit-line is still a challenge to be solved.

The present application is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like components, and:

FIG. 1 is a block diagram of a conventional local and global bit-line arrangement for repeater insertions.

FIG. 2 is a block diagram of one embodiment of a bit-line repeater architecture for the repeater insertion on a read bit-line.

FIG. 3 is a flowchart of one embodiment of the process for reading data from the SRAM array with the bit-line repeater global bitline.

FIG. 4 is a block diagram of a SRAM including the drivers and repeaters in a global write line.

A method and apparatus to mitigate limited bit-cell current through the use of repeaters is described. Repeater insertion is a suitable way of dealing with the limited bit-cell current and lengthy transmission line effect of the long bit-lines. The present application discloses a method of inserting and controlling repeaters in a static random access memory (SRAM) at a suitable locations, to break a lengthy bit-line into segments of reasonable size. The resulting SRAM memory, implemented in a multibank architecture, can be used at below nominal voltage at a high density.

FIG. 1 illustrates a simplified multibank architecture for an SRAM. The data output of each of the banks from 101 - 104 is fed to a common global bit-line 155 .

In one embodiment, a one-hot decoding scheme is used in SRAM arrays to select one local bit-line out of multiple lines. People versed in the state of the art are very familiar with this scheme.

Only one bank out of banks 101 - 104 is selected and connected to the global bit-line 155 . In one embodiment, a one-hot decoder 133 activates the appropriate one of the bank select lines from 111 - 114 . The bank select lines 111 to 114 are connected to tristate drivers 141 - 144 .

During use, the one-hot decoder 133 enables one bank select line to 111 to 114 at any one time. This activates the respective tristate driver of 141 - 144 , and connects the respective bank's local bit-line of 121 - 124 to the global bit-line 155 .

The worst-case access time of the memory depends on the length of the global bit-line and on the location of the worst-case driver, which is the farthest driver from the global bit-line. In the embodiment illustrated in FIG. 1 , this is the driver 141 . The delay of the global bit-line increases quadratically with the bit-line length especially for the case where column multiplexing is not available.

FIG. 2 illustrates breaking up the global bitline into multiple segments, to mitigate delays. The global bitline of a conventional SRAM such as the one shown in FIG. 1 , is broken up into segments 251 - 254 , as shown in FIG. 2 .

Segments 251 - 254 of the global bit-line 250 are created by placing repeaters 281 - 284 at break points in the global bit-line 250 . In one embodiment, each repeater 281 - 284 is controlled by the associated inverted bank line select signals, signals 271 - 274 respectively. In one embodiment, the inverted bank line select signals 271 - 274 enable and disable the repeaters 281 - 284 . Therefore, the bank which is selected by the bank select signal can transmit the data on the global bit-line, by selecting its own driver 241 - 244 and at the same time deselecting the repeater 281 - 284 just before it only. All the subsequent repeaters are selected and are active for the connectivity to be complete. The structure thus created can eliminate the need for column multiplexed lines as the repeaters mitigate the quadratic delay effect. This reduces the sense time.

In one embodiment, the repeaters 281 - 284 are tri-state multiplexers. If there are decoders at least one line should always be ON. However, the control may not necessarily come from a decoder. In one embodiment, it can come through a set of word-line registers. These registers may be at a reset value on the onset and may load the decoder output after the first clock. However, in no case the lines will be left in a tri-stated arrangement in a real design.

In one embodiment, the drivers are tri-state drivers, because if the bank is selected it will drive it value on the bit-line. In such case, for a read the bank just above the selected bank must have its driver switched off. This can be done if the drivers are tri-stated.

By this insertion scheme and architecture, there is no need to keep a separate global bit-line, in addition to the global bitline 250 with the repeaters 281 - 284 .

FIG. 3 is a flowchart of one embodiment of the process for reading data from the SRAM array with the bit-line repeater global bitline. The process starts at block 310 .

At block 320 , a read request is received for Bank X of the SRAM. The decoder activates the bank select signal for Bank X, at block 330 .

At block 340 , the bank select signal activates the driver for Bank X, thus enabling data to be read from Bank X. The inverted bank select signal deselects the repeater before Bank X. All other repeaters remain active. Referring to the configuration shown in FIG. 2 , for example, when bank 203 is to be read, decoder 233 activates driver 243 using the bank select line 273 . The repeater 283 is switched off, while all the subsequent repeaters are active (ON state), as the inverse of select lines 211 to 241 of the one-hot decoder 233 , i.e. 271 to 274 selects/deselects them respectively.

Returning to FIG. 3 , at block 360 the data is read from Bank X onto the global bitline, and propagated through the active repeaters, to complete the read operation.

At block 370 , the decoder deactivates the bank select signal. The system is now ready for a next action. The process then ends at block 380 .

FIG. 4 is a block diagram of a SRAM including the drivers and repeaters in a global write line. The repeaters 481 - 484 are activated by write select signal, from decoder 433 . The write drivers 481 - 484 are selected by signals 471 - 474 , which are provided from inverters 461 - 464 by inverting signals 411 - 414 output from the decoder 433 .

For example, when bank 402 is selected for writing, the write drivers from the D port to 483 are all selected by the inverted signal from the decoder 433 , while the driver 482 associated with bank 402 is switched off. Thus the turned off driver ensures that the switching ON the write bit-line is not carried ahead of the repeater 482 associated with the bank 402 selected for writing.

In one embodiment, the configuration of the circuit uses the same decoder as the read embodiment described above, no additional circuit elements are needed to provide the repeater architecture for writing.

Using the same local write bit-line to insert the repeaters removes the need for a global bit-line for both read and write, which results in significant area and capacitance savings.

In one embodiment, the write drivers on the write bit-lines are not multiplexed. The write driver can directly drive any bit-cell connected to the write bit-line. In one embodiment, is not the case for a read bit-line. The read bit-line may be driven by any bit-cell along it. So each stage driver just before the active bank, should be switched off. Thus, in one embodiment, the write bit-line drivers may be disconnected from the decoder as they need no controls.

However, in another embodiment, the write buffers can be tri-stated to save power. When writing to any bank under the topmost bank, the bit-lines above the bank to which the system is writing do not need to be on. By using the decoder, the system can switch off the bank above the bank being written to. Although this arrangement does not save power in the worst-case write (which is writing in the top most bank), it still improves the average dynamic power, assuming only 50% access is in the upper half banks.

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.