Terminal device including reference voltage circuit

This application claims priority from Korean Patent Application No. 10-2017-0091601, filed on Jul. 19, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Methods and apparatuses consistent with example embodiments relate to a semiconductor device, and more particularly, to a terminal device including a reference voltage circuit driven by ultra-low power by using a sub-threshold current.

Applications where energy consumption is a key metric have been developed. Such energy-constrained applications may require low activity rates and low speeds. Also, these applications may require a long battery life span (for example, one year or more). For example, energy consumption may be a concern for a sensor implanted in a living subject and that provides location information.

Location information provided by such a sensor may be provided to a remote device, such as a server over a communication network. The remote device may estimate a location of the living subject based on the location information provided by the sensor. In particular, when the sensor is implanted in an animal, an internal battery may provide driving power and the sensor has to be continually turned-on. Thus, a method of minimizing the driving power of the sensor is required.

According to an aspect of an example embodiment, there is provided reference voltage circuit including a first current bias circuit including a first node; a second current bias circuit comprising a plurality of NMOS transistors and a second node, the plurality of NMOS transistors including a first NMOS transistor and a second NMOS transistor, the first NMOS transistor being connected to the first node, and the plurality of NMOS transistors being connected to the second node and configured to perform a sub-threshold operation based on a first voltage of the first node so that a second voltage is generated at the second node; and an amplifier configured to output a reference voltage having same value as the second voltage.

According to an aspect of another example embodiment, there is provided a terminal device including: a communicator configured to receive a first signal via a wireless communication network and transmit a second signal corresponding to the first signal via the wireless communication network; and a reference voltage circuit configured to be driven by a power voltage, generate a reference voltage and apply the reference voltage to the communicator, the reference voltage circuit including: a first current bias circuit including a first node; a second current bias circuit including a plurality of NMOS transistors and a second node, the plurality of NMOS transistors including a first NMOS transistor and a second NMOS transistor, the first NMOS transistor being connected to the first node, and the plurality of NMOS transistors being connected to the second node and configured to perform a sub-threshold operation according to a first voltage of the first node to generate a second voltage at the second node; and an amplifier configured to output the reference voltage having a same value as the second voltage.

According to an aspect of yet another example embodiment, there is provided an operating method of a terminal device, the operating method including: receiving a first signal with respect to the terminal device; performing a sub-threshold operation of at least two NMOS transistors connected between a power voltage and a ground voltage to generate a reference voltage; generating a second signal corresponding to the first signal based on the reference voltage; and transmitting the second signal.

The above and/or other aspects will become more apparent from the following description of example embodiments taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram for describing a wireless communication system according to an example embodiment;

FIG. 2 is a circuit diagram for describing a reference voltage circuit of FIG. 1 according to an example embodiment;

FIG. 3 is a diagram for modeling a first current of FIG. 2 according to an example embodiment;

FIGS. 4 through 8 are diagrams for describing a general N-channel metal oxide semiconductor (NMOS) transistor according to various example embodiments;

FIG. 9 is a diagram for describing an operation of a second current bias circuit of FIG. 2 according to an example embodiment;

FIG. 10 is a diagram for describing an operation of an amplifier of FIG. 2 according to an example embodiment;

FIG. 11 is a diagram for describing operations of a first current bias circuit and the amplifier of FIG. 2 according to an example embodiment;

FIGS. 12 and 13 are graphs for describing a temperature characteristic of the reference voltage circuit of FIG. 2 according to various example embodiments;

FIGS. 14 through 16 are circuit diagrams of a reference voltage circuit according to various example embodiments; and

FIG. 17 is a diagram for describing an operating method of a terminal device including a reference voltage circuit according to an example embodiment.

FIG. 1 is a block diagram for describing a wireless communication system 100 according to an example embodiment.

Referring to FIG. 1 , the wireless communication system 100 may include a remote device 110 and a terminal device 120 . The wireless communication system 100 may allow the remote device 110 to receive a wireless signal and estimate information from the terminal device 120 .

According to some example embodiments, the terminal device 120 may be implanted in a living subject, that is, a biological life form. The terminal device 120 may provide various information according to its purpose of use. For example, a location of a subject, in which the terminal device 120 is mounted, and bio signals (for example, blood pressure, temperature, changes in thoracic volume due to breathing, etc.) may be sensed and provided as information by the terminal device 120 .

According to example embodiments, the terminal device 120 may also be implanted in a non-living structure (e.g., machines, buildings, etc.). The terminal device 120 may provide information with respect to a state (e.g., a location, a temperature, etc.) of the non-living structure.

The terminal device 120 may transmit a wireless signal to the remote device 110 via a wireless communication network. The wireless communication network may include a cellular communication network 150 using a cell tower 130 and a base station 140 . The cellular communication network 150 may include, for example, at least one of long-term evolution (LTE), LTE-advance (LTE-A), code division multiple access (CDMA), wideband CDMA (WCDMA), a universal mobile telecommunications system (UMTS), wireless broadband (WiBro), and global system for mobile communications (GSM).

The wireless communication network between the terminal device 120 and the remote device 110 may include a short-range wireless communication network. The short-range wireless communication network may include, for example, at least one of wireless fidelity (WiFi), Bluetooth, near-field communication (NFC), and a global navigation satellite system (GNSS). The GNSS may include, for example, at least one of a global positioning system (GPS), a global navigation satellite system (Glonass), a Beidou navigation satellite system, and Galileo, the European global satellite-based navigation system.

The cellular communication network 150 may communicate with the Internet 160 accessing the remote device 110 . The remote device 110 may communicate with the terminal device 120 via a computer network (e.g., a local area network (LAN) or a wide area network (WAN)) or the Internet 160 . Also, the remote device 110 may access a wireless short-range communication network, such as Bluetooth, WiFi, or Zigbee, or a mobile cellular network, such as power line communication (PLC), 3 rd generation (3G), or LTE, and may perform wireless communication with the terminal device 120 . The remote device 110 may receive, via an antenna 116 , the wireless signal transmitted by the terminal device 120 .

The base station 140 may be a fixed station communicating with the terminal device 120 . The base station 140 may communicate with the terminal device 120 or other base stations and exchange various data and control information with the terminal device 120 or the other base stations. The base station 140 may be referred to as evolved-Node B (eNB), a base transceiver system (BTS), an access point, or other terms.

The terminal device 120 may be stationary or mobile and may be any device capable of communicating with the base station 140 to transmit and receive various data and control information. The terminal device 120 may be referred to as a sensor, user equipment (UE), a mobile station (MS), a mobile terminal (MT), a user terminal (UT), a subscribe station (SS), a wireless device, a handheld device, etc.

The remote device 110 may include a processor 112 and a memory 114 . The processor 112 may include one or more of a central processing unit (CPU), an application processor (AP), and a communication processor (CP). The processor 112 may be operationally connected to at least one other component of the remote device 110 and may control general operations of components of the remote device 110 .

The processor 112 may be referred to as a controller, a microcontroller, a microprocessor, a microcomputer, or the like. The processor 112 may be implemented as hardware, firmware, software, or a combination thereof. When the processor 112 is implemented as hardware, the processor 112 may include application specific integrated circuits (ASICs), digital signal processors (DSPs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), etc.

When the processor 112 is implemented as firmware or software, the firmware or the software may be configured to include modules, procedures, functions, etc., performing functions or operations of the processor 112 . The firmware or the software may be installed in the processor 112 or stored in the memory 114 to be driven by the processor 112 .

The memory 114 may temporarily or permanently store various information of the remote device 110 . The memory 114 may store programs for processing or controlling the processor 112 and may store information that is input and output. Also, the memory 114 may be used as a buffer. The memory 114 may be implemented as flash memory, a hard disk, a MultiMediaCardmicro (MMCmicro), a card (for example, an SD card or XD memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, a magnetic disk, an optical disk, or the like.

According to example embodiments, the remote device 110 may operate in connection with a web storage that performs a storage function of the memory 114 on the Internet 160 .

The remote device 110 may process information with respect to the terminal device 120 , based on the wireless signal transmitted by the terminal device 120 . For example, the remote device 110 may obtain a location (or a local location) of the terminal device 120 , and may allow the processor 112 to calculate data with respect to the location and store the calculated data in the memory 114 . Further, the processor may analyze the stored calculated data to estimate a motion of the terminal device 120 .

The terminal device 120 may include an antenna 122 , a power supply 124 , a reference voltage circuit 126 , and an electronic module 128 . The terminal device 120 may perform wireless communication with the cellular communication network 150 in a predetermined manner, via the cell tower 130 and the base station 140 . For example, the terminal device 120 may be triggered to perform data communication with the cellular communication network 150 , based on various triggers. The triggers may include a timer, a real time clock, an event, a trigger signal received from the cellular communication network 150 , etc.

The antenna 122 may be mounted for wireless communication. The antenna 122 may receive information, data, signals, messages, or trigger signals from the outside. The antenna 122 may be referred to as an antenna port. The antenna port may correspond to one physical antenna or may include a combination of a plurality of physical antennas.

The power supply 124 may supply power to the components included in the terminal device 120 . The power supply 124 may include a battery, and the battery may include an embedded battery. For example, the battery may include any one of a lead storage battery, an alkaline battery, a gas cell, a lithium-ion battery, a nickel-hydride battery, a nickel-cadmium cell, a polymer battery, and a lithium polymer battery. However, the battery is not limited thereto.

According to example embodiments, the terminal device 120 may receive solar heat and convert the received solar heat into electrical energy.

The reference voltage circuit 126 may generate a reference voltage V REF by using a band gap of silicon. The terminal device 120 may recognize an external trigger signal based on the reference voltage V REF , and output information thereof to an external device in response to the external trigger signal.

To reduce power consumption, the terminal device 120 may recognize external trigger signals by maintaining a standby state at all times without large power consumption. For example, the terminal device 120 may include an ultra-low-power sensor which requires dozens of microwatts (μW) or a few hundred nanowatts (nW).

The reference voltage circuit 126 may generate the reference voltage V REF based on a sub-threshold operation from among operation models of N-channel metal oxide semiconductor (NMOS) transistors. The reference voltage circuit 126 may include a plurality of NMOS transistors and may be designed such that the NMOS transistors perform a sub-threshold operation. The sub-threshold operation may be performed under a condition in which a gate-source voltage V GS of the NMOS transistors is biased to be lower than a threshold voltage Vth of the NMOS transistors (V GS ≤Vth), and a drain-source voltage V DS of the NMOS transistors is biased to be higher than 0 V (V DS >0).

When the NMOS transistors perform the sub-threshold operation, the sub-threshold operation is performed with a very low voltage and a very low current. Power consumed during the sub-threshold operation of the NMOS transistors is, for example, almost equal to power consumed by normally-off logic gates. Accordingly, the reference voltage circuit 126 may have ultra-low power consumption and may be suitable for use in the terminal device 120 having ultra-low power consumption.

The electronic module 128 may transmit the information of the terminal device 120 to the outside via the antenna 122 , by using the reference voltage V REF generated by the reference voltage circuit 126 . The electronic module 128 may include a wireless communication circuit, such as a mobile chip-set radio frequency (RF) wireless circuit or a cellular radio. The electronic module 128 may establish a link with an external wireless device and transmit and receive information to and from the external wireless device. The electronic module 128 may perform, via the link, a data transmission control operation, such as a timing control operation and an RF control operation, with respect to the external wireless device.

FIG. 2 is a circuit diagram for describing the reference voltage circuit 126 of FIG. 1 according to an example embodiment.

Referring to FIG. 2 , the reference voltage circuit 126 may be driven via a power voltage VDD, which may be provided from the power supply 124 (refer to FIG. 1 ), and may generate a reference voltage V REF having a value substantially the same as a band gap (for example, 1.205 V) of silicon. The reference voltage circuit 126 may include a first current bias circuit 210 , a second current bias circuit 220 , and an amplifier 230 .

The first current bias circuit 210 may use a bipolar transistor Q 1 to generate a first voltage V be according to a first current N bjt . The first current bias circuit 210 may include a PNP bipolar transistor Q 1 and a first P-channel metal oxide semiconductor (PMOS) transistor MP 1 .

Both a base and a collector of the PNP bipolar transistor Q 1 may be connected to a ground voltage VSS, and an emitter of the PNP bipolar transistor Q 1 may be connected to a first node NC 1 so as to form a diode-connected bipolar transistor. The first PMOS transistor MP 1 may include a source, to which a power voltage VDD is connected, a gate, to which a fifth node NA 5 of the second current bias circuit 220 is connected, and a drain, to which the first node NC 1 is connected. The first node NC 1 is connected to the emitter of the PNP bipolar transistor Q 1 and the drain of the PMOS transistor 212 .

An operation of the PNP bipolar transistor Q 1 may be schematically represented by Equation 1 and Equation 2 below.

Here, k is Boltzmann's constant, q is a charge of an electron, T is an operation temperature according to the Kelvin temperature scale, I s is a saturation current, and N bjt is an emitter current.

A forward-biased base-emitter voltage V be of the PNP bipolar transistor Q 1 has a temperature dependent characteristic. That is, the forward-biased base-emitter voltage V be of the PNP bipolar transistor Q 1 has a complementary to absolute temperature (CTAT) voltage characteristic, whereby a voltage decreases as a temperature increases.

In Equation 2, kT/q denotes a thermal voltage V T . The thermal voltage V T increases as a temperature increases. However, the saturation current I s increases by a much greater percentage than the terminal voltage V T , and thus, the base-emitter voltage V be of the PNP bipolar transistor Q 1 may have the CTAT voltage characteristic. The base-emitter voltage V be of the PNP bipolar transistor Q 1 is a voltage of the first node NC 1 of the first current bias circuit 210 and may be provided to the second current bias circuit 220 .

An emitter current of the PNP bipolar transistor Q 1 is the first current N bjt and is the same as a drain current of the first PMOS transistor MP 1 . The drain current of the first PMOS transistor MP 1 may have the same value as an output current I out of the amplifier 230 . That is, the drain current of the first PMOS transistor MP 1 may be determined by receiving a feedback of an operational result of the amplifier 230 . Accordingly, in the first current bias circuit 210 , the first PMOS transistor MP 1 ( FIG. 2 ) may be modelled as a current source 310 corresponding to the first current I bjt , as illustrated in FIG. 3 .

The second current bias circuit 220 of FIG. 2 may include first through third sub-threshold operation circuits 221 through 223 including a plurality of NMOS transistors MN 1 through MN 6 . The second current bias circuit 220 may be designed such that the NMOS transistors MN 1 through MN 6 perform a sub-threshold operation by the base-emitter voltage V be of the PNP bipolar transistor Q 1 , the base-emitter voltage V be being the voltage of the first node NC 1 of the first current bias circuit 210 . Also, the second current bias circuit 220 may be designed such that a voltage obtained as a result of the sub-threshold operation of the NMOS transistors MN 1 through MN 6 has a same value as the reference voltage V REF output by the amplifier 230 .

According to the present example embodiment, it is described that the second current bias circuit 220 includes the three sub-threshold operation circuits 221 through 223 . However, example embodiments are not limited thereto, and the second current bias circuit 220 may include various numbers of sub-threshold operation circuits. For example, the second current bias circuit 220 may include one sub-threshold operation circuit 221 ( FIG. 16 ) or two sub-threshold operation circuits 221 and 222 ( FIG. 15 ).

The first sub-threshold operation circuit 221 may include the first and second NMOS transistors MN 1 and MN 2 connected in series between the power voltage VDD and the ground voltage VSS. The first NMOS transistor MN 1 may include a drain, to which the power voltage VDD is connected, a gate, to which the first node NC 1 of the first current bias circuit 210 is connected, and a source, to which a second node NP 2 is connected. The second NMOS transistor MN 2 may include a gate and a drain, to which the second node NP 2 is connected, and a source, to which the ground voltage VSS is connected.

The base-emitter voltage V be of the PNP bipolar transistor Q 1 of the first node NC 1 may be applied to the gate of the first NMOS transistor MN 1 . Thus, a gate-source voltage V GS of each of the first and second NMOS transistors MN 1 and MN 2 is biased to be lower than a threshold voltage Vth of each of the first and second NMOS transistors MN 1 and MN 2 (V GS ≤Vth). Also, a drain-source voltage V DS of each of the first and second NMOS transistors MN 1 and MN 2 is biased to be higher than 0 V(V DS >0). Accordingly, each of the first and second NMOS transistors MN 1 and MN 2 may perform a sub-threshold operation from among operation models of the NMOS transistors.

The second sub-threshold operation circuit 222 may include the third and fourth NMOS transistors MN 3 and MN 4 connected in series between the power voltage VDD and the ground voltage VSS. The third NMOS transistor MN 3 may include a drain, to which the power voltage VDD is connected, a gate, to which the second node NP 2 is connected, and a source, to which a third node NP 3 is connected. The fourth NMOS transistor MN 4 may include a gate and a drain, to which the third node NP 3 is connected, and a source, to which the ground voltage VSS is connected.

A voltage V PTAT1 of the second node NP 2 may be applied to the gate of the third NMOS transistor MN 3 . The voltage V PTAT1 of the second node NP 2 is lower than the voltage V be of the first node NC 1 inducing the sub-threshold operation of the first and second NMOS transistors MN 1 and MN 2 . Thus, a gate-source voltage V GS of each of the third and fourth NMOS transistors MN 3 and MN 4 is biased to be lower than a threshold voltage Vth of each of the third and fourth NMOS transistors MN 3 and MN 4 (V GS ≤Vth). Also, a drain-source voltage V DS of each of the third and fourth NMOS transistors MN 3 and MN 4 is biased to be higher than 0 V(V DS >0). Accordingly, each of the third and fourth NMOS transistors MN 3 and MN 4 may perform a sub-threshold operation.

The third sub-threshold operation circuit 223 may include the fifth and sixth NMOS transistors MN 5 and MN 6 connected in series. The fifth NMOS transistor MN 5 may include a drain, to which a fifth node NA 5 of the amplifier 230 is connected, a gate, to which the third node NP 3 is connected, and a source, to which a fourth node NP 4 is connected. The sixth NMOS transistor MN 6 may include a gate and a drain, wherein the fourth node NP 4 is connected to the gate and the drain, and a source, to which the ground voltage VSS is connected. The third node NP 3 and the fourth node NP 4 may operate as symmetrical nodes in comparison to a connection structure in the amplifier 230 .

A voltage V PTAT2 of the third node NP 3 may be applied to the gate of the fifth NMOS transistor MN 5 . The voltage V PTAT2 of the third node NP 3 is lower than the voltage V PTAT1 of the second node NP 2 inducing the sub-threshold operation of the third and fourth NMOS transistors MN 3 and MN 4 . Thus, a gate-source voltage V GS of each of the fifth and sixth NMOS transistors MN 5 and MN 6 is biased to be lower than a threshold voltage Vth of each of the fifth and sixth NMOS transistors MN 5 and MN 6 (V GS ≤Vth). Also, a drain-source voltage V DS of each of the fifth and sixth NMOS transistors MN 5 and MN 6 is biased to be higher than 0 V (V DS >0). Accordingly, each of the fifth and sixth NMOS transistors MN 5 and MN 6 may perform a sub-threshold operation.

The amplifier 230 may include second through fourth PMOS transistors MP 2 through MP 4 , seventh and eighth NMOS transistors MN 7 and MN 8 , and a resistor R.

The second PMOS transistor MP 2 may include a source, to which the power voltage VDD is connected, a gate, to which the gate and the drain of the third PMOS transistor MP 3 are connected, and a drain, to which a fifth node NA 5 is connected. The third PMOS transistor MP 3 may include a source, to which the power voltage VDD is connected, and a gate and a drain, which are connected to each other. The second and third PMOS transistors MP 2 and MP 3 may form a current mirror structure. The fourth PMOS transistor MP 4 may include a source, to which the power voltage VDD is connected, a gate, to which the fifth node NA 5 is connected, and a drain, to which the resistor R is connected. A connection node between the fourth PMOS transistor MP 4 and the resistor R may be an output node OUT of the reference voltage circuit 126 and may output the reference voltage V REF .

The seventh NMOS transistor MN 7 may include a drain, to which the gate and the drain of the third PMOS transistor MP 3 are connected, a gate, to which the third node NP 3 is connected, and a source, to which a drain of the eight NMOS transistor MN 8 is connected. The eighth NMOS transistor MN 8 may include the drain, to which the source of the seventh NMOS transistor MN 7 is connected, a gate, to which the output node OUT is connected, and a source, to which the ground voltage VSS is connected.

The voltage V PTAT2 of the third node NP 3 , which is output from the second current bias circuit 220 , is connected to the gate of the seventh NMOS transistor MN 7 in the amplifier 230 , wherein the seventh NMOS transistor MN 7 may be symmetrical to the fifth NMOS transistor MN 5 of the second current bias circuit 220 , the fifth NMOS transistor MN 5 including the gate, to which the voltage V PTAT2 of the third node NP 3 is connected.

When aspect ratios W/L, ratios of widths to lengths, of the second and third PMOS transistors MP 2 and MP 3 forming the current mirror structure are set to be the same, the same current may flow in the second and third PMOS transistors MP 2 and MP 3 . A current of the seventh NMOS transistor MN 7 may be the same as a current of the fifth NMOS transistor MN 5 . Also, a current that is the same as a current of the sixth NMOS transistor connected in series with the fifth NMOS transistor MN 5 may flow in the eighth NMOS transistor MN 8 connected in series with the seventh NMOS transistor MN 7 . Accordingly, a voltage that is the same as the voltage V PTAT3 of the fourth node NP 4 may be developed to the output node OUT connected to the gate of the eighth NMOS transistor MN 8 , and may be output as the reference voltage V REF .

FIGS. 4 through 8 are diagrams for describing a general NMOS transistor according to various example embodiments. FIG. 4 is a diagram for describing a general strong inversion operation from among operation models of the NMOS transistors. FIG. 5 is a diagram for describing a sub-threshold operation of the NMOS transistors. FIGS. 6 through 8 are graphs for describing the sub-threshold operation. In FIGS. 6 through 8 , a horizontal axis indicates a gate-source voltage V Gs of the NMOS transistor and a vertical axis indicates a drain current i D .

Referring to FIG. 4 , when the gate-source voltage V Gs between a gate G and a source S of the NMOS transistor is greater than a threshold voltage Vth of the NMOS transistor, and a drain-source voltage V DS (V DS >0) is applied between a drain D and the source S of the NMOS transistor, a strong inversion layer is formed on a substrate surface p-Si below the gate G to induce a high-conductive n-type channel 401 . Highly-concentrated electrons in the strong inversion layer are drifted from the source S to the drain D, due to an electrical field formed by the drain-source voltage V DS between the drain D and the source S. Accordingly, a strong inversion drain current i D may flow from the drain D to the source S.

Referring to FIG. 5 , when the gate-source voltage V Gs between the gate G and the source S of the NMOS transistor is equal to or less than the threshold voltage Vth of the NMOS transistor, the high-conductive n-type channel 401 is not formed in the substrate surface p-Si below the gate G. A diffusion flux is formed from the source S to the drain D by the drain-source voltage V DS (V DS >0) between the drain D and the source S, and thus, a few number of electrons 501 in the source S may overcome a barrier and may be diffused to the drain D. In this case, the electrons are not affected by the drain-source voltage V DS until the electrons reach an edge of a depletion area 502 . Accordingly, a sub-threshold drain current i D of a very small magnitude flows from the drain D to the source S.

Referring to FIG. 6 , the drain current i D , which flows until the gate-source voltage V GS between the gate G and the source S reaches the threshold voltage Vth of the NMOS transistor, corresponds to the sub-threshold drain current i D , which is almost zero, as described in FIG. 5 . When the gate-source voltage V GS is greater than the threshold voltage Vth, the drain current I D corresponds to the strong inversion drain current I D which has a large magnitude and quickly flows, as described in FIG. 4 .

Referring to FIG. 7 , the gate-source voltage V GS of FIG. 6 has magnified the drain current i D approximate to the threshold voltage Vth by 100 times. FIG. 7 shows a flow of the sub-threshold drain current I D of a very small magnitude, rather than the sub-threshold drain current I D equal to 0.

Referring to FIG. 8 , the drain current i D of FIG. 7 is altered according to a log scale. FIG. 8 shows that the sub-threshold drain current I D has linearity having a predetermined gradient.

The sub-threshold drain current i D of the NMOS transistor, described in FIGS. 4 through 8 , may be represented via Equation 3.

Here, W and L denote a width and a length of a channel of the NMOS transistor, respectively, μ n denotes an electron mobility, C ox denotes a gate capacitance, m denotes a sub-threshold gradient (=(1+Cd/Cox)), Cd denotes a drain capacitance, V T denotes a thermal voltage (=kT/q), q denotes a charge of an electron, k denotes Boltzmann's constant, and T denotes an operation temperature in the Kelvin temperature scale.

In Equation 3, (1−e −qV DS /kT ) is almost 1 due to the drain-source voltage V DS of the NMOS transistor. That is, (1−e −qV DS /kT )≈1 may be used. Accordingly, the sub-threshold drain current i D of the NMOS transistor may be represented by Equation 4.

FIG. 9 is a diagram for describing a detailed operation of the second current bias circuit 220 of FIG. 2 .

Referring to FIG. 9 , each of the first and second NMOS transistors MN 1 and MN 2 of the first sub-threshold operation circuit 221 in the second current bias circuit 220 may, based on the sub-threshold operation of each of the first and second NMOS transistors MN 1 and MN 2 , allow the sub-threshold drain current i D of the NMOS transistor described with reference to FIGS. 4 through 8 to flow.

A drain current i PTAT1 of the first NMOS transistor MN 1 may be obtained based on Equation 5 by substituting a width W 1 and a length L 1 of a channel of the first NMOS transistor MN 1 and the gate-source voltage V GS (=V be −V PTAT1 ) in Equation 4.

The drain current i PTAT1 of the first NMOS transistor MN 1 is the same as a drain current i PTAT1 of the second NMOS transistor MN 2 connected in series with the first NMOS transistor MN 1 . The drain current i PTAT1 of the second NMOS transistor MN 2 may be obtained based on Equation 6 by substituting a width W 2 and a length L 2 of a channel of the second NMOS transistor MN 2 and the gate-source voltage V Gs (=V PTAT1 ) in Equation 4. The voltage V PTAT1 is the voltage of the second node NP 2 .

Equation 7 may be obtained from Equation 5 and Equation 6.

When the voltage V PTAT1 of the second node NP 2 is calculated via Equation 7, Equation 8 is obtained.

It is to be understood that the voltage V PTAT1 of the second node NP 2 depends on the widths W 1 and W 2 and the lengths L 1 and L 2 of the channels of the first and second NMOS transistors MN 1 and MN 2 .

The first NMOS transistor MN 1 performs the sub-threshold operation whereby the gate-source voltage V GS is lower than the threshold voltage Vth of the first NMOS transistor MN 1 . Thus, the voltage V PTAT1 of the second node NP 2 , which is the source of the first NMOS transistor MN 1 , may be lower than the voltage V be of the first node NC 1 , which is the gate of the first NMOS transistor MN 1 , and a difference between the voltage V be of the first node NC 1 and the voltage V PTAT1 of the second node NP 2 may be less than the threshold voltage Vth of the first NMOS transistor MN 1 . The voltage V PTAT1 of the second node NP 2 may be provided to the second sub-threshold operation circuit 222 .

The second sub-threshold operation circuit 222 may include the third and fourth NMOS transistors MN 3 and MN 4 connected in series between the power voltage VDD and the ground voltage VSS. The third NMOS transistor MN 3 may include a drain, to which the power voltage VDD is connected, a gate, to which the second node NP 2 is connected, and a source, to which the third node NP 3 is connected. The fourth NMOS transistor MN 4 may include a gate and a drain, to which the third node NP 3 is connected, and a source, to which the ground voltage VSS is connected.

The voltage V PTAT1 of the second node NP 2 is applied to the gate of the third NMOS transistor MN 3 . The voltage V PTAT1 of the second node NP 2 is lower than the voltage V be of the first node NC 1 inducing the sub-threshold operations of the first and second NMOS transistors MN 1 and MN 2 . Thus, the third and fourth NMOS transistors MN 3 and MN 4 having the same connection structure as the first and second NMOS transistors MN 1 and MN 2 may each perform a sub-threshold operation.

A drain current i PTAT2 of the third NMOS transistor MN 3 may be obtained based on Equation 9, by substituting a width W 3 and a length L 3 of a channel of the third NMOS transistor MN 3 and the gate-source voltage V GS (=V PTAT1 −V PTAT2 ) in Equation 4.

The drain current i PTAT2 of the third NMOS transistor MN 3 is the same as a drain current i PTAT2 of the fourth NMOS transistor MN 4 connected in series with the third NMOS transistor MN 3 . The drain current i PTAT2 of the fourth NMOS transistor MN 4 may be obtained as shown in Equation 10, by substituting a width W 4 and a length L 4 of a channel of the fourth NMOS transistor MN 4 and the gate-source voltage VGS (=V PTAT2 ) to Equation 4. The voltage V PTAT2 is a voltage of the third node NP 3 .

Equation 11 may be obtained from Equation 9 and Equation 10.

Equation 12 may be obtained by calculating the voltage V PTAT2 of the third node NP 3 by substituting the voltage V PTAT1 of Equation 8 in Equation 11.

It is to be understood that the voltage V PTAT2 of the third node NP 3 depends on the widths W 1 and W 2 and the lengths L 1 and L 2 of the channels of the first and second NMOS transistors MN 1 and MN 2 , and the widths W 3 and W 4 and the lengths L 3 and L 4 of the channels of the third and fourth NMOS transistors MN 3 and MN 4 .

The third NMOS transistor MN 3 performs the sub-threshold operation whereby the gate-source voltage V GS is lower than the threshold voltage Vth of the third NMOS transistor MN 3 . Thus, the voltage V PTAT2 of the third node NP 3 , which is the source of the third NMOS transistor MN 3 , may be lower than the voltage V PTAT1 of the second node NP 2 , which is the gate of the third NMOS transistor MN 3 , and a difference between the voltage V PTAT1 of the second node NP 2 and the voltage V PTAT2 of the third node NP 3 may be less than the threshold voltage Vth of the third NMOS transistor MN 3 . The voltage V PTAT2 of the third node NP 3 may be provided to the third sub-threshold operation circuit 223 .

The third sub-threshold operation circuit 223 may include the fifth and sixth NMOS transistors MN 5 and MN 6 connected in series with each other. The fifth NMOS transistor MN 5 may include a drain, to which the fifth node NA 5 of the amplifier 230 is connected, a gate, to which the third node NP 3 is connected, and a source, to which the fourth node NP 4 is connected. The sixth NMOS transistor MN 6 may include a gate and a drain, to which the fourth node NP 4 is connected, and a source, to which the ground voltage VSS is connected.

The voltage V PTAT2 of the third node NP 3 is applied to the gate of the fifth NMOS transistor MN 5 . The voltage V PTAT2 of the third node NP 3 is lower than the voltage V PTAT1 of the second node NP 2 inducing the sub-threshold operations of the third and fourth NMOS transistors MN 3 and MN 4 of the second sub-threshold operation circuit 222 . Thus, the fifth and sixth NMOS transistors MN 5 and MN 6 having the same connection structure as the third and fourth NMOS transistors MN 3 and MN 4 may each perform a sub-threshold operation.

A drain current i PTAT3 of the fifth NMOS transistor MN 5 may be based on in Equation 13 by substituting a width W 5 and a length L 5 of a channel of the fifth NMOS transistor MN 5 and the gate-source voltage V GS (=V PTAT2 −V PTAT3 ) in Equation 4.

The drain current i PTAT3 of the fifth NMOS transistor MN 5 is the same as a drain current i PTAT3 of the sixth NMOS transistor MN 6 connected in series with the fifth NMOS transistor MN 5 . The drain current i PTAT3 of the sixth NMOS transistor MN 6 may be obtained based on Equation 14 by substituting a width W 6 and a length L 6 of a channel of the sixth NMOS transistor MN 6 and the gate-source voltage V Gs (=V PTAT3 ) in Equation 4. The voltage V PTAT3 is a voltage of the fourth node NP 4 .

Equation 15 may be obtained from Equation 13 and Equation 14.

Equation 16 may be obtained by calculating the voltage V PTAT3 of the fourth node NP 4 by substituting the voltage V PTAT2 of Equation 12 in Equation 15.

It is to be understood that the voltage V PTAT3 of the fourth node NP 4 depends on the widths W 1 and W 2 and the lengths L 1 and L 2 of the channels of the first and second NMOS transistors MN 1 and MN 2 , the widths W 3 and W 4 and the lengths L 3 and L 4 of the channels of the third and fourth NMOS transistors MN 3 and MN 4 , and the widths W 5 and W 6 and the lengths L 5 and L 6 of the channels of the fifth and sixth NMOS transistors MN 5 and MN 6 .

The voltage V PTAT1 of the second node NP 2 of Equation 8, the voltage V PTAT2 of the third node NP 3 of Equation 12, and the voltage V PTAT3 of the fourth node P 4 of Equation 16 are respectively correlated with the widths W 1 and W 2 and the lengths L 1 and L 2 of the channels of the first and second NMOS transistors MN 1 and MN 2 , the widths W 3 and W 4 and the lengths L 3 and L 4 of the channels of the third and fourth NMOS transistors MN 3 and MN 4 , and the widths W 5 and W 6 and the lengths L 5 and L 6 of the channels of the fifth and sixth NMOS transistors MN 5 and MN 6 , wherein Equations 8, 12, and 16 may function as referential factors for determining a chip area of the reference voltage circuit 126 to be described with reference to FIGS. 15 and 16 .

FIG. 10 is a diagram for describing an operation of the amplifier 230 of FIG. 2 .

Referring to FIG. 10 , the amplifier 230 may operate in connection with the third sub-threshold operation circuit 223 described in FIG. 9 . It is assumed that the second and third PMOS transistors MP 2 and MP 3 have the same aspect ratios W/L, that is, ratios of widths to lengths, so that the same current flows in the second and third PMOS transistors MP 2 and MP 3 forming the current mirror structure. Also, it is assumed that the fifth and seventh NMOS transistors MN 5 and MN 7 have the same aspect ratios W/L and the sixth and eighth NMOS transistors MN 6 and MN 8 have the same aspect ratios W/L.

The same current flows in the second and third PMOS transistors MP 2 and MP 3 , and the seventh NMOS transistor MN 7 including the gate, to which the voltage V PTAT2 of the third node NP 3 is connected, and the fifth NMOS transistor MN 5 including the gate, to which the voltage V PTAT2 of the third node NP 3 is connected, are symmetrical to each other. A current of the seventh NMOS transistor MN 7 connected in series with the third PMOS transistor MP 3 may be the same as the current I PTAT3 of the fifth NMOS transistor MN 5 connected in series with the second PMOS transistor MP 2 . Also, a current that is the same as the current I PTAT3 of the sixth NMOS transistor MN 6 connected in series with the fifth NMOS transistor MN 5 may flow in the eighth NMOS transistor MN 8 connected in series with the seventh NMOS transistor MN 7 .

A path CP 1 of the current I PTAT3 flowing in the second PMOS transistor MP 2 and the fifth and sixth NMOS transistors MN 5 and MN 6 and a path CP 2 of the current I PTAT3 flowing in the third PMOS transistor MP 3 and the seventh and eighth NMOS transistors MN 7 and MN 8 may have the same structure. Thus, a voltage having the same value as a voltage of the gate of the sixth NMOS transistor may be developed in the gate of the eighth NMOS transistor MN 8 . The output node OUT connected to the gate of the eighth NMOS transistor MN 8 may have a voltage having the same value as the voltage V PTAT3 of the forth node NP 4 , which is the voltage of the gate of the sixth NMOS transistor MN 6 , and the voltage may be output as the reference voltage V REF .

That the output node OUT of the amplifier 230 outputs the voltage V PTAT3 of the fourth node NP 4 of the second current bias circuit 220 connected to a front end of the amplifier 230 denotes that a gain of the amplifier 230 is 1. The voltage V PTAT3 of the fourth node NP 4 may have a very low value that is determined based on the sub-threshold operation of the sixth NMOS transistor MN 6 . The voltage V PTAT3 of the fourth node NP 4 is lower than the voltages V be , V PTAT1 , and V PTAT2 of the first through third nodes NC 1 , NP 2 , and NP 3 , which allow the NMOS transistors MN 1 through MN 6 of the first through third sub-threshold operation circuits 221 through 223 in the second current bias circuit 220 ( FIG. 9 ) to perform the sub-threshold operations. Thus, the amplifier 230 may output the reference voltage V REF having a very low value.

The output current I out flowing in the resistor R by the reference voltage V REF of the output node OUT of the amplifier 230 corresponds to Equation 17.

I OUT =V REF /R   [Equation 17]

The output current I out flowing in the output node OUT of the amplifier 230 may be the same as a current flowing in the fourth PMOS transistor MP 4 connected in series with the resistor R. That is, the output current I out may flow in the fourth PMOS transistor MP 4 .

FIG. 11 is a diagram for describing operations of the first current bias circuit 210 and the amplifier 230 of FIG. 2 .

Referring to FIG. 11 , the output current I out flowing in the fourth PMOS transistor MP 4 of the amplifier 230 may induce the first current I bjt of the first current bias circuit 210 . The fourth PMOS transistor MP 4 may include the source, to which the power voltage VDD is connected, the gate, to which the fifth node NA 5 is connected, and the drain, to which the output node OUT is connected. The first PMOS transistor MP 1 of the first current bias circuit 210 may include the source, to which the power voltage VDD is connected, the gate, to which the fifth node NA 5 is connected, and the drain, to which the emitter of the PNP bipolar transistor Q 1 is connected.

The power voltage VDD is commonly connected to the sources of the first and fourth PMOS transistors MP 1 and MP 4 , and the fifth node NA is commonly connected to the gates of the first and fourth PMOS transistors MP 1 and MP 4 , and thus, the gate-source voltages V GS of the first and fourth PMOS transistors MP 1 and MP 4 may be the same. Accordingly, the output current I out of the fourth PMOS transistor MP 4 may be the same as the current of the first PMOS transistor MP 1 . That is, the first current I bjt of the first current bias circuit 210 , corresponding to the output current I out of the amplifier 230 , may be induced.

As described above, the reference voltage circuit 126 may use the NMOS transistors MN 1 through MN 8 performing the sub-threshold operations, and may generate the reference voltage V REF based on the sub-threshold drain currents of the NMOS transistors MN 1 through MN 8 . Accordingly, the reference voltage circuit 126 consumes a power equal to or less than hundreds of nW, and the reference voltage circuit 126 may be used in the terminal device 120 having ultra-low power consumption.

FIGS. 12 and 13 are graphs for describing a temperature characteristic of the reference voltage circuit 126 of FIG. 2 . A horizontal axis of FIG. 12 denotes Kelvin temperature, and a vertical axis denotes a current. A horizontal axis of FIG. 13 denotes Kelvin temperature and a vertical axis denotes a voltage.

Referring to FIG. 12 , the first current I bjt of the first current bias circuit 210 may have a CTAT current characteristic that is inversely proportional to absolute temperature. The current I PTAT1 of the first sub-threshold operation circuit 221 of the second current bias circuit 220 has a proportional to absolute temperature (PTAT) characteristic that is proportional to absolute temperature. The current I PTAT2 of the second sub-threshold operation circuit 222 is less than the current I PTAT1 of the first sub-threshold operation circuit 221 , and the current I PTAT 3 of the third sub-threshold operation circuit 223 is less than the current I PTAT2 of the second sub-threshold operation circuit 222 .

A point X 1 , at which the first current I bjt of the first current bias circuit 210 meets the current I PTAT1 of the first sub-threshold operation circuit 221 , a point X 2 , at which the first current I bjt of the first current bias circuit 210 meets the current I PTAT2 of the second sub-threshold operation circuit 222 , and a point X 3 , at which the first current I bjt of the first current bias circuit 210 meets the current I PTAT3 of the third sub-threshold operation circuit 223 may be found. Positions of the points X 1 , X 2 , and X 3 in the graph are lowered in this stated order, so that the reference voltage V REF of the reference voltage circuit 126 ( FIG. 2 ) may be determined at the point X 3 , at which the CTAT characteristic graph of the first current I bjt of the first current bias circuit 210 and the PTAT characteristic graph of the current I PTAT3 of the third sub-threshold operation circuit 223 meet. Accordingly, the reference voltage circuit 126 may generate the reference voltage V REF at room temperature of about 300 K, irrespective of a temperature change, as illustrated in FIG. 13 . That is, the reference voltage circuit 126 may generate the reference voltage V REF having low temperature dependence.

FIGS. 14 through 16 are respectively circuit diagrams for describing reference voltage circuits 1400 , 1500 , and 1600 according to example embodiments. The reference voltage circuits 1400 , 1500 , and 1600 of FIGS. 14 through 16 , respectively, correspond to the reference voltage circuit 126 included in the terminal device 120 of FIG. 1 . For convenience, differences from the reference voltage circuit 126 of FIG. 2 will be mainly described below.

The reference voltage circuit 1400 of FIG. 14 differs from the reference voltage circuit 126 of FIG. 2 in that the reference voltage circuit 1400 includes a diode D 1 in a first current bias circuit 1410 . The diode D 1 may include an anode, to which the first node NC 1 is connected, and a cathode, to which the ground voltage VSS is connected. A diode voltage V D of the first node NC 1 may be expressed by Equation 18.

According to Equation 18, a temperature voltage V T increases as a temperature increases, but a saturation current I S increases by a much greater percentage than the temperature voltage V T , and thus, the diode voltage V D has a CTAT voltage characteristic. The diode voltage V D may be a voltage of the first node NC 1 and may be provided to the second current bias circuit 220 . A diode current I D flowing in the first node NC 1 may be a first current, which is the same as the drain current of the first PMOS transistor MP 1 , and may have the same value as the output current I out of the amplifier 230 .

The reference voltage circuit 1500 of FIG. 15 does not include the second sub-threshold operation circuit 222 in the second current bias circuit 220 , unlike the reference voltage circuit 126 of FIG. 2 . The second node NP 2 of the first sub-threshold operation circuit 221 may be connected to the gates of the fifth NMOS transistor MN 5 of the third sub-threshold operation circuit 223 and the seventh NMOS transistor MN 7 of the amplifier 230 .

The reference voltage circuit 1500 may determine the reference voltage V REF at the point X 2 illustrated in FIG. 12 , at which the CTAT characteristic graph of the first current I bjt of the first current bias circuit 210 meets the PTAT characteristic graph of the current I PTAT2 of the second sub-threshold operation circuit 222 . The reference voltage V REF generated by the reference voltage circuit 1500 may correspond to the voltage V PTAT2 of the third node NP 3 described in FIG. 9 .

The reference voltage circuit 1600 of FIG. 16 does not include the second and third sub-threshold operation circuits 222 and 223 in the second current bias circuit 220 , unlike the reference voltage circuit 126 of FIG. 2 . The second node NP 2 of the first sub-threshold operation circuit 221 may be connected to the gate of the seventh NMOS transistor MN 7 of the amplifier 230 , and the drain of the second PMOS transistor MP 2 of the amplifier 230 may be connected to the drain of the first NMOS transistor MN 1 .

The reference voltage circuit 1600 may determine the reference voltage V REF at the point X 1 illustrated in FIG. 12 , at which the CTAT characteristic graph of the first current I bjt of the first current bias circuit 210 meets the PTAT characteristic graph of the current I PTAT1 of the first sub-threshold operation circuit 221 . The reference voltage V REF generated by the reference voltage circuit 1600 may correspond to the voltage V PTAT1 of the second node NP 2 described in FIG. 9 .

The reference voltage circuits 126 , 1500 , and 1600 of FIGS. 2, 15, and 16 , respectively, are correlated with chip areas of the reference voltage circuits in an integrated circuit, in connection with Equations 8, 12, and 16 described above.

The voltage V PTAT1 of the second node NP 2 of Equation 8 depends on the widths W 1 and W 2 and the lengths L 1 and L 2 of the channels of the first and second NMOS transistors MN 1 and MN 2 . The voltage V PTAT2 of the third node NP 3 of Equation 12 depends on the widths W 1 and W 2 and the lengths L 1 and L 2 of the channels of the first and second NMOS transistors MN 1 and MN 2 , and the widths W 3 and W 4 and the lengths L 3 and L 4 of the channels of the third and fourth NMOS transistors MN 3 and MN 4 . The voltage V PTAT3 of the fourth node NP 4 of Equation 16 depends on the widths W 1 and W 2 and the lengths L 1 and L 2 of the channels of the first and second NMOS transistors MN 1 and MN 2 , the widths W 3 and W 4 and the lengths L 3 and L 4 of the channels of the third and fourth NMOS transistors MN 3 and MN 4 , and the widths W 5 and W 6 and the lengths L 5 and L 6 of the channels of the fifth and sixth NMOS transistors MN 5 and MN 6 .

The reference voltage circuit 1600 of FIG. 16 may include one sub-threshold operation circuit 221 , the reference voltage circuit 1500 of FIG. 15 may include two sub-threshold operation circuits 221 and 223 , and the reference voltage circuit 126 of FIG. 2 may include three sub-threshold operation circuits 221 , 222 , and 223 . For example, when it is assumed that a chip area of the reference voltage circuit 1600 of FIG. 16 is about 300 μm 2 , the reference voltage circuit 1500 of FIG. 15 may have a chip area of about 150 μm 2 , and the reference voltage circuit 126 of FIG. 2 may have a chip area of about 100 μm 2 . That is, the reference voltage circuit 126 of FIG. 2 has the least chip area.

As described above, when the number of sub-threshold operation circuits 221 , 222 , and 223 included in each of the reference voltage circuits 126 , 1500 , and 1600 increases, the chip area of the reference voltage circuits 126 , 1500 , and 1600 may decrease. That is, the chip area may be decreased when the large transistors MN 1 and MN 2 of the reference voltage circuit 1600 of FIG. 16 are divided into the plurality of transistors MN 1 through MN 8 as shown in FIG. 2 . However, the number of the sub-threshold operation circuits 221 , 222 , and 223 may be limited according to a target value of the reference voltage V REF .

FIG. 17 is a diagram for describing an operating method of the terminal device 120 including any one of the reference voltage circuits 126 , 1400 , 1500 , and 1600 , according to an example embodiment.

Referring to FIG. 17 , the terminal device 120 may communicate with the remote device 110 via the wireless communication system 100 of FIG. 1 . The remote device 110 may transmit a first signal TRGS to the terminal device 120 . The first signal TRGS may include a timer, a real time clock, an event, a trigger signal, etc., provided from the remote device 110 .

The terminal device 120 may generate the reference voltage V REF by including any one of the reference voltage circuits 126 , 1400 , 1500 , and 1600 described with reference to FIGS. 2 through 16 . The reference voltage circuits 126 , 1400 , 1500 , and 1600 may generate a regular reference voltage V REF by using the NMOS transistors regularly performing sub-threshold operations. The terminal device 120 may receive the first signal TRGS from the electronic module 128 driven by the regular reference voltage V REF . The terminal device 120 may generate a second signal RES in response to the first signal TRGS and transmit the generated second signal RES to the remote device 110 . The second signal RES may correspond to a location of an object, in which the terminal device 120 is mounted, a biometric signal, a status of a structure, or the like.

While example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.