Power supply device, and control method of power supply device

The present application is a Continuation Application of U.S. patent application Ser. No. 14/690,381, filed on Apr. 18, 2015, which is based on Japanese patent application No. 2014-090922, filed on Apr. 25, 2014, the disclosure of which is incorporated herein in its entirety by reference.

The present invention relates to a power supply device and to a control method of a power supply device, for instance a power supply device that converts radio waves to power, and a method for controlling such a power supply device.

Energy harvesting technologies in which radio waves in the surroundings (environmental radio waves) are converted to power have garnered attention in recent years. By resorting to energy harvesting technologies, it becomes possible to dispense with the need for installing batteries in electronic devices, and to improve thus the convenience of electronic devices.

Herein, Japanese Unexamined Patent Application Publication No. H08-79970 discloses a technology pertaining to a device provided with a plurality of power sources, wherein power is supplied simultaneously from each power source to each load, without incurring element malfunction, breakdown or the like. Further, Japanese Unexamined Patent Application Publication No. 2011-30324 discloses a technology pertaining to a power supply device that combines multiple power supply units, the power supply device having high reliability in that the probability that each system malfunctions at the same time is reduced, and there is no instantaneous interruption of power supply.

A power supply device that converts surrounding radio waves to power includes a plurality of power sources each including an antenna and an AC/DC conversion unit that converts, to a DC signal, the AC signal received by the antenna. The DC signals supplied by the plurality of power sources are consolidated in the power supply unit, and a DC signal resulting from consolidation is converted to a predetermined voltage using a voltage conversion circuit. Since the power obtained from one power source is small in energy harvesting technologies where radio waves in the surroundings are converted to power, such technologies involve arranging a plurality of power sources, collecting then, in a power supply unit, the power obtained in the plurality of power sources, and converting thereupon the power to a predetermined voltage using a voltage conversion circuit.

In a power supply device comprising a plurality of power sources and a power supply unit, however, each power source must be connected with the power supply unit using wiring. Accordingly, wiring that connects each power source with the power supply unit is disposed over the entirety of the power supply device, which translates into a greater wiring length in the power supply device. The greater the wiring length in the power supply device, the higher becomes the likelihood that wiring itself functions as an antenna, which has thus an impact on the characteristics of the antennas provided in each power source. A problem arises as a result in that antenna characteristics are impaired and the power obtained from each antenna decreases, and in consequence, the power obtained from the power supply device as a whole decreases likewise.

Other issues and novel features will become apparent on the basis of the disclosure in the description below and accompanying drawings.

In a power supply device according to an embodiment, a plurality of AC signals received by a plurality of antennas undergoes AC/DC conversion to generate a plurality of DC signals, the plurality of DC signals undergoes selective consolidation using first consolidating circuits, a plurality of DC signals output from the first consolidating circuits undergoes selective consolidation using a second consolidating circuit, and a DC signal resulting from consolidation in the second consolidating circuit is converted to a predetermined voltage using a first voltage conversion circuit.

By virtue of the above embodiment, it becomes possible to provide a power supply device in which wiring length can be curtailed, and in which drops in power obtained in the power supply device as a whole can be likewise curtailed, and to provide a control method of such a power supply device.

The above and other aspects, advantages and features will be more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a power supply device according to Embodiment 1;

FIG. 2 is a top-view diagram illustrating a configuration example of a power supply device according to Embodiment 1;

FIG. 3 is a block diagram illustrating a power supply device according to a comparative example;

FIG. 4 is a top-view diagram illustrating a power supply device according to the comparative example;

FIG. 5 is a block diagram illustrating a power supply device according to Embodiment 2;

FIG. 6 is a circuit diagram illustrating an example of an AC/DC conversion unit provided in a power supply device according to Embodiment 2;

FIG. 7 is a circuit diagram illustrating an example of a consolidating unit provided in a power supply device according to Embodiment 2;

FIG. 8 is a circuit diagram illustrating an example of a power supply unit provided in a power supply device according to Embodiment 2;

FIG. 9 is a block diagram illustrating a power supply device according to Embodiment 3;

FIG. 10 is a circuit diagram illustrating an example of a consolidating unit provided in a power supply device according to Embodiment 3;

FIG. 11 is a circuit diagram illustrating an example of a power supply unit provided in a power supply device according to Embodiment 3;

FIG. 12 is a block diagram illustrating a power supply device according to Embodiment 4;

FIG. 13 is a block diagram illustrating a power supply device according to Embodiment 5;

FIG. 14 is a top-view diagram illustrating an example of a power supply device according to Embodiment 6;

FIG. 15 is a top-view diagram illustrating an example of a power supply device according to Embodiment 6;

FIG. 16 is a top-view diagram illustrating an example of a power supply device according to Embodiment 6;

FIG. 17 is a top-view diagram illustrating an example of a power supply device according to Embodiment 6; and

FIG. 18 is a top-view diagram illustrating an example of a power supply device according to Embodiment 6.

Embodiment 1 will be explained next with reference to accompanying drawings. FIG. 1 is a block diagram illustrating a power supply device 1 according to Embodiment 1. As illustrated in FIG. 1 , the power supply device 1 according to the present embodiment includes a plurality of antennas 11 _ 1 to 11 _ n, a plurality of AC/DC conversion units 12 _ 1 to 12 _ n, a plurality of consolidating units 13 _ 1 to 13 _ i, and a power supply unit 15 . Each antenna 11 _ 1 to 11 _ n and each AC/DC conversion unit 12 _ 1 to 12 _ n make up each respective power source 10 . Specifically, FIG. 1 illustrates an instance where there are provided n power sources 10 . An output Vout of the power supply device 1 is supplied to a load circuit 18 .

The antennas 11 _ 1 to 11 _ n receive radio waves of a predetermined frequency band, and output the received signals (i.e. AC signals) to respective AC/DC conversion units 12 _ 1 to 12 _ n . The antennas 11 _ 1 to 11 _ n are configured to be capable of receiving radio waves of a frequency band (i.e. high-energy frequency band) that is often used in the environment where the power supply device 1 is installed. For instance, the antennas 11 _ 1 to 11 _ n are configured to be capable of receiving radio waves in frequency bands of mobile phones, radio waves in frequency bands of wireless LAN, and radio waves in frequency bands of terrestrial digital broadcasting.

The antennas 11 _ 1 to 11 _ n may be configured to receive radio waves of a single frequency band, or to receive radio waves of a plurality of frequency bands. In a case where the antennas 11 _ 1 to 11 _ n are configured to receive radio waves of a plurality of frequency bands, the antennas may be configured in such a manner that for instance a plurality of antennas 11 _ 1 to 11 _ m corresponding to one consolidating unit 13 _ 1 receives radio waves of a plurality of frequency bands. In other words, the antennas may be configured in such a manner that a signal based on radio waves of a plurality of frequency bands is supplied to one consolidating unit 13 _ 1 .

For instance, antennas 11 _ 1 to 11 _ m corresponding to one consolidating unit 13 _ 1 may be configured so as to receive radio waves of a single frequency band, while a plurality of antennas corresponding to another consolidating unit 13 _ 2 may be configured to receive radio waves of a single frequency band (different from that of the antennas 11 _ 1 to 11 _ m ).

In FIG. 1 , m denotes the number of antennas corresponding to the consolidating unit 13 _ 1 , and n denotes the total number of antennas provided in the power supply device 1 . The number of antennas corresponding to each consolidating unit 13 _ 1 to 13 _ i may be identical or different. In order to simplify the explanation hereafter, instances will be described in which the number of antennas corresponding to each consolidating unit 13 _ 1 to 13 _ i is identical (m antennas). In such a case, specifically, the total number of antennas is n=m×i (where i is the number of consolidating units 13 _ 1 to 13 _ i ).

The AC/DC conversion units 12 _ 1 to 12 _ n, which are provided so as to correspond to the antennas 11 _ 1 to 11 _ n, convert the AC signals received by the antennas 11 _ 1 to 11 _ n to respective DC signals, and output DC signals 21 _ 1 to 21 _ n after conversion to the consolidating units 13 _ 1 to 13 _ i.

The plurality of consolidating units 13 _ 1 to 13 _ i has input thereinto the plurality of DC signals 21 _ 1 to 21 _ n supplied by the plurality of power sources 10 (AC/DC conversion units 12 _ 1 to 12 _ n ), and selectively consolidates the input plurality of DC signals 21 _ 1 to 21 _ n. Each consolidating unit 13 _ 1 to 13 _ i includes a respective consolidating circuit 14 _ 1 to 14 _ i (first consolidating circuits). The consolidating circuit 14 _ 1 includes switches SWa_ 1 to SWa_m provided so as to correspond to the AC/DC conversion units 12 _ 1 to 12 _ m. Each switch SWa_ 1 to SWa_m is configured to be capable of switching the connection between each AC/DC conversion unit 12 _ 1 to 12 _ m and an output node 22 _ 1 of the consolidating unit 13 _ 1 .

Specifically, one end of the switch SWa_ 1 is connected to the output side of the AC/DC conversion unit 12 _ 1 , while the other end of the switch SWa_ 1 is connected to the output node 22 _ 1 of the consolidating unit 13 _ 1 . When the switch SWa_ 1 is in an on state, the output side of the AC/DC conversion unit 12 _ 1 and the output node 22 _ 1 of the consolidating unit 13 _ 1 are connected, and a DC signal 21 _ 1 is supplied to the output node 22 _ 1 . When the switch SWa_ 1 is in an off state, on the other hand, the output side of the AC/DC conversion unit 12 _ 1 and the output node 22 _ 1 of the consolidating unit 13 _ 1 are disconnected. In such a case, no DC signal 21 _ 1 is supplied to the output node 22 _ 1 of the consolidating unit 13 _ 1 . The other switches SWa_ 2 to SWa_m are identical to the switch SWa_ 1 .

In a case where, for instance, the voltage of the DC signal 21 _ 1 that is supplied by the AC/DC conversion unit 12 _ 1 is equal to or greater than a predetermined threshold value, the consolidating circuit 14 _ 1 brings the switch SWa_ 1 to an on state, to connect thereby the output side of the AC/DC conversion unit 12 _ 1 and the output node 22 _ 1 of the consolidating unit 13 _ 1 , such that the DC signal 21 _ 1 is supplied to the output node 22 _ 1 . In a case where, on the other hand, the voltage of the DC signal 21 _ 1 that is supplied by the AC/DC conversion unit 12 _ 1 is smaller than a predetermined threshold value, the consolidating circuit 14 _ 1 brings the switch SWa_ 1 to an off state, to disconnect thereby the output side of the AC/DC conversion unit 12 _ 1 from the output node 22 _ 1 of the consolidating unit 13 _ 1 .

By controlling thus the switches SWa_ 1 to SWa_m, the consolidating circuit 14 _ 1 allows consolidating selectively a plurality of DC signals 21 _ 1 to 21 _ m, supplied by the AC/DC conversion units 12 _ 1 to 12 _ m, and outputting a consolidated DC signal to the output node 22 _ 1 . In other words, the consolidating circuit 14 _ 1 allows outputting, to the output node 22 _ 1 , only those DC signals 21 _ 1 to 21 _ m having a voltage that is equal to or greater than predetermined threshold value.

In a case where, for instance, the output side of all the AC/DC conversion units 12 _ 1 to 12 _ m is connected to the output node 22 _ 1 , those AC/DC conversion units that are connected to antennas that receive strong radio waves and AC/DC conversion units that are connected to antennas that receive weak radio waves are connected to the output node 22 _ 1 . In other words, high-output voltage signals of AC/DC conversion units that are connected to antennas that receive strong radio waves, and low-output voltage signals of AC/DC conversion units that are connected to antennas that receive weak radio waves, are connected to the output node 22 .

In such a case, leakage current to ground potential flows ordinarily, in the AC/DC conversion units, in proportion to the output voltage of the AC/DC conversion units. Upon connection, to a high voltage, of the output of AC/DC conversion units that are connected to antennas that receive weak radio waves, a leakage current that is larger than the power obtained from the antenna flows therefore to the AC/DC conversion units, and loss of power is incurred as a result.

In consequence, although obtaining the total sum of power output from the AC/DC conversion units would be the ideal situation, in actuality there can be obtained only power that is smaller, due to the above problem of leakage current, than the power that would be obtained from a single AC/DC conversion unit connected to the antennas that receive strong radio waves.

From the viewpoint of usability of the system as a whole, on the other hand, it would be preferable to use AC/DC conversion units that operate at a high conversion efficiency, also with weak radio waves. However, the greater the number of AC/DC conversion units that operate at a high conversion efficiency, also with weak radio waves, the more decreases the threshold value of the elements that make up the AC/DC conversion unit, and the larger becomes the leakage current. The above problem of leakage current becomes accordingly more pronounced as there increases the number of AC/DC conversion units intended for recovery of very weak radio waves.

In a case where, for instance, radio waves received by the antenna 11 _ 1 are strong, and the radio waves received by the antenna 11 _ 2 are weak (or in a case where no radio waves are received), the voltage of the DC signal 21 _ 1 that is output from the AC/DC conversion unit 12 _ 1 is large, and the voltage of the DC signal 21 _ 2 output from the AC/DC conversion unit 12 _ 2 is small (or zero). In this case, when the AC/DC conversion unit 12 _ 1 and the AC/DC conversion unit 12 _ 2 are connected to the output node 22 _ 1 , leakage current flows from the AC/DC conversion unit 12 _ 1 to the AC/DC conversion unit 12 _ 2 , and the power obtained from the output node 22 _ 1 decreases.

In the present embodiment, therefore, the AC/DC conversion units 12 _ 1 to 12 _ m corresponding to the antennas 11 _ 1 to 11 _ m of weak received radio waves, from among the antennas 11 _ 1 to 11 _ m, are disconnected from the output node 22 _ 1 . It becomes accordingly possible to curtail drops in the power that is obtained from the output node 22 _ 1 .

The configuration of the other consolidating units 13 _ 2 to 13 _ i (consolidating circuits 14 _ 2 to 14 _ i ) is identical to that of the consolidating unit 13 _ 1 (consolidating circuit 14 _ 1 ).

The power supply unit 15 includes a consolidating circuit 16 (second consolidating circuit) and a voltage conversion circuit 17 (first voltage conversion circuit). The consolidating circuit 16 has input thereinto the DC signals (hereafter referred to as DC signals 22 _ 1 to 22 _ i ) output from the respective output nodes 22 _ 1 to 22 _ i of each consolidating unit 13 _ 1 to 13 _ i, and selectively consolidates the input plurality of DC signals 22 _ 1 to 22 _ i. The consolidating circuit 16 includes switches SWb_ 1 to SWb_i provided so as to correspond to the output nodes 22 _ 1 to 22 _ i. Each switch SWb_ 1 to SWb_i is configured to be capable of switching the connection between each output node 22 _ 1 to 22 _ i and an output node 23 of the consolidating circuit 16 . The configuration of the consolidating circuit 16 is basically identical to that of the consolidating circuit 14 _ 1 provided in the consolidating unit 13 _ 1 explained above.

In a case where, for instance, the voltage of the DC signal 22 _ 1 supplied by the consolidating unit 13 _ 1 is equal to or greater than predetermined threshold value, the consolidating circuit 16 brings the switch SWb_ 1 to an on state, whereby the DC signal 22 _ 1 is output to the output node 23 . On the other hand, when the voltage of the DC signal 22 _ 1 that is supplied by the consolidating unit 13 _ 1 is smaller than a predetermined threshold value, the consolidating circuit 16 brings the switch SWb_ 1 to an off state, whereby no DC signal 22 _ 1 is supplied to the output node 23 . The DC signals 22 _ 1 to 22 _ i supplied to the consolidating circuit 16 are DC signals after resulting from consolidation in the consolidating circuits 14 _ 1 to 14 _ i. Accordingly, the predetermined threshold value that serves as the criterion for switching on/off by the consolidating circuit 16 takes on a value higher than the predetermined threshold value that serves as the criterion for switching on/off by the consolidating circuits 14 _ 1 to 14 _ i.

By controlling thus the switches SWb_ 1 to SWb_m, the consolidating circuit 16 allows consolidating selectively the DC signals 22 _ 1 to 22 _ i supplied by the consolidating units 13 _ 1 to 13 _ i, and outputting a consolidated DC signal to the output node 23 . In other words, the consolidating circuit 16 allows outputting, to the output node 23 , only those DC signals 22 _ 1 to 22 _ i having a voltage equal to or greater than a predetermined threshold value.

In a case where, for instance, the DC signal 22 _ 1 supplied by the consolidating unit 13 _ 1 is a signal into which there are consolidated radio waves received by ten antennas, and the DC signal 22 _ 2 supplied by the consolidating unit 13 _ 2 is a signal into which there are consolidated radio waves received by two antennas, then the voltage of the DC signal 22 _ 1 is significantly larger than the voltage of the DC signal 22 _ 2 . When the consolidating unit 13 _ 1 and the consolidating unit 13 _ 2 are connected to the output node 23 in this case, leakage current flows from the consolidating unit 13 _ 1 to the consolidating unit 13 _ 2 , and the power obtained from the output node 23 decreases.

In the present embodiment, therefore, DC signals of low voltage, from among the DC signals 22 _ 1 to 22 _ i supplied by the consolidating units 13 _ 1 to 13 _ i, are disconnected from the output node 23 , to curtail thereby drops in the power obtained from the output node 23 .

The voltage conversion circuit 17 converts the voltage of the DC signal resulting from consolidation in the consolidating circuit 16 (DC signal of the output node 23 , hereafter referred to as DC signal 23 ). For instance, the voltage conversion circuit 17 boosts the DC signal 23 to a predetermined voltage, and outputs a boosted output voltage Vout to the load circuit 18 .

FIG. 2 is a top-view diagram illustrating a configuration example of the power supply device 1 according to the present embodiment. FIG. 2 illustrates an example of the power supply device 1 provided with sixteen antennas, sixteen AC/DC conversion units, and four consolidating unit 13 _ 1 to 13 _ 4 , on a substrate 20 .

The consolidating unit 13 _ 1 consolidates the DC signals output from four power sources (antennas and AC/DC conversion units), and outputs the consolidated DC signal 22 _ 1 to the consolidating circuit 16 of the power supply unit 15 , via wiring 27 _ 1 . The consolidating unit 13 _ 2 consolidates the DC signals output from four power sources, and outputs a consolidated DC signal 22 _ 2 to the consolidating circuit 16 of the power supply unit 15 , via wiring 27 _ 2 . The consolidating unit 13 _ 3 consolidates the DC signals output from four power sources, and outputs a consolidated DC signal 22 _ 3 to the consolidating circuit 16 of the power supply unit 15 , via wiring 27 _ 3 . The consolidating unit 13 _ 4 consolidates the DC signals output from four power sources, and outputs a consolidated DC signal 22 _ 4 to the consolidating circuit 16 of the power supply unit 15 , via wiring 27 _ 4 .

In the power supply device 1 according to the present embodiment, thus DC signals output from a predetermined number of power sources are consolidated in the consolidating units 13 _ 1 to 13 _ 4 , and the consolidated DC signals 22 _ 1 to 22 _ 4 are supplied to the power supply unit 15 . It becomes accordingly possible to curtail the length of wiring in the power supply device.

FIG. 3 is a block diagram illustrating a power supply device 101 in a comparative example. As illustrated in FIG. 3 , the power supply device 101 according to the comparative example includes a plurality of antennas 111 _ 1 to 111 _ n, a plurality of AC/DC conversion units 112 _ 1 to 112 _ n and a power supply unit 115 . The antennas 111 _ 1 to 111 _ n and the AC/DC conversion units 112 _ 1 to 112 _ n make up power sources 110 . An output Vout of the power supply device 101 is supplied to a load circuit 118 . The power supply unit 115 includes a consolidating circuit 116 and a voltage conversion circuit 117 .

The power supply device 101 according to the comparative example illustrated in FIG. 3 differs from the power supply device 1 illustrated in FIG. 1 in that the power supply device 101 lacks the consolidating units 13 _ 1 to 13 _ i. Otherwise, the power supply device 101 is identical to that of the power supply device 1 illustrated in FIG. 1 , and hence recurrent features will not be explained again. In the power supply device 101 according to the comparative example illustrated in FIG. 3 , those constituent elements corresponding to the power supply device 1 illustrated in FIG. 1 are denoted by respective 100-series reference symbols.

FIG. 4 is a top-view diagram illustrating the power supply device 101 according to the comparative example. In FIG. 4 , an example of the power supply device 101 is illustrated wherein the latter includes sixteen antennas and sixteen AC/DC conversion units, on a substrate 120 . In the power supply device 101 according to the comparative example, the DC signal output from each power source (antenna and AC/DC conversion unit) is output directly to the consolidating circuit 116 of the power supply unit 115 , via wiring 127 _ 1 to 127 _ 16 . In the power supply device 101 according to the comparative example, wiring length is thus greater, since each AC/DC conversion unit and the consolidating circuit 116 of the power supply unit 115 must be directly connected via the wiring 127 _ 1 to 127 _ 16 .

When the plurality of AC/DC conversion units and the consolidating circuit 116 of the power supply unit 115 are connected using the wiring 127 _ 1 to 127 _ 16 , the wiring that connects each power source with the power supply unit is disposed over the entirety of the power supply device, and thus the wiring length of the power supply device increases. The greater the wiring length in the power supply device, the higher becomes the likelihood that wiring itself functions as an antenna, which has thus an impact on the characteristics of the antennas provided in each power source. A problem arises as a result in that antenna characteristics are impaired and the power obtained from each antenna decreases, and in consequence, the power obtained from the power supply device as a whole decreases likewise.

In the power supply device 1 according to the present embodiment, therefore, the DC signals that are output from a predetermined number of power sources (sixteen in the case of FIG. 2 ) are consolidated in the consolidating units 13 _ 1 to 13 _ 4 , and the consolidated DC signals 22 _ 1 to 22 _ 4 are supplied to the power supply unit 15 . It becomes accordingly possible to curtail the length of wiring in the power supply device, and, therefore, to suppress drops in the power that is obtained in the power supply device as a whole.

In the present embodiment, each consolidating unit 13 _ 1 to 13 _ 4 and the power supply unit 15 may be configured using semiconductor chips. As illustrated in FIG. 2 , for instance, a plurality of power sources (antennas and AC/DC conversion units), a plurality of consolidating chips (consolidating units) 13 _ 1 to 13 _ 4 and a power source chip (power supply unit) 15 may be disposed on a substrate.

The effect of the power supply device 1 according to the present embodiment will be explained next with reference to a specific example.

In the configuration (comparative example) illustrated in FIG. 3 , for instance, the total wiring length is n×L 1 , where n is the total number of antennas, and L 1 is the wiring distance (average value of wiring distance) between the AC/DC conversion units 112 _ 1 to 112 _ n and the power supply unit 115 .

In the configuration (embodiment) illustrated in FIG. 1 , meanwhile, the total number of antennas is set to n, the number of antennas connected to one consolidating unit 13 _ 1 to 13 _ i is set to m, the wiring distance (average value of wiring distance) between the consolidating units 13 _ 1 to 13 _ i and the power supply unit 15 is set to L 1 , and the wiring distance (average value of wiring distance) between the AC/DC conversion units 12 _ 1 to 12 _ n and the consolidating units 13 _ 1 to 13 _ i is set to L 2 . In the configuration illustrated in FIG. 1 , the consolidating units 13 _ 1 to 13 _ i are disposed close to the AC/DC conversion units 12 _ 1 to 12 _ n. It is assumed herein that the positions at which the consolidating units 13 _ 1 to 13 _ i are disposed are any positions on the substrate, and, accordingly, L 1 in the configuration (comparative example) illustrated in FIG. 3 and L 1 in the configuration (embodiment) illustrated in FIG. 1 are envisaged to be comparable wiring lengths.

In the configuration illustrated in FIG. 1 , accordingly, the total wiring length between the AC/DC conversion units 12 _ 1 to 12 _ n and the consolidating units 13 _ 1 to 13 _ i is n×L 2 , and the total wiring length between the consolidating units 13 _ 1 to 13 _ i and the power supply unit 15 is (n/m)×L 1 (where n/m=i). Therefore, the total wiring length in the configuration illustrated in FIG. 1 is n×L 2 +(n/m)×L 1 .

An example will be explained next of an instance where the size of the substrates 20 , 120 is set to a 50-cm square. In the configuration illustrated in FIG. 3 (comparative example), n=16 and L 1 =25 cm (average wiring length of wiring of all the antennas), and the total wiring length is 400 cm.

In the configuration (embodiment) illustrated in FIG. 1 , by contrast, n=16, L 1 =25 cm, m=4 and L 2 =2 cm, the total wiring length between the AC/DC conversion units 12 _ 1 to 12 _ 16 and the consolidating units 13 _ 1 to 13 _ 4 is 28 cm, and the total wiring length between the consolidating units 13 _ 1 to 13 _ 4 and the power supply unit 15 is 100 cm. Therefore, the total wiring length in the configuration illustrated in FIG. 1 is 128 cm.

In the case of the configuration (embodiment) illustrated in FIG. 1 , accordingly, the total wiring length is reduced by 68% with respect to that in the configuration (comparative example) illustrated in FIG. 3 .

Embodiment 2 will be explained next. FIG. 5 is a block diagram illustrating a power supply device 2 according to Embodiment 2. In the present embodiment there is illustrated a more concrete configuration example of the power supply device explained in Embodiment 1. Those constituent elements in the power supply device 2 , illustrated in FIG. 5 , that are identical to those of the power supply device 1 according to Embodiment 1 illustrated in FIG. 1 will be denoted with identical reference symbols, and will not be explained anew.

As illustrated in FIG. 5 , the power supply device 2 according to the present embodiment includes a plurality of antennas 11 _ 1 to 11 _ n, a plurality of AC/DC conversion units 12 _ 1 to 12 _ n, a plurality of consolidating units 31 _ 1 to 31 _ i and a power supply unit 35 . The antennas 11 _ 1 to 11 _ n are identical to those of in the instance explained in Embodiment 1.

FIG. 6 is a circuit diagram illustrating an example of the AC/DC conversion units 12 (hereafter, the AC/DC conversion units 12 _ 1 to 12 _ n will be referred to collectively as AC/DC conversion unit 12 . The same applies to other constituent elements). As illustrated in FIG. 6 , the AC/DC conversion unit 12 includes a capacitor C 1 , inductors L 1 , L 2 , and a diode D 1 . One end of the capacitor C 1 is connected to an antenna 11 , and the other end is connected to one end of the inductor L 1 and one end of the inductor L 2 . The other end of the inductor L 1 is connected to ground potential. The other end of the inductor L 2 is connected to the anode of the diode D 1 . The cathode of the diode D 1 is connected to a consolidating circuit 32 . That is, the DC signal 21 is output from the cathode of the diode D 1 . The AC/DC conversion unit 12 is configured thus in the form of a T-type matching circuit and half-wave rectifier circuit, such that an input AC signal is converted to a DC signal.

The AC/DC conversion unit 12 illustrated in FIG. 6 is an example. The AC/DC conversion unit 12 in the present embodiment may adopt some other configuration.

As illustrated in FIG. 5 , the consolidating units 31 _ 1 to 31 _ i include respective consolidating circuits 32 _ 1 to 32 _ i, voltage conversion circuits 33 _ 1 to 33 _ i (second voltage conversion circuits) and control circuits 34 _ 1 to 34 _ i (first control circuits). The consolidating circuits 32 _ 1 to 32 _ i have input thereinto the DC signals 21 _ 1 to 21 _ n that are supplied by the AC/DC conversion units 12 _ 1 to 12 _ n, and selectively consolidate the input DC signals 21 _ 1 to 21 _ n . The consolidating circuits 32 _ 1 to 32 _ i have the same configuration as that of the consolidating circuits 14 _ 1 to 14 _ i illustrated in FIG. 1 . Each voltage conversion circuit 33 _ 1 to 33 _ i converts the voltage of the DC signals 22 _ 1 to 22 _ i resulting from consolidation in each respective consolidating circuit 32 _ 1 to 32 _ i. Each control circuit 34 _ 1 to 34 _ i respectively controls each consolidating circuit 32 _ 1 to 32 _ i. Power is supplied by each voltage conversion circuit 33 _ 1 to 33 _ i to each control circuit 34 _ 1 to 34 _ i.

FIG. 7 is a circuit diagram illustrating an example of the consolidating unit 31 _ 1 provided in the power supply device 2 according to the present embodiment. As illustrated in FIG. 7 , the consolidating circuit 32 _ 1 includes switches SWa_ 1 to SWa_m. Each switch SWa_ 1 to SWa_m is configured to be capable of switching the respective connection between each AC/DC conversion unit 12 _ 1 to 12 _ m and the output node 22 _ 1 . The switches SWa_ 1 to SWa_m are controlled using control signals CTRa_ 1 to CTRa_m output from the control circuit 34 _ 1 .

In a case where, for instance, the voltage of the DC signal 21 _ 1 supplied by the AC/DC conversion unit 12 _ 1 is equal to or greater than a predetermined threshold value, the control circuit 34 _ 1 brings the switch SWa_ 1 to an on state, whereby the DC signal 21 _ 1 is output to the output node 22 _ 1 . In a case where, on the other hand, the voltage of the DC signal 21 _ 1 that is supplied by the AC/DC conversion unit 12 _ 1 is smaller than a predetermined threshold value, the control circuit 34 _ 1 brings the switch SWa_ 1 to an off state, to disconnect thereby the output side of the AC/DC conversion unit 12 _ 1 and the output node 22 _ 1 . The same applies to the other switches SWa_ 2 to SWa_m.

The voltage conversion circuit 33 _ 1 converts the DC signal 22 _ 1 , resulting from consolidation in the consolidating circuit 32 _ 1 to 32 _ i, to a predetermined voltage. In the example illustrated in FIG. 7 a configuration is depicted in which the voltage conversion circuit 33 _ 1 is configured in the form of a switched capacitor.

As illustrated in FIG. 7 , the voltage conversion circuit 33 _ 1 includes switches SW 11 to SW 13 , capacitors C 11 , C 12 , and an oscillator circuit OSC 11 . The switch SW 11 switches between connection and non-connection of the output node 22 _ 1 and one end of the capacitor C 11 . The other end of the capacitor C 11 is connected to ground potential. The switch SW 12 switches between connection (“0”) of the one end of the capacitor C 11 and the switch SW 13 , and connection (“1”) of the one end of the capacitor C 11 and one end of the capacitor C 12 . The switch SW 13 switches between connection (“0”) of the switch SW 12 and the other end of the capacitor C 12 , and connection (“1”) of the other end of the capacitor C 12 and ground potential. The oscillator circuit OSC 11 supplies a control clock signal to each switch SW 11 to SW 13 .

The switch SW 11 is brought to an on state (connection state) when the clock signal output from the oscillator circuit OSC 11 takes on a high level (“1”). Thereupon, the one end of the capacitor C 11 and the one end of the capacitor C 12 are connected by the switch SW 12 , and the other end of the capacitor C 12 is connected to ground potential by the switch SW 13 . Accordingly, the capacitor C 11 and the capacitor C 12 are brought to a state of being connected in parallel, such that the capacitor C 11 and the capacitor C 12 are charged by the DC signal 22 _ 1 .

Thereafter, the switch SW 11 is brought to an off state (non-connection state) when the clock signal output from the oscillator circuit OSC 11 takes on a low level (“0”). Thereupon, the one end of the capacitor C 11 and the other end of the capacitor C 12 are connected by the switch SW 12 and the switch SW 13 . Accordingly, the capacitor C 11 and the capacitor C 12 are brought to a state of being connected in series, and boosted voltage is output from an output node C_out of the voltage conversion circuit 33 _ 1 . The voltage conversion circuit 33 _ 1 converts the DC signal 22 _ 1 to predetermined voltage by repeating such an operation. The output (predetermined power source voltage) of the voltage conversion circuit 33 _ 1 is supplied to the control circuit 34 _ 1 .

The power supply unit 35 illustrated in FIG. 5 includes a consolidating circuit 36 , a voltage conversion circuit 37 (first voltage conversion circuit) and a control circuit 38 (second control circuit). The consolidating circuit 36 has input thereinto the DC signals 22 _ 1 to 22 _ i respectively output from each consolidating unit 31 _ 1 to 31 _ i, and selectively consolidates the input DC signals 22 _ 1 to 22 _ i. The consolidating circuit 36 has the same configuration as that of the consolidating circuit 16 illustrated in FIG. 1 . The voltage conversion circuit 37 converts the voltage of the DC signal 23 resulting from consolidation in the consolidating circuit 36 . The control circuit 38 controls the consolidating circuit 36 . Power from the voltage conversion circuit 37 is supplied to the control circuit 38 .

FIG. 8 is a circuit diagram illustrating an example of the power supply unit 35 provided in the power supply device 2 according to the present embodiment. As illustrated in FIG. 8 , the consolidating circuit 36 includes the switches SWb_ 1 to SWb_i. Each switch SWb_ 1 to SWb_i is configured to be capable of switching the connection of the respective output nodes 22 _ 1 to 22 _ i of each consolidating unit 31 _ 1 to 31 _ i and the output node 23 of the consolidating circuit 36 . The switches SWb_ 1 to SWb_i are controlled using control signals CTRb_ 1 to CTRb_i that are output from the control circuit 38 .

In a case where, for instance, the voltage of the DC signal 22 _ 1 supplied by the consolidating unit 13 _ 1 is equal to or greater than predetermined threshold value, the control circuit 38 brings the switch SWb_ 1 to an on state, whereby the DC signal 22 _ 1 is output to the output node 23 . On the other hand, when the voltage of the DC signal 22 _ 1 that is supplied by the consolidating unit 13 _ 1 is smaller than a predetermined threshold value, the control circuit 38 brings the switch SWb_ 1 to an off state, whereby no DC signal 22 _ 1 is supplied to the output node 23 . The same applies to the other switches SWb_ 2 to SWb_i.

The voltage conversion circuit 37 converts the DC signal 23 , resulting from consolidation in the consolidating circuit 36 , to a predetermined voltage. In the example illustrated in FIG. 8 , an instance is depicted in which the voltage conversion circuit 37 is configured in the form of a buck converter.

As illustrated in FIG. 8 , the voltage conversion circuit 37 includes an inductor L 11 , a switch SW 14 , an oscillator circuit OSC 12 and a control circuit 41 . The DC signal 23 output from the consolidating circuit 36 is supplied to one end of the inductor L 11 . The other end of the inductor L 11 is connected to the switch SW 14 . The switch SW 14 connects the other end of the inductor L 11 to ground potential or the output node Vout.

The oscillator circuit OSC 12 supplies a clock signal to the control circuit 41 . The control circuit 41 generates a control signal CTR_sw for controlling the switch SW 14 , using the clock signal supplied by the oscillator circuit OSC 12 . For instance, the control circuit 41 adjusts the pulse width and timing of the control signal CTR_sw, to control thereby the timing at which the switch SW 14 connects the other end of the inductor L 11 to ground potential, and the timing at which the switch SW 14 connects the other end of the inductor L 11 to the output node Vout.

In a case where the control signal CTR_sw is at a high level, the switch SW 14 connects the other end of the inductor L 11 to ground potential. In this case, the DC signal 23 is supplied to the inductor L 11 , and hence current flows in the inductor L 11 . Energy is stored as a result in the inductor L 11 . Thereafter, when the control signal CTR_sw is at a low level, the switch SW 14 connects the other end of the inductor L 11 to the output node Vout. As a result, the energy stored in the inductor L 11 is output to the output node Vout. The output voltage Vout is determined in accordance with the pulse width (duty ratio) of the control signal CTR_sw. The pulse width (duty ratio) of the control signal CTR_sw can be worked out herein by calculating time at high level/(time at high level+time at low level). The output voltage Vout of the voltage conversion circuit 37 rises as the pulse width (duty ratio) of the control signal CTR_sw increases. The output Vout of the voltage conversion circuit 37 is supplied to the control circuit 38 .

An example has been illustrated of an instance where the voltage conversion circuits 33 _ 1 to 33 _ i provided in the consolidating units 31 _ 1 to 31 _ i are made up of switched capacitors, and the voltage conversion circuit 37 provided in the power supply unit 35 is made up of a buck converter, but the circuits that make up the voltage conversion circuits 33 _ 1 to 33 _ i and the voltage conversion circuit 37 are not limited to switched capacitors or a buck converter.

The configuration in the present embodiment may be such that quiescent power in the voltage conversion circuit 33 _ 1 to 33 _ i respectively provided in each consolidating unit 31 _ 1 to 31 _ i is lower than quiescent power in the voltage conversion circuit 37 provided in the power supply unit 35 . The configuration in the present embodiment may be such that the conversion efficiency of the voltage conversion circuit 37 provided in the power supply unit 35 is higher than the conversion efficiency of the voltage conversion circuit 33 _ 1 to 33 _ i respectively provided in each consolidating unit 31 _ 1 to 31 _ i.

In the power supply device 2 according to the present embodiment, the voltage conversion circuits 33 _ 1 to 33 _ i respectively provided in each consolidating unit 31 _ 1 to 31 _ i supply power to the control circuits 34 _ 1 to 34 _ i (of small load). The voltage conversion circuit 37 provided in the power supply unit 35 supplies power to the load circuit 18 (of large load). As a result, the oscillator circuit OSC 11 installed in each voltage conversion circuit 33 _ 1 to 33 _ i can be made slower than the oscillator circuit OSC 12 installed in the voltage conversion circuit 37 . Quiescent power in the voltage conversion circuits 33 _ 1 to 33 _ i can accordingly be made smaller than quiescent power in the voltage conversion circuit 37 .

In order to enhance conversion efficiency in the voltage conversion circuit 37 , the pulse width and timing of the output pulse (clock signal) of the oscillator circuit OSC 12 are adjusted finely, whereby power consumption increases in proportion. That is, complex timing control, for instance PFM control, PWM control, zero current control or the like is required in order to enhance conversion efficiency. The voltage conversion circuits 33 _ 1 to 33 _ i respectively provided in each consolidating unit 31 _ 1 to 31 _ i use a simple clock signal, and hence although quiescent power in the voltage conversion circuits 33 _ 1 to 33 _ i is low, the conversion efficiency of the voltage conversion circuits 33 _ 1 to 33 _ i is lower than that of the voltage conversion circuit 37 .

In the power supply device 2 according to the present embodiment, DC signals output from a predetermined number of power sources are consolidated at the consolidating units 31 _ 1 to 31 _ i, and the consolidated DC signals 22 _ 1 to 22 _ i are supplied to the power supply unit 35 . It becomes accordingly possible to curtail the length of wiring in the power supply device, and, therefore, to suppress drops in the power that is obtained in the power supply device as a whole.

In another conceivable configuration, supply of power to the consolidating units 31 _ 1 to 31 _ i involves supply of power from the voltage conversion circuit 37 provided in the power supply unit 35 to the consolidating units 31 _ 1 to 31 _ i. However, in a case where power is supplied by the voltage conversion circuit 37 provided in the power supply unit 35 to the consolidating units 31 _ 1 to 31 _ i, wiring is necessary to connect the voltage conversion circuit 37 and each consolidating unit 31 _ 1 to 31 _ i, and the length of wiring in the power supply device increases accordingly, which is problematic.

In the power supply device 2 according to the present embodiment, therefore, the voltage conversion circuits 33 _ 1 to 33 _ i are provided in the consolidating units 31 _ 1 to 31 _ i. The power source wiring, which connects the voltage conversion circuit 37 and each consolidating unit 31 _ 1 to 31 _ i, is rendered accordingly unnecessary, and it becomes possible to curtail lengthening of wiring in the power supply device.

In this case, providing the voltage conversion circuits 33 _ 1 to 33 _ i in the consolidating units 31 _ 1 to 31 _ i results in power consumption proportional thereto, which can conceivably result, in turn, in less power being generated in the power supply device 2 . In the power supply device 2 according to the present embodiment, however, power consumption by the voltage conversion circuits 33 _ 1 to 33 _ i of the consolidating units 31 _ 1 to 31 _ i can be kept very small, as explained above, and therefore the power generated in the power supply device 2 is virtually unaffected.

Specifically, various electronic circuits of substantial power consumption are connected, as a load, to the voltage conversion circuit 37 that is provided in the power supply unit 35 . In consequence, a complex circuit with emphasis laid on conversion efficiency is used in the voltage conversion circuit 37 provided in the power supply device 2 . Quiescent power is accordingly large herein.

The control circuits 34 _ 1 to 34 _ i of small power consumption are connected, as a load, to the voltage conversion circuits 33 _ 1 to 33 _ i provided in the consolidating units 31 _ 1 to 31 _ i. It becomes accordingly possible to use circuits that are specialized not in conversion efficiency, but in reducing quiescent power, in the voltage conversion circuits 33 _ 1 to 33 _ i provided in the consolidating units 31 _ 1 to 31 _ i. Quiescent power in the voltage conversion circuits 33 _ 1 to 33 _ i can be reduced as a result. In turn, this allows avoiding drops in the power that is generated in the power supply device 2 .

Embodiment 3 will be explained next. FIG. 9 is a block diagram illustrating a power supply device 3 according to Embodiment 3. The power supply device 3 according to the present embodiment differs from the power supply device 2 explained in Embodiment 2 in that now monitoring circuits 45 _ 1 to 45 _ i are provided in the consolidating units 31 _ 1 to 31 _ i, and a monitoring circuit 46 is provided in the power supply unit 35 . Other features are identical to those of the power supply devices 1 , 2 explained in Embodiments 1 and 2; hence, identical constituent elements will be denoted with identical reference symbols, and recurrent features will not be explained again.

As illustrated in FIG. 9 , the consolidating units 31 _ 1 to 31 _ i provided in the power supply device 3 according to the present embodiment include consolidating circuits 32 _ 1 to 32 _ i, voltage conversion circuits 33 _ 1 to 33 _ i (second voltage conversion circuits), the control circuits 34 _ 1 to 34 _ i (first control circuits) and the monitoring circuits 45 _ 1 to 45 _ i (first monitoring circuits). The consolidating circuits 32 _ 1 to 32 _ i have input thereinto the DC signals 21 _ 1 to 21 _ n supplied by the AC/DC conversion units 12 _ 1 to 12 _ n, and selectively consolidate the input DC signals 21 _ 1 to 21 _ n. The consolidating circuits 32 _ 1 to 32 _ i have the same configuration as that of the consolidating circuits 14 _ 1 to 14 _ i illustrated in FIG. 1 . Each voltage conversion circuit 33 _ 1 to 33 _ i converts the voltage of the DC signals 22 _ 1 to 22 _ i that are consolidated in each consolidating circuit 32 _ 1 to 32 _ i. Each of the monitoring circuits 45 _ 1 to 45 _ i monitors respective DC signals 21 _ 1 to 21 _ n supplied by the AC/DC conversion units 12 _ 1 to 12 _ n. Each control circuit 34 _ 1 to 34 _ i respectively controls each consolidating circuit 32 _ 1 to 32 _ i in accordance with the monitoring result in each of the monitoring circuits 45 _ 1 to 45 _ i. Each voltage conversion circuit 33 _ 1 to 33 _ i supplies power to each respective control circuit 34 _ 1 to 34 _ i and each respective monitoring circuit 45 _ 1 to 45 _ i.

FIG. 10 is a circuit diagram illustrating an example of the consolidating unit 31 _ 1 provided in the power supply device 3 according to the present embodiment. As illustrated in FIG. 10 , the consolidating circuit 32 _ 1 includes switches SWa_ 1 to SWa_m. Each switch SWa_ 1 to SWa_m is configured to be capable of switching the respective connection between each AC/DC conversion unit 12 _ 1 to 12 _ m and the output node 22 _ 1 . The switches SWa_ 1 to SWa_m are controlled using control signals CTRa_ 1 to CTRa_m output from the control circuit 34 .

The voltage conversion circuit 33 _ 1 converts the DC signal 22 _ 1 , resulting from consolidation in the consolidating circuit 32 _ 1 to 32 _ i, to a predetermined voltage. In the example illustrated in FIG. 10 a configuration is depicted in which the voltage conversion circuit 33 _ 1 is configured in the form of a switched capacitor. The same explanation regarding the voltage conversion circuit 33 _ 1 (see FIG. 7 ) explained in Embodiment 2 applies to the voltage conversion circuit 33 _ 1 herein, and a recurrent explanation will be therefore omitted.

The monitoring circuit 45 _ 1 includes a multiplexer MUX 11 , a reference voltage circuit BGR and a comparator CMP 11 . The multiplexer MUX 11 selects any one of DC signals 21 _ 1 to 21 _ m in accordance with a control signal D 1 output from the control circuit 34 _ 1 , and outputs the selected DC signal to one of the inputs of the comparator CMP 11 . The reference voltage circuit BGR generates a predetermined reference voltage Vref (predetermined threshold value), and outputs the generated reference voltage Vref to the other input of the comparator CMP 11 . The comparator CMP 11 compares the reference voltage Vref with the voltage of the DC signal selected by the multiplexer MUX 11 , and outputs the comparison result to the control circuit 34 _ 1 .

The control circuit 34 _ 1 includes an oscillator circuit OSC 13 , a counter CNT 11 , a multiplexer MUX 12 , and flip-flops FF 1 to FFm. The oscillator circuit OSC 13 generates a clock signal, and outputs the generated clock signal to the counter CNT 11 and the flip-flops FF 1 to FFm. The counter CNT 11 generates a counter value in synchrony with the clock signal, and outputs the generated counter value (control signal D 1 ) to the multiplexers MUX 11 , 12 . In accordance with the control signal D 1 , the multiplexer MUX 12 outputs, to any one of the flip-flops FF 1 to FFm, the output of the comparator CMP 11 . In accordance with the clock signal, the flip-flops FF 1 to FFm output a held value (D input value), as the control signals CTRa_ 1 to CTRa_m.

The operation of the monitoring circuit 45 _ 1 and the control circuit 34 _ 1 will be explained next in detail. The multiplexer MUX 11 provided in the monitoring circuit 45 _ 1 selects any one of the DC signals 21 _ 1 to 21 _ m, in accordance with the control signal D 1 , and outputs the selected DC signal to one of the inputs of the comparator CMP 11 . The comparator CMP 11 compares the reference voltage Vref with the voltage of the DC signal selected by the multiplexer MUX 11 , and outputs the comparison result to the multiplexer MUX 12 . In accordance with the control signal D 1 , the multiplexer MUX 12 outputs, to any one of the flip-flops FF 1 to FFm, the output of the comparator CMP 11 .

In a case where, for instance, the DC signal selected by the multiplexer MUX 11 is equal to or greater than the reference voltage Vref, the comparator CMP 11 outputs a high-level signal (“1”), as the comparison result, to the multiplexer MUX 12 . On the other hand, in a case where the DC signal selected by the multiplexer MUX 11 is smaller than the reference voltage Vref, the comparator CMP 11 outputs a low-level signal (“0”), as the comparison result, to the multiplexer MUX 12 .

The control signal D 1 is herein the counter value generated by the counter CNT 11 , and is a value corresponding to each DC signal 21 _ 1 to 21 _ m and each flip-flop FF 1 to FFm. In a case where, for instance, the counter value is “1”, the multiplexer MUX 11 selects the DC signal 21 _ 1 , and the multiplexer MUX 12 outputs the output of the comparator CMP 11 to the flip-flop FF 1 . In a case where the counter value is “2”, the multiplexer MUX 11 selects the DC signal 21 _ 2 , and the multiplexer MUX 12 outputs the output of the comparator CMP 11 to the flip-flop FF 2 . Similarly, in a case where the counter value is “m”, the multiplexer MUX 11 selects the DC signal 21 _ m, and the multiplexer MUX 12 outputs the output of the comparator CMP 11 to the flip-flop FFm. The counter increments the counter value in accordance with the clock signal generated by the oscillator circuit OSC 13 , and resets the counter value once the latter has completed one round (i.e. has counted up to “m”).

In a case where the control signal D 1 is “1”, therefore, the comparator CMP 11 compares the voltage of the DC signal 21 _ 1 and the reference voltage Vref. If the voltage of the DC signal 21 _ 1 is equal to or greater than the reference voltage Vref, the comparator CMP 11 outputs the high-level signal (“1”). Therefore, “1” is held in the flip-flop FF 1 . In this case, the flip-flop FF 1 outputs the high-level signal (“1”) as the control signal CTRa_ 1 , and hence the switch SWa_ 1 of the consolidating circuit 32 _ 1 is brought to an on state (connection state). In a case where, on the other hand, the voltage of the DC signal 21 _ 1 is smaller than the reference voltage Vref, the comparator CMP 11 outputs the low-level signal (“0”), and hence “0” is held in the flip-flop FF 1 . In this case, the flip-flop FF 1 outputs the low-level signal (“0”) as the control signal CTRa_ 1 , and hence the switch SWa_ 1 of the consolidating circuit 32 _ 1 is brought to an off state (non-connection state).

The timing at which the output of the comparator CMP 11 is stored in the flip-flops FF 1 to FFm is the timing of the clock edge of the oscillator circuit OSC 13 . The value of the reference voltage Vref can be set to a value such that, from among the DC signals 21 _ 1 to 21 _ m, only DC signals of sufficiently high voltage are supplied to the output node 22 _ 1 .

The power supply unit 35 illustrated in FIG. 9 includes the consolidating circuit 36 , the voltage conversion circuit (first voltage conversion circuit), the control circuit 38 (second control circuit) and the monitoring circuit 46 (second monitoring circuit). The consolidating circuit 36 has input thereinto the DC signals 22 _ 1 to 22 _ i respectively output from each consolidating unit 31 _ 1 to 31 _ i, and selectively consolidates the input DC signals 22 _ 1 to 22 _ i. The consolidating circuit 36 has the same configuration as that of the consolidating circuit 16 illustrated in FIG. 1 . The voltage conversion circuit 37 converts the voltage of a DC signal 23 resulting from consolidation in the consolidating circuit 36 . The monitoring circuit 46 monitors the DC signals 22 _ 1 to 22 _ i respectively output from each consolidating unit 31 _ 1 to 31 _ i. The control circuit 38 controls the consolidating circuit 36 in accordance with the monitoring result of the monitoring circuit 46 . The voltage conversion circuit 37 supplies power to the control circuit 38 and the monitoring circuit 46 .

FIG. 11 is a circuit diagram illustrating an example of the power supply unit 35 provided in the power supply device 3 according to the present embodiment. As illustrated in FIG. 11 , the consolidating circuit 36 includes switches SWb_ 1 to SWb_i. Each switch SWb_ 1 to SWb_i is configured to be capable of switching the connection of the respective output nodes 22 _ 1 to 22 _ i of each consolidating unit 31 _ 1 to 31 _ i and the output node 23 of the consolidating circuit 36 . The switches SWb_ 1 to SWb_i are controlled using control signals CTRb_ 1 to CTRb_i that are output from the control circuit 38 .

The voltage conversion circuit 37 converts the DC signal 23 , resulting from consolidation in the consolidating circuit 36 , to a predetermined voltage. In the example illustrated in FIG. 11 , an instance is depicted in which the voltage conversion circuit 37 is configured in the form of a buck converter. The same explanation regarding the voltage conversion circuit 37 (see FIG. 8 ) explained in Embodiment 2 applies to the voltage conversion circuit 37 herein, and a recurrent explanation will be therefore omitted.

The configuration and operation of the control circuit 38 provided in the power supply unit 35 are identical to the configuration and operation of the control circuit 34 _ 1 provided in the consolidating unit 31 _ 1 illustrated in FIG. 10 , and hence a recurrent explanation will be omitted. The configuration and operation of the monitoring circuit 46 provided in the power supply unit 35 are likewise identical to the configuration and operation of the monitoring circuit 45 _ 1 provided in the consolidating unit 31 _ 1 illustrated in FIG. 10 , and hence a recurrent explanation will be omitted.

The DC signals 22 _ 1 to 22 _ i that are supplied to the power supply unit 35 are signals after consolidating in the consolidating units 31 _ 1 to 31 _ i. As a result, the voltage of the DC signals 22 _ 1 to 22 _ i is higher than the voltage of the DC signals 21 _ 1 to 21 _ n that are supplied to the consolidating units 31 _ 1 to 31 _ i. Accordingly, the reference voltage Vref of the comparator provided in the monitoring circuit 46 of the power supply unit 35 is set to a higher value than the reference voltage Vref of the comparator provided in the monitoring circuit 45 _ 1 of the consolidating unit 31 _ 1 .

In the power supply device 3 according to the present embodiment, as explained above, the monitoring circuits 45 _ 1 to 45 _ i are provided, in the consolidating units 31 _ 1 to 31 _ i, to monitor the voltage of the DC signals 21 _ 1 to 21 _ n, such that the consolidating circuits 32 _ 1 to 32 _ i are controlled in accordance with the monitoring result of the monitoring circuits 45 _ 1 to 45 _ i. The monitoring circuit 46 is provided, in the power supply unit 35 , to monitor the voltage of the DC signals 22 _ 1 to 22 _ i, such that the consolidating circuit 36 is controlled in accordance with the monitoring result of the monitoring circuit 46 . Accordingly, the connection state of the switches in the consolidating circuits 32 _ 1 to 32 _ i, 36 can be controlled automatically, also upon changes in the state of the radio waves that are received by the antennas. Power can therefore be generated efficiently.

A configuration has been explained above in which the consolidating units 31 _ 1 to 31 _ i and the power supply unit 35 include the monitoring circuits 45 _ 1 to 45 _ i and the monitoring circuit 46 , respectively. In the present embodiment, however, the monitoring circuits 45 _ 1 to 45 _ i may alternatively be provided in the consolidating units 31 _ 1 to 31 _ i alone, or the monitoring circuit 46 be provided in the power supply unit 35 alone.

Embodiment 4 will be explained next. FIG. 12 is a block diagram illustrating a power supply device 4 according to Embodiment 4. A power supply device 4 according to the present embodiment differs from the power supply device 1 explained in Embodiment 1 in that now each consolidating circuit 52 _ 1 to 52 _ i includes two output nodes 61 H, 61 L, the consolidating circuit 54 of the power supply unit 53 includes two output nodes 62 H, 62 L, and the power supply unit 53 includes two voltage conversion circuits 55 , 56 . Other features are identical to those of the power supply device 1 explained in Embodiment 1, and hence identical constituent elements will be denoted with identical reference symbols, and recurrent features will not be explained again.

As illustrated in FIG. 12 , the power supply device 4 according to the present embodiment includes a plurality of antennas 11 _ 1 to 11 _ n, a plurality of AC/DC conversion units 12 _ 1 to 12 _ n, a plurality of consolidating units 51 _ 1 to 51 _ i and a power supply unit 53 . The antennas 11 _ 1 to 11 _ n and AC/DC conversion units 12 _ 1 to 12 _ n are identical to those explained in Embodiment 1, and hence a recurrent explanation will be omitted herein.

Each consolidating unit 51 _ 1 to 51 _ i has input thereinto the DC signals 21 _ 1 to 21 _ n respectively supplied by each AC/DC conversion unit 12 _ 1 to 12 _ n, and selectively consolidates the input DC signals 21 _ 1 to 21 _ n. Each consolidating unit 51 _ 1 to 51 _ i includes a respective consolidating circuit 52 _ 1 to 52 _ i. The consolidating circuit 52 _ 1 includes switches SWa_ 1 to SWa_m provided so as to correspond to the AC/DC conversion units 12 _ 1 to 12 _ m. Each switch SWc_ 1 to SWc_m is configured to be capable of switching between three states, namely a state in which the output side of each AC/DC conversion unit 12 _ 1 to 12 _ m and an output node 61 H_ 1 (first output node) are connected, a state in which the output side of each AC/DC conversion unit 12 _ 1 to 12 _ m and an output node 61 L_ 1 (second output node) are connected, and a state in which the output side of each AC/DC conversion unit 12 _ 1 to 12 _ m is in an open state (i.e. not connected to either the output node 61 H_ 1 or the output node 61 L_ 1 ).

In a case where, for instance, the voltage of the DC signal 21 _ 1 supplied by the AC/DC conversion unit 12 _ 1 is equal to or greater than a threshold value Vt 1 (first threshold value), the consolidating circuit 52 _ 1 connects the output side of the AC/DC conversion unit 12 _ 1 and the output node 61 H_ 1 , and the DC signal 21 _ 1 is supplied to the output node 61 H_ 1 . In a case where the voltage of the DC signal 21 _ 1 supplied by the AC/DC conversion unit 12 _ 1 is equal to or greater than a threshold value Vt 2 but smaller than the threshold value Vt 1 , the consolidating circuit 52 _ 1 connects the output side of the AC/DC conversion unit 12 _ 1 and the output node 61 L_ 1 , and the DC signal 21 _ 1 is supplied to the output node 61 L_ 1 . In a case where the voltage of the DC signal 21 _ 1 supplied by the AC/DC conversion unit 12 _ 1 is smaller than the threshold value Vt 2 , the consolidating circuit 52 _ 1 brings on a state where the output side of the AC/DC conversion unit 12 _ 1 is open. The threshold values Vt 1 and Vt 2 obey the relationship 0<Vt 2 <Vt 1 .

By controlling thus the switches SWc_ 1 to SWc_m, the consolidating circuit 52 _ 1 selectively consolidates the plurality of DC signals 21 _ 1 to 21 _ m supplied by the AC/DC conversion units 12 _ 1 to 12 _ m to either one of the two output nodes 61 H_ 1 , 61 L_ 1 . The same applies to the other consolidating units 51 _ 2 to 51 _ i (consolidating circuits 51 _ 2 to 51 _ i ).

In a case where antennas that receive strong radio waves are mixed with antennas that receive weak radio waves (radio waves which, although non-zero, are extremely weak), from among the plurality of antennas 11 _ 1 to 11 _ n, the AC/DC conversion units connected to antennas that receive weak radio waves are disconnected in the power supply device 1 according to Embodiment 1. Doing so makes it possible to suppress the flow of leakage current into the AC/DC conversion units connected to antennas that receive weak radio waves, and to curtail drops in the power generated in the power supply device 1 .

In such a case, however, a state is brought about in which the power recovered in antennas that receive weak radio waves is wasted. In the present embodiment, accordingly, there are provided two nodes, namely the high voltage-side output node 61 H_ 1 and the low voltage-side output node 61 L_ 1 , as the output node of the consolidating circuit 52 _ 1 , such that the supply destination of the DC signals 21 _ 1 to 21 _ n is switched in accordance with the voltage the DC signals 21 _ 1 to 21 _ n that are supplied by the AC/DC conversion units 12 _ 1 to 12 _ n.

In a case where, for instance, the voltage of the DC signals 21 _ 1 to 21 _ n is high (equal to or greater than the threshold value Vt 1 ), the DC signals 21 _ 1 to 21 _ n are supplied to the high voltage-side output node 61 H_ 1 . In a case where the voltage of the DC signals 21 _ 1 to 21 _ n is low (equal to or greater than the threshold value Vt 2 but smaller than the threshold value Vt 1 ), the DC signals 21 _ 1 to 21 _ n are supplied to the low voltage-side output node 61 L_ 1 . In a case where the voltage of the DC signals 21 _ 1 to 21 _ n is substantially equal to zero (smaller than the threshold value Vt 2 ), the DC signals 21 _ 1 to 21 _ n are not supplied to either the output node 61 H_ 1 or the output node 61 L_ 1 . By doing so, it becomes possible to utilize effectively power that is recovered in antennas that receive weak radio waves, while suppressing flow of leakage current into the AC/DC conversion units.

The power supply unit 53 includes the consolidating circuit 54 and the voltage conversion circuits 55 , 56 . The consolidating circuit 54 includes switches SWH_ 1 to SWH_i that are provided so as to correspond to the output nodes 61 H_ 1 to 61 H_i, on the high potential side, of the consolidating units 51 _ 1 to 51 _ i, and switches SWL_ 1 to SWL_i that are provided so as to correspond to the output nodes 61 L_ 1 to 61 L_i, on the low potential side, of the consolidating units 51 _ 1 to 51 _ i.

Each switch SWH_ 1 to SWH_i is configured to be capable of switching between three states, namely a state in which the output nodes 61 H_ 1 to 61 H_i and the output node 62 H (third output node) are connected, a state in which the respective output nodes 61 H_ 1 to 61 H_i and the output node 62 L (fourth output node) are connected, and a state in which each output node 61 H_ 1 to 61 H_i is in an open state (i.e. not connected to either the output node 62 H or the output node 62 L).

Similarly, each switch SWL_ 1 to SWL_i is configured to be capable of switching between three states, namely a state in which the output nodes 61 L_ 1 to 61 L_i and the output node 62 H (third output node) are connected, a state in which the output nodes 61 L_ 1 to 61 L_i and the output node 62 L (fourth output node) are connected, and a state in which each output node 61 L_ 1 to 61 L_i is in an open state (i.e. not connected to either the output node 62 H or the output node 62 L).

For instance, the switch SWH_ 1 of the consolidating circuit 54 supplies the DC signal 61 H_ 1 to the output node 62 H in a case where the voltage of the DC signal 61 H_ 1 supplied by the consolidating unit 51 _ 1 is equal to or greater than a threshold value Vt 3 (second threshold value). The switch SWH_ 1 supplies the DC signal 61 H_ 1 to the output node 62 L in a case where the voltage of the DC signal 61 H_ 1 supplied by the consolidating unit 51 _ 1 is equal to or greater than a threshold value Vt 4 and smaller than the threshold value Vt 3 . In a case where the voltage of the DC signal 61 H_ 1 supplied by the consolidating unit 51 _ 1 is smaller than the threshold value Vt 4 , the switch SWH_ 1 does not supply the DC signal 61 H_ 1 to either the output node 62 H or the output node 62 L. The threshold values Vt 3 and Vt 4 obey 0<Vt 4 <Vt 3 . The same applies to the other switches SWH_ 2 to SWH_i.

In a case where, for instance, the voltage in the DC signal 61 L_ 1 supplied by the consolidating unit 51 _ 1 is equal to or greater than the threshold value Vt 3 , the switch SWL_ 1 of the consolidating circuit 54 supplies the DC signal 61 L_ 1 to the output node 62 H. The switch SWL_ 1 supplies the DC signal 61 L_ 1 of the output node 62 L in a case where the voltage of the voltage of the DC signal 61 L_ 1 supplied by the consolidating unit 51 _ 1 is equal to or greater than the threshold value Vt 4 and smaller than the threshold value Vt 3 . In a case where the voltage of the DC signal 61 L_ 1 supplied by the consolidating unit 51 _ 1 is smaller than the threshold value Vt 4 , the switch SWL_ 1 does not supply the DC signal 61 L_ 1 to either the output node 62 H or the output node 62 L. The same applies to the other switches SWL_ 2 to SWL_i.

The voltage conversion circuit 55 converts the voltage of the DC signal (DC signal of the output node 62 H, hereafter notated as DC signal 62 H) resulting from consolidation in the consolidating circuit 54 . Specifically, the voltage conversion circuit 55 boosts the DC signal 62 H to a predetermined voltage, and outputs the boosted output voltage Vout to the load circuit 18 .

The voltage conversion circuit 56 converts the voltage of the DC signal (DC signal of the output node 62 L, hereafter notated as DC signal 62 L) resulting from consolidation in the consolidating circuit 54 . Specifically, the voltage conversion circuit 56 boosts the DC signal 62 L to a predetermined voltage, and outputs the boosted output voltage Vout to the load circuit 18 . In this case, the voltage conversion circuit 56 boosts the signals to a voltage comparable to the output voltage Vout of the voltage conversion circuit 55 . Specifically, the voltage of the DC signal 62 L is lower than the voltage of the DC signal 62 H, and hence the boost width of the voltage conversion circuit 56 is larger than the boost width of the voltage conversion circuit 55 .

In the power supply device 4 according to the present embodiment, as explained above, two output nodes 61 H, 61 L are provided in each consolidating circuit 52 _ 1 to 52 _ i, two output nodes 62 H, 62 L are provided in the consolidating circuit 54 of the power supply unit 53 , and two voltage conversion circuits 55 , 56 are provided in the power supply unit 53 . It becomes accordingly possible to utilize effectively power that is recovered in antennas that receive weak radio waves, while suppressing flow of leakage current into the AC/DC conversion units.

Features pertaining to Embodiments 2 and 3 explained above may be applied to the power supply device 4 according to the present embodiment.

Embodiment 5 will be explained next. FIG. 13 is a block diagram illustrating a power supply device 5 according to Embodiment 5. The power supply device 5 according to the present embodiment differs from the power supply device 1 explained in Embodiment 1 in that now consolidating units 65 are further provided between the consolidating units 13 and the power supply unit 15 . Other features are identical to those of the power supply device 1 explained in Embodiment 1, and hence identical constituent elements will be denoted with identical reference symbols, and recurrent features will not be explained again.

As illustrated in FIG. 13 , the power supply device 5 according to the present embodiment includes a plurality of antennas 11 , a plurality of AC/DC conversion units 12 , first-stage consolidating units 13 (first consolidating circuits), second-stage consolidating units 65 (third consolidating circuits) and a power supply unit 15 . The antennas 11 and the AC/DC conversion units 12 are identical to those of the instance explained in Embodiment 1, and hence a recurrent explanation will be omitted herein.

Each consolidating unit 13 has input thereinto a plurality of DC signals supplied by respective AC/DC conversion units 12 , and selectively consolidates the input plurality of DC signals. Each consolidating unit 13 includes a consolidating circuit (see FIG. 1 , FIG. 5 ).

Each consolidating unit 65 has input thereinto respective DC signals resulting from consolidation in the consolidating units 13 , and selectively consolidates the input plurality of DC signals. Each consolidating unit 65 includes a consolidating circuit, a voltage conversion circuit and a control circuit. The configuration of each consolidating unit 65 is identical to the configuration of each consolidating unit 13 (see, for instance, consolidating units 31 _ 1 to 31 _ i in FIG. 5 ), and hence a recurrent explanation will be omitted herein. For instance, the power source circuit 5 includes M consolidating units (consolidating circuits) 13 and N (N<M) consolidating units (consolidating circuits) 65 .

The power supply unit 15 includes the consolidating circuit 16 and the voltage conversion circuit 17 . The consolidating circuit 16 has input thereinto the DC signals that are output from each consolidating unit 65 , and selectively consolidates the input plurality of DC signals. The configuration of power supply unit 15 is identical to that of the power supply unit 15 provided in the power supply device 1 according to Embodiment 1, and hence a recurrent explanation will be omitted herein.

In the power supply device 5 according to the present embodiment, the consolidating units 65 are provided between the consolidating units 13 and the power supply unit 15 . It becomes accordingly possible to curtail the length of wiring in the power supply device 5 , even when, for instance, the number of antennas 11 is large.

An instance has been illustrated above wherein the consolidating units (consolidating circuits) have been configured in two stages (consolidating units 13 , consolidating units 65 ), but the consolidating units may be configured in three or more stages. Features pertaining to Embodiments 2 and 4 explained above may be applied to the power supply device 5 according to the present embodiment.

Embodiment 6 will be explained next. In Embodiment 6, a configuration example is illustrated of an instance where the power supply devices 1 to 5 explained in Embodiments 1 to 5 are disposed on substrates.

FIG. 14 is a top-view diagram illustrating an example of a power supply device 6 _ 1 according to Embodiment 6. The power supply device 6 _ 1 illustrated in FIG. 14 includes 48 antennas, 48 AD/DC conversion units, four consolidating units 73 _ 1 to 73 _ 4 , and one power supply unit 75 , on a substrate 70 . The power supply device 6 _ 1 includes three types of antenna 71 _ 1 to 71 _ 3 , and hence can receive radio waves of three types of frequency band. The AC signals received by each antenna are converted to DC signals in respective AC/DC conversion units, and the DC signals after conversion are supplied to respective consolidating units 73 _ 1 to 73 _ 4 . In the power supply device 6 _ 1 illustrated in FIG. 14 , twelve DC signals (output of the AC/DC conversion units) are respectively supplied to each consolidating unit 73 _ 1 to 73 _ 4 . The respective DC signals output from each consolidating unit 73 _ 1 to 73 _ 4 are supplied to the power supply unit 75 .

FIG. 15 is a top-view diagram illustrating an example of a power supply device 6 _ 2 according to Embodiment 6. The power supply device 6 _ 2 illustrated in FIG. 15 includes 48 antennas, 48 AD/DC conversion units, eight consolidating units 81 _ 1 to 81 _ 8 and one power supply unit 82 , on a substrate 80 . The power supply device 6 _ 2 includes three types of antenna, and hence can receive radio waves of three types of frequency band. The AC signals received by each antenna are converted to DC signals in respective AC/DC conversion units, and the DC signals after conversion are supplied to respective consolidating units 81 _ 1 to 81 _ 8 . In the power supply device 6 _ 2 illustrated in FIG. 15 , six DC signals (output of the AC/DC conversion units) are respectively supplied to each consolidating unit 81 _ 1 to 81 _ 8 . The respective DC signals output from each consolidating unit 81 _ 1 to 81 _ 8 are supplied to the power supply unit 82 . In the power supply device 6 _ 2 illustrated in FIG. 15 there are provided eight consolidating units 81 _ 1 to 81 _ 8 , and hence the total wiring length can be shortened with respect to that of the power supply device 6 _ 1 illustrated in FIG. 14 .

FIG. 16 is a top-view diagram illustrating an example of a power supply device 6 _ 3 according to Embodiment 6. The power supply device 6 _ 3 illustrated in FIG. 16 includes eighteen antennas, eighteen AD/DC conversion units, two consolidating unit 86 _ 1 to 86 _ 2 , and one power supply unit 87 , on a substrate 85 . The power supply device 6 _ 3 includes three types of antenna, and hence can receive radio waves of three types of frequency band. The AC signals received by each antenna are converted to DC signals in respective AC/DC conversion units, and the DC signals after conversion are supplied to respective consolidating units 86 _ 1 to 86 _ 2 . In the power supply device 6 _ 3 illustrated in FIG. 16 , nine DC signals (output of the AC/DC conversion units) are respectively supplied to each consolidating unit 86 _ 1 to 86 _ 2 . The respective DC signals output from each consolidating unit 86 _ 1 to 86 _ 2 are supplied to the power supply unit 87 .

FIG. 17 is a top-view diagram illustrating an example of a power supply device 6 _ 4 according to Embodiment 6. The power supply device 6 _ 4 illustrated in FIG. 17 includes eighteen antennas, eighteen AD/DC conversion units, four consolidating units 91 _ 1 to 91 _ 4 , and one power supply unit 92 , on a substrate 90 . The power supply device 6 _ 4 includes three types of antenna, and hence can receive radio waves of three types of frequency band. The AC signals received by each antenna are converted to DC signals in respective AC/DC conversion units, and the DC signals after conversion are supplied to respective consolidating units 91 _ 1 to 91 _ 4 . In the power supply device 6 _ 4 illustrated in FIG. 17 , four or five DC signals (output of the AC/DC conversion units) are respectively supplied to each consolidating unit 91 _ 1 to 91 _ 4 . The respective DC signals output from each consolidating unit 91 _ 1 to 91 _ 4 are supplied to the power supply unit 92 .

FIG. 18 is a top-view diagram illustrating an example of a power supply device 6 _ 5 according to Embodiment 6, and depicting a power supply device (see Embodiment 5) in which the consolidating units are configured over two stages. The power supply device 6 _ 5 illustrated in FIG. 18 includes 96 antennas, 96 AD/DC conversion units, eight consolidating units (first-stage consolidating units) 96 _ 1 to 96 _ 8 , and two consolidating units (second-stage consolidating unit) 97 _ 1 to 97 _ 2 , on a substrate 95 .

The power supply device 6 _ 5 includes three types of antenna, and hence can receive radio waves of three types of frequency band. The AC signals received by each antenna on the substrate 95 are converted to DC signals in respective AC/DC conversion units, and the DC signals after conversion are supplied to respective consolidating units 96 _ 1 to 96 _ 8 . Herein, twelve DC signals (output of the AC/DC conversion units) are respectively supplied to each consolidating unit 96 _ 1 to 96 _ 8 on the substrate 95 . The respective DC signals output from each consolidating unit 96 _ 1 to 96 _ 4 are supplied to the second-stage consolidating unit 97 _ 1 . The respective DC signals output from each consolidating unit 96 _ 5 to 96 _ 8 are supplied to the second-stage consolidating unit 97 _ 2 . The DC signal output from the consolidating unit 97 _ 1 , and the DC signal output from the consolidating unit 97 _ 2 , are supplied to the power supply unit 98 .

In the power supply device 6 _ 5 illustrated in FIG. 18 , the consolidating units are configured over two stages, and hence it becomes possible to curtail the length of wiring in the power supply device 6 _ 5 , even when the number of antennas is large.

The first to sixth embodiments can be combined as desirable by one of ordinary skill in the art.

While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above.

Further, the scope of the claims is not limited by the embodiments described above.

Furthermore, it is noted that, Applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution.