Electrical transformer to transmit data and power

This relates generally to an electrical circuit with a transformer to transmit data and power.

A transformer is an electrical device that transfers electrical energy between two or more circuits through electromagnetic induction. A varying current in one winding (e.g., inductor or coil) of the transformer produces a varying magnetic field, which in turn induces a voltage in a second winding. Power is transferred between the two windings through the magnetic field, without a metallic connection between the two circuits. Transformers may be used to increase or decrease the alternating voltages in electric power applications.

In electronics and telecommunications, modulation is the process of varying one or more properties of a periodic waveform, called the carrier signal, with a modulating signal that typically contains information to be transmitted.

In a first example, a system includes a transformer that includes a primary winding and a secondary winding. The system also includes a primary side circuit coupled to the primary winding of the transformer. The primary side circuit includes a primary controller. The system further includes a secondary side circuit coupled to the secondary winding of the transformer. The primary controller is coupled to cause the primary side circuit to transfer power and intermittently transmit data to the secondary side circuit via the primary winding and the secondary winding of the transformer.

In a second example, a system includes a transformer having a primary winding and a secondary winding and a primary side circuit coupled to the primary winding of the transformer. The primary side circuit includes a primary controller and a clock generator coupled to output a given pair of signals oscillating at a predetermined frequency. The system also includes a secondary side circuit coupled to the secondary winding of the transformer. The secondary side circuit includes a secondary controller and a clock recovery circuit coupled to output another pair of signals oscillating at the predetermined frequency. The primary side circuit is coupled to transfer power to the secondary side circuit via the transformer. Additionally, the primary controller coupled to intermittently cause a short at the primary winding to indicate a transmission of data to the secondary controller via the transformer and the secondary controller is coupled to intermittently cause a short at the secondary winding to indicate a transmission of data to the primary controller via the transformer.

In a third example, a method includes transferring power from a given winding of a transformer to another winding of a transformer. The method also includes shorting the given winding of the transformer to induce a rapidly rising current on the other winding of the transformer and transmitting data from the given winding to the other winding during a data transmission window that is opened in response to the rapidly induced rising current.

FIG. 1 is a diagram of an example of a system for transferring power and transmitting data over a transformer.

FIG. 2 is a circuit diagram of an example of a system for transferring power and transmitting data over a transformer.

FIG. 3 is a circuit diagram of the system in FIG. 2 operating in a power transfer mode.

FIG. 4 is another circuit diagram of the system in FIG. 2 operating in the power transfer mode.

FIG. 5 is a circuit diagram of the system in FIG. 2 operating in a high primary data mode.

FIG. 6 is a circuit diagram of the system in FIG. 2 operating in a low primary data mode.

FIG. 7 is a circuit diagram of the system in FIG. 2 operating in a high secondary data mode.

FIG. 8 is a circuit diagram of the system in FIG. 2 operating in a low secondary data mode.

FIG. 9 is a timing diagram depicting example waveforms of the circuit of FIG. 2 operating in the high primary data mode.

FIG. 10 is a circuit diagram of the system in FIG. 2 operating in a primary data transmit mode during an echo operation.

FIG. 11 is a circuit diagram of the system in FIG. 2 operating in a secondary data transmit mode during an echo operation.

FIG. 12 is a timing diagram depicting example waveforms of the circuit of FIG. 2 executing an echo operating in the high primary data mode.

FIG. 13 is another timing diagram depicting example waveforms of the circuit of FIG. 2 executing an echo operating in the high primary data mode.

FIG. 14 . is a flowchart of an example method of transferring power and transmitting data via a transformer.

This disclosure describes systems and methods for isolated power transfer and data transmission over the same transformer. In particular, in a power transfer mode, power is transferred from a primary winding to a secondary winding (or vice versa) with a driver (e.g., a half-wave or full-wave driver) operating on the primary side of the transformer and a rectifier (e.g., a half-wave or full-wave rectifier) operating on a secondary side of the transformer.

Intermittently, a given controller modulates data across the transformer. For example, the given controller applies shorts to a given transformer winding (e.g., one of the primary winding or the secondary winding) that induces a rapidly rising current in another transformer winding (e.g., the other of the primary winding or the secondary winding). The rapidly rising current on the other winding of the transformer is detected by another controller, which indicates that a data transmission window is open for a duration (e.g., a predetermined number of clock cycles) corresponding to a data transmission mode.

During the data transmission window, the given controller transmits data to the other controller via the transformer. Additionally, in some examples, to achieve higher power efficiency and/or greater throughput, the other controller may apply a short to the other transformer winding. Upon expiration of the predetermined number of clock cycles, both the given and the other winding of the transformer are de-shorted to terminate the data transmission mode, and the system returns to the power transfer mode.

FIG. 1 is a block diagram of a system 50 for transferring power and transmitting data over a transformer 52 . The transformer 52 includes a primary winding 54 and a secondary winding 56 . A primary side circuit 58 is coupled to the primary winding 54 and a secondary side circuit 60 is coupled the secondary winding 56 . The transformer 52 provides galvanic isolation and electro-magnetic coupling between the primary side circuit 58 and the secondary side circuit 60 .

In at least one example, the primary side circuit 58 is implemented as an integrated circuit (IC) chip. In other examples, some (or all) of the components of the primary side circuit 58 are implemented as discrete circuit components. The primary side circuit 58 includes circuit components (e.g., resistors, capacitors, inductors and switches) that are controlled by a primary controller 62 . In at least one example, primary controller 62 is implemented as a microcontroller (e.g., a microprocessor with embedded machine-readable instructions). In other examples, the primary controller is implemented as hard-wired or programmable logic.

In some examples, the secondary side circuit 60 is implemented in a manner similar to the primary side circuit 58 . That is, in at least one example, the secondary side circuit 60 is also implemented as an IC chip. In other examples, some (or all) of the components of the secondary side circuit 60 are implemented as discrete circuit components. The secondary side circuit 60 includes a secondary controller 64 that controls the circuit components of the secondary side circuit 60 .

The system 50 operates in a plurality of different modes. In particular, the system 50 can operate in a power transfer mode in a synchronous rectification operation. In one example of the power transfer mode, power is transferred from the primary side circuit 58 to the secondary side circuit 60 . In another example, in the power transfer mode, power is transferred from the secondary side circuit 60 to the primary side circuit 58 . For purposes of simplification of explanation, it is presumed that in the power transfer mode, power is transferred from the primary side circuit 58 to the secondary side circuit 60 .

The primary side circuit 58 receives an input signal, V IN . The input signal, V IN is a direct-current (DC) voltage signal. In the power transfer mode, the primary controller 62 controls the primary side circuit 58 to operate as a half-bridge driver that applies a primary driver signal (e.g., a square wave) to a first node 66 of a primary winding 54 of the transformer 52 . Application of the primary driver signal induces a current at a first node 70 of a secondary winding 56 of the transformer 52 . The current at the first node 70 of the secondary winding 56 is provided to the secondary side circuit 60 . The secondary controller 64 controls a rectifier in the secondary side circuit 60 to generate an output signal, V OUT .

The primary controller 62 and the secondary controller 64 each control clock signals that operate in a phase-locked loop (PLL). In this manner, the clock signal of the primary side circuit 58 and the secondary side circuit 60 have the same frequency. Thus, in examples where a number of turns in the primary winding 54 and the secondary winding 56 are equal, the output signal, V OUT is about equal to the input signal V IN . In other examples, the number of turns in the primary winding 54 and the secondary winding 56 are unequal. In such a situation, the output signal, V OUT is greater than or less than the input signal, V IN . Accordingly, in the power transfer mode, the primary side circuit 58 and the secondary side circuit 60 co-operate to execute a synchronous rectification operation.

Additionally, intermittently, the system 50 operates in a primary data transmission mode. In the primary data transmission mode, data is transferred from the primary side circuit 58 to the secondary side circuit 60 via the transformer 52 . To initiate the primary data transmission mode, the primary controller 62 requests opening of a data window.

To request opening of a data window, the primary controller 62 causes the primary side circuit 58 to short (e.g., “short circuit”) the first node 66 of the primary winding 54 with a second node 74 of the primary winding 54 . As used herein, the term “short”, “short circuit” or its derivatives denotes an electrical circuit of significantly lower electrical resistance (e.g., near ‘0’Ω) than that of the resistance during operation in the power transfer mode. For example, while the resistance during the short circuit condition between nodes 66 and 74 is to approximate 0Ω, there may be some incidental resistance due to the electrical path (e.g., a switch device and one or more electrical conductors, such as wires or traces) between such nodes. The substantial shorting of the first node 66 with the second node 74 of the primary winding 54 induces a rapidly rising current at the first node 70 of the secondary winding 56 . The secondary side circuit 60 includes components for detecting the rapidly rising current that provides a signal to the secondary controller 64 indicating that the request for the data transmission window has been received.

In response to the request for the opening of the data transmission window, the secondary controller 64 opens the data transmission window for a predetermined amount of time (e.g., a predetermined number of clock cycles). In some examples, the secondary controller 64 can also execute an echo operation that causes a short between the first node 70 and a second node 76 of the secondary winding 56 . In this manner, the secondary winding 56 is shorted after the shorting of the primary winding 54 such that the state of the secondary winding 56 “echoes” the state of the primary winding 54 . As explained herein, the echo operation improves power efficiency and/or data throughput of the system 50 .

Upon opening of the data transmission window, the primary controller 62 modulates the signal provided to the first node 66 of the primary winding 54 to encode data provided on a primary data input signal, DATA IP . The data is received at the secondary controller 64 . In at least one example, the secondary controller 64 decodes the data and provides the decoded data on a secondary data output signal, DATA OS . In another example, the secondary controller 64 employs the received data for local processing. Upon expiration of the predetermined amount of time, the primary controller 62 causes the primary side circuit 58 to de-short the primary winding 54 . As used herein, the term “de-short” denotes returning the resistance between first and second nodes of the winding (the primary winding 54 or the secondary winding 56 ) to the resistance at the power transfer mode. Additionally, in at least one example, the secondary controller 64 causes the secondary side circuit 60 to de-short the secondary winding 56 , thereby closing the data transmission window. Moreover, the system 50 returns to the power transfer mode.

The system 50 is symmetrical. Accordingly, the transformer 52 allows bi-directional data communication between the primary side circuit 58 and the secondary side circuit 60 . Thus, the system 50 can operate in the secondary data transmission mode. In the secondary data transmission mode, data is transferred from the secondary side circuit 60 to the primary side circuit 58 via the transformer 52 .

In the secondary data transmission mode, the secondary controller 64 can request opening of a data transmission window. To request opening of a data window, the secondary controller 64 causes the secondary side circuit 60 to short the first node 70 of the secondary winding 56 with the second node 76 of the secondary winding 56 . The shorting of the first node 70 with the second node 76 of the secondary winding 56 induces a rapidly rising current at the first node 66 of the primary winding 54 . The primary side circuit 58 includes components for detecting the rapidly rising current that provides a signal to the primary controller 62 indicating that the request for the data transmission window has been received.

In response to the request for opening the data transmission window, the primary controller 62 opens the data transmission window for a predetermined amount of time (e.g., a predetermined number of clock cycles). In some examples, the primary controller 62 can also execute an echo operation that causes a short between the first node 66 and a second node 74 of the primary winding 54 . In this manner, the primary winding 54 is shorted after the shorting of the secondary winding 56 such that the state of the primary winding 54 “echoes” the state of the primary winding 54 . As noted, the echo operation improves power efficiency and/or data throughput of the system 50 .

Upon opening of the data transmission window, the secondary controller 64 modulates the signal provided to the first node 70 of the secondary winding 56 to encode data provided on a secondary data input signal, DATA IS . The data is received at the primary controller 62 . In at least one example, the primary controller 62 decodes the data and provides the decoded data on a primary data output signal, DATA OP . In another example, the primary controller 62 employs the received data for local processing. Upon expiration of the predetermined amount of time, the secondary controller 64 causes the primary side circuit 58 to de-short the primary winding 54 . Additionally, in at least one example, the primary controller 62 causes the primary side circuit 58 to de-short the primary winding 54 , thereby closing the data transmission window. Moreover, the system 50 returns to the power transfer mode.

By employment of the system 50 , the same transformer 52 is employable for both power transfer and bi-directional data communication. In this manner, the need for a separate couplers for transferring power and transmitting data is obviated. Thus, the system 50 can achieve space and cost savings by eliminating the need for a (relatively large and expensive) second transformer and/or optical coupler.

FIG. 2 is a circuit diagram of a system 100 for transferring power and transmitting data over a transformer 102 . In at least one example, the system 100 is employed to implement the system 50 of FIG. 1 . The system 100 includes a primary side circuit 104 and a secondary side circuit 106 . In at least one example, components of the primary side circuit 104 and the secondary side circuit 106 are implemented on respective first and second IC chips. In other examples, some (or all) of the components of the primary side circuit 104 and/or the secondary side circuit 106 are implemented as discrete circuit components. Additionally, in at least one example, the transformer 102 is implemented on a third IC chip. In at least one other example, the transformer is implemented as a discrete circuit component. The transformer 102 provides galvanic isolation and electromagnetic coupling between the primary side circuit 104 and the secondary side circuit 106 .

For purposes of simplification of explanation, the system 100 is illustrated and described as employing a p-channel enhancement mode metal oxide semiconductor field effect transistors (PMOSs) and n-channel enhancement mode metal oxide semiconductor field effect transistors (NMOSs) that operate as electrically controlled switches. However, it is understood that in other examples, other types of transistors, such as PNP and NPN bipolar junction transistors (BJTs) or other type of electric switches (e.g., solid-state relays) could be alternatively employed.

The system 100 operates in multiple modes of operation. In a power transfer mode, the primary side circuit 104 transfers power to the secondary side circuit 106 via the transformer 102 . The system 100 is symmetric. Accordingly, in at least one other example, the secondary side circuit 106 transfers power to the primary side circuit 104 via the transformer 102 . However, for purposes of simplification of explanation, it is presumed that in the power transfer mode, the power is transferred from the primary side circuit 104 to the secondary side circuit 106 .

In the examples described, it is presumed that a primary winding L P and a secondary winding L S of the transformer 102 have equal number of turns. However, in other examples, the primary winding L P and the secondary winding L S of the transformer 102 may have a different number of turns. As used herein, the term “high side” denotes a positive voltage applied to the transformer 102 and the term “low side” denotes a negative voltage or neutral voltage applied to the transformer 102 .

Additionally, the system 100 also operates in a primary data transmit mode and a secondary data transmit mode. Accordingly, as described herein, bi-directional data is transmitted between the primary side circuit 104 and the secondary side circuit 106 via the transformer 102 .

The primary side circuit 104 includes a half-wave driver 105 that is controlled by a primary controller 108 and a clock generator 110 . To transfer power, the primary controller 108 asserts (e.g., sets to a logical ‘1’) an enable signal (labeled in FIG. 2 as “EN P ”) to the clock generator 110 . In response, the clock generator 110 generates two square wave signals, A and B at a predetermined power transfer frequency. In at least one example, the power transfer frequency of A and B is set based on physical properties of the transformer 102 . Moreover, in at least one example, the signals, A and B have the same (or nearly the same waveform) when operating in the power transfer mode.

As used herein, the term “logical ‘1’ denotes a high voltage state (e.g., about 3-5 V) and the term “logical ‘0’” denotes a low voltage state (e.g., about ‘0’ V). As explained, the effects of the logical ‘0’ or logical ‘1’ vary based on the type of device that receives the logical ‘0’ or logical ‘1’.

In at least one example, the primary side circuit 104 includes a PMOS M 1 and an NMOS M 2 . In at least one example, the signal A (output by the clock generator 110 ) is coupled to a gate (a control node) of the PMOS M 1 and the signal B (also output by the clock generator 110 ) coupled to a gate of the NMOS M 2 . A drain (e.g., an output node) of the PMOS M 1 and a drain (e.g., an input node) of the NMOS M 2 is coupled to a first primary side node 112 on a primary winding L P of the transformer 102 . In the examples described herein, the components of the primary side circuit 104 induce a primary driver signal, Drv P at the first primary side node 112 .

In at least one example, the first primary side node 112 is also coupled to a drain of an NMOS M 3 , an inverting input of a primary high side detector implemented as an operational amplifier (op-amp) 114 and to a non-inverting input of a primary low side op-amp 116 . A non-inverting input of the primary high side op-amp 114 is coupled to a power input node 118 of the primary side circuit 104 . Moreover, throughout this disclosure, although op-amps are illustrated, in other examples, other types of detectors could be employed in place of the illustrated and described op-amps.

The power input node 118 is coupled to an input voltage, V IN . In at least one example, the input voltage, V IN is a direct current (DC) voltage. The power input node 118 is also coupled to a source (e.g., an input node) of the PMOS M 1 and to a capacitor C 1 . The capacitor C 1 is also coupled to a second primary side node 120 of the primary winding L P of the transformer 102 . The second primary side node 120 is also coupled another capacitor C 2 and to a source of the NMOS M 3 . In at one example, the capacitors C 1 and C 2 have the same capacitance. Moreover, the capacitance of C 1 and C 2 are based on the power transfer frequency.

The capacitor C 2 is also coupled to a primary side common node 122 . The primary side common node 122 is coupled to an electrically neutral node, GND P (e.g., ground or chassis ground). The primary side common node 122 is also coupled to a source (e.g., an output node) of the NMOS M 2 and to an inverting input of the primary low side op-amp 116 .

The primary controller 108 outputs a signal, TX P (a primary side data transmission signal) for transmitting data to the secondary side circuit 106 . In some examples, the primary controller 108 receives an input data signal, DATA IP that includes encoded data. The signal TX P is coupled to a gate of the NMOS M 3 . Additionally, in at least some examples, an output of the primary high side op-amp 114 , a primary high data receive signal, Rxh p and an output of the primary low side op-amp 116 , a primary low data receive signal, Rxl p is provided to the primary controller 108 .

The secondary side circuit 106 is configured in a manner similar to the primary side circuit 104 . In particular, the secondary side circuit 106 includes a half-wave rectifier 129 that is controlled by a secondary controller 130 and a clock recovery circuit 132 . The secondary controller 130 asserts (e.g., as a logical ‘1’) an enable signal, EN S that is provided to the clock recovery circuit 132 . In response, the clock recovery circuit 132 outputs two square wave signals, C and D that oscillate at the power frequency. In at least one example, in the power transfer mode, the signals C and D have the same (or nearly the same) waveform.

The primary controller 108 and the secondary controller 130 operate in a PLL relationship. That is, the both primary controller 108 and the secondary controller 130 have a clock signal (or multiple clock signals) that have an equal or nearly equal frequency. In this manner, the primary side circuit 104 and the secondary side circuit 106 that are controlled by the primary controller 108 and the secondary controller 130 operate in a synchronized relationship. In this manner, the clock generator 110 of the primary side circuit 104 and the clock recovery circuit 132 of the secondary side circuit 106 operate in the PLL relationship. Accordingly, in the power transfer mode, the signals A and B have the same (or nearly the same) frequency as the signals C and D.

In at least one example, the signal C (provided from the clock recovery circuit 132 ) is coupled to a gate (e.g., a control node) of a PMOS M 4 . Additionally, the signal D is applied to a gate of an NMOS M 5 . A drain (e.g., an output node) of the PMOS M 4 and a drain (e.g., an input node) of the NMOS M 5 is coupled to a first secondary side node 134 of a secondary winding L S of the transformer 102 .

In at least one example, the first secondary side node 134 is also coupled to an inverting input of a secondary high side op-amp 136 and to a non-inverting input of a secondary low side op-amp 138 . The first secondary side node 134 is also coupled to a drain (e.g., an input node) of an NMOS M 6 . In the examples described herein, the components of the transformer 102 and the secondary side circuit 106 induce a secondary driver signal, Drv S on the first secondary side node 134 .

A non-inverting input of the secondary high side op-amp 136 is coupled to a power output node 140 of the secondary side circuit 106 . The power output node 140 provides an output power signal, V OUT . The power output node 140 is also coupled to a source (e.g., an input node) of the PMOS M 4 and to a capacitor C 3 . The capacitor C 3 is also coupled to a second secondary side node 142 of the secondary winding L S . The second secondary side node 142 is coupled to a source (e.g., an output node) of the NMOS M 6 and to a capacitor C 4 . In at least one example, the capacitors C 3 and C 4 have about the same capacitance, which is based on the power transfer frequency.

The capacitor C 2 is also coupled to a secondary side common node 144 . The secondary side common node 144 is coupled to an electrically neutral node, GND S (e.g., ground or chassis ground). The secondary side common node 144 is also coupled to a source (e.g., an output node) of the NMOS M 2 and to an inverting input of the secondary low side op-amp 138 .

The secondary controller 130 outputs a signal, TX S (a secondary side data transmission signal) for transmitting data to the primary side circuit 104 . The signal TX S is coupled to a gate of the NMOS M 6 . In some examples, the secondary controller 130 receives encoded data on an input signal, DATA IS . Additionally, in at least some examples, an output of the primary high side op-amp 114 , a secondary high data receive signal, Rxh S and an output of the primary low side op-amp 116 , a secondary low data receive signal, Rxl s is provided to the primary controller 108 .

As noted, the system 100 can operate in different modes of operation. During the power transfer mode, the NMOSs M 3 and M 6 are turned off (operating in the cutoff mode). Moreover, application of the input voltage, V IN causes the capacitors C 1 and C 2 to charge the second primary side node 120 of the primary winding L P to a voltage level of about one-half of the input voltage, V IN (V IN /2). Moreover, as noted, it is presumed that the turns in the primary winding L P and the secondary winding L S are equal. Thus, an approximately equal voltage of V IN /2 is induced at the second secondary side node 142 of the secondary winding L S .

More particularly, FIGS. 3 and 4 illustrate the system 100 operating in the power transfer mode. For purposes of simplification of explanation, transistors (NMOSs or PMOSs) that are turned off (operating in the cutoff mode) are illustrated with dotted lines to illustrate current flow. Similarly, to illustrate the current flow, transistors (NMOSs or PMOSs) are illustrated with solid lines are turned on (operating in saturation mode). In the operation illustrated by FIGS. 3 and 4 it is presumed that the system 100 is configured such that the output voltage, V OUT is about equal to the input voltage V IN . However, in other examples, the V OUT and V IN may be different voltage levels.

FIG. 3 illustrates the system 100 operating in the power transfer mode during a high side (positive voltage half-cycle) power transfer. During the high side power transfer, the PMOS M 1 is turned on by the signal A, and the NMOS M 2 is turned off by the signal B, driving current to flow in the manner illustrated by the line 150 . As noted, during the power transfer mode, the second primary side node 120 is at a level of about one-half of the input voltage, V IN , namely V IN /2. Moreover, turning on the PMOS M 1 and turning off the NMOS M 2 drives the primary driver signal, Drv P to a level of about the input voltage V IN . As noted, in the power transfer mode, the second primary side node 120 is about one-half the input voltage, V IN /2. Accordingly, the voltage difference between the voltage at the first primary side node 112 and the second primary side node 120 induces a voltage drop of about one-half the input voltage, V IN /2 across the primary winding L P . This voltage drop drives the current indicated by the line 150 that increases at a rate defined by the voltage drop across the primary winding L P (about V IN /2) and the inductance of the primary winding L P .

The rising current across the primary winding L P induces a current on the secondary winding L S , and this current is denoted by a line 152 . As noted, signals C and D output by the clock recovery circuit 132 oscillate at the same frequency (the power transfer frequency) as signals A and B that are output by the clock generator 110 . Thus, during the high side power transfer, NMOS M 5 is turned off (e.g., operating in the cutoff mode) and PMOS M 4 is turned off (operating in the saturation mode). Additionally, NMOS M 6 is also turned off. Thus, the flow of current induced on the secondary winding L S is indicated by the line 152 . As noted, a voltage of about one-half the input voltage (V IN /2) is present at the second secondary side node 142 . Accordingly, the secondary driver signal, Drv S is driven to a level of about the input voltage, V IN . Since the PMOS M 4 is turned on (e.g., operating in the saturation mode), the power output node 140 , which provides the output signal, V OUT is driven to about the same level as the secondary driver signal, Drv S , which is about equal to the input voltage V IN .

FIG. 4 illustrates the system 100 operating in the power transfer mode during a low side (neutral or negative voltage half-cycle) power transfer. During the low side power transfer, in the primary side circuit 104 , the PMOS M 1 is turned off by signal B and NMOS M 2 is turned on by signal A. Additionally, the NMOS M 3 is turned off.

As noted, the second primary side node 120 of the primary winding L P has a voltage level of about one-half of the input voltage, (V IN /2). Turning off the PMOS M 1 and turning on NMOS M 2 couples the first primary side node 112 of the primary winding L P to about the level of the primary side common node 122 (e.g., about GND P or ‘0’ volts). Accordingly, a voltage drop of about one-half of the input voltage, (V IN /2) with is induced over the primary winding L P . The voltage drop induces a decreasing current flowing in a direction indicated by a line 154 . This current decreases at a rate defined by V IN /2 and the inductance of the primary winding L P .

As noted, the second secondary side node 142 has a voltage of about one-half the input voltage (V IN /2). In the secondary side circuit, the PMOS M 4 is turned off by signal C and the NMOS M 5 is turned on by signal D, wherein signals C and D are output by the clock recovery circuit 132 . Additionally, the NMOS M 6 is turned off by the secondary data transmit signal, Tx S . Accordingly, the secondary driver signal, Drv s is driven to a level of about the secondary side common node 144 (about GND S or about ‘0’ volts). Thus, the decreasing current on the primary side circuit 104 indicated by the line 154 induces a corresponding decreasing current on the secondary side circuit 106 that is indicated by a line 156 . The current decreases at a rate defined by the capacitors C 3 and C 4 and the inductance of the secondary winding L S . Moreover, the power output node 140 coupled to the output voltage, V OUT decreases at a rate corresponding to the rate of the decreasing current indicated by the line 156 .

Based on the changing output of signals A and B from the clock generator 110 and the signals C and D of the clock recovery circuit 132 , in the power transfer mode, the system 100 oscillates between a state illustrated in FIG. 3 to a state illustrated in FIG. 4 . This oscillation allows power transfer from the primary side circuit 104 to the secondary side circuit 106 . In this manner, the PMOS M 4 and the NMOS M 5 operate as a rectifier of the secondary driving signal, Drv S . In particular, in at least one example, the primary side circuit 104 and the secondary side circuit 106 are designed such that the output signal, V OUT is about equal to the input signal V IN . Accordingly, the primary side circuit 104 and the secondary side circuit 106 co-operate to execute a synchronous rectification operation.

Referring back to FIG. 2 , as noted, the system 100 also operates in a primary side data transmission mode. In the primary side data transmission mode, data is transferred from the primary side circuit 104 to the secondary side circuit 106 . The primary controller 108 requests opening of a data transmission window for a predetermined number of clock cycles of a data transmission frequency. In at least one example, the data transmission frequency is the same frequency as the power transfer frequency. In other examples, the data transmission frequency is higher or lower than the power transfer frequency. FIGS. 5 and 6 illustrate an example of the system 100 operating in the primary side data transmission mode.

In particular, FIG. 5 illustrates the system 100 operating in the high side primary side data transmission mode, which is referred to as a “high primary data mode” for purposes of simplification of explanation. In the high primary data mode, it is presumed that signals C and D of the clock recovery circuit 132 in the secondary side circuit 106 have turned on the PMOS M 4 (e.g., operating in saturation mode) and turned off the NMOS M 5 . Additionally, the NMOS M 6 is turned off. Concurrently, to request opening of the data transmission window, the primary controller 108 de-asserts (e.g., logical ‘0’) the enable signal provided to the clock generator 110 , EN P . In response, the clock generator 110 turns off the PMOS M 1 and the NMOS M 2 . For example, the clock generator 110 outputs a logical ‘1’ for signal A and a logical ‘0’ for signal B. Accordingly, the primary side circuit 104 operates in a high impedance “high Z” state.

Additionally, the primary controller 108 turns on the NMOS M 3 (e.g., by applying a logical ‘1’ to the primary data transmission signal, Tx P ). Turning on the NMOS M 3 shorts the first primary side node 112 with the second primary side node 120 . That is, turning on NMOS M 3 shorts the primary winding L P . The shorting of the primary winding L P induces a current in the primary winding L P that is indicated by a line 160 . The current indicated by the line 160 rises rapidly at a rate defined by a leakage inductance and a coupling factor of the transformer 102 .

The rapidly rising current in the primary winding L P induces a current in the secondary winding L S that is indicated by a line 162 . The current indicated by the line 162 reverses a current flowing from the drain to the source of the PMOS M 4 , which induces a drain-to-source voltage, V DS across the PMOS M 4 that rises to a (data) threshold level. The drain-to-source voltage, V DS across the PMOS M 4 is detected by the secondary high side op-amp 136 and the secondary high side op-amp 136 asserts (e.g., as a logical ‘1’) the secondary high data receive signal, Rxh s . In response to the assertion (e.g., logical ‘1’) of the secondary high data receive signal, Rxh s the secondary controller 130 opens the data transmission window for a predetermined number of clock cycles of the power transmission clock. To open the data transmission window, the secondary controller 130 sets the enable signal, EN S to a hold state that holds signals C and D to states that keeps PMOS M 4 turned on and NMOS M 5 turned off.

During the data transmission window, the primary controller 108 modulates the primary data transmission signal, TX P to transmit encoded data (e.g., data provided by the data input signal, DATA IP ). The modulation of the primary data transmission signal, TX P induces a corresponding change in the drain-to-source voltage, V DS across the PMOS M 4 that is detected by the secondary high side op-amp 136 . During the data transmission window, the secondary controller 130 samples the output of the secondary high data receive signal, Rxh s at predetermined intervals until the end of the data transmission window. In at least one example, each clock pulse during the data transmission window (or some subset thereof) corresponds to a bit of data. In some examples, the encoded data can be transmitted from the primary side circuit 104 to the secondary side circuit 106 at a rate of up to about 1 Megabit per second (Mbps).

FIG. 6 illustrates the system 100 operating in the low side primary side data transmission mode, which is referred to as a “low primary data mode” for purposes of simplification of explanation. In the low primary data mode, the primary side circuit 104 operates in substantially the same manner as the high primary data mode to request a data transmission window that generates the rapidly rising current indicated by the line 160 . Accordingly, the primary side circuit 104 operates in the high impedance “high Z” state.

Additionally, it is presumed that signals C and D of the clock recovery circuit 132 in the secondary side circuit 106 have turned off the PMOS M 4 (e.g., operating in cutoff mode) and turned on the NMOS M 5 (e.g., operating in saturation mode). Additionally, the NMOS M 6 is turned off.

The rapidly rising current in the primary winding L P induces a current in the secondary winding L S that is indicated by a line 166 . The current indicated by the line 166 reverses a current flowing from the drain to the source of the NMOS M 5 , which induces a drain-to-source voltage, V DS across the NMOS M 5 that rises to the (data) threshold level. The drain-to-source voltage, V DS across the NMOS M 5 is detected by the secondary low side op-amp 138 and the secondary low side op-amp 138 asserts (e.g., as a logical ‘1’) the secondary low data receive signal, Rxl s . In response to the assertion (e.g., logical ‘1’) of the secondary low data receive signal, Rxl s the secondary controller 130 opens the data transmission window for the predetermined number of clock cycles. To open the data transmission window, the secondary controller 130 sets the enable signal, EN S to a hold state that holds signals C and D to states that keeps PMOS M 4 turned off and NMOS M 5 turned on.

During the data transmission window, the primary controller 108 modulates the primary data transmission signal, TX P to transmit encoded data (e.g., provided by the input data signal, DATA IP ) in substantially the same manner as the high primary data mode. The modulation of the primary data transmission signal, TX P induces a corresponding change in the drain-to-source voltage, V DS across the NMOS M 6 that is detected by the secondary low side op-amp 138 . During the data transmission window, the secondary controller 130 samples the output of the secondary low data receive signal, Rxl s at predetermined intervals until the end of the data transmission window. In at least one example, each clock pulse during the data transmission window (or some subset thereof) corresponds to a bit of data. Similar to the high primary data mode, data may be transmitted from the primary side circuit 104 to the secondary side circuit 106 at a rate of up to about 1 Mbps.

Referring back to FIG. 2 , in some examples, the encoded data transmitted in either the high primary data mode or the low primary data mode can be transmitted from the primary side circuit 104 to the secondary side circuit 106 at a rate of up to about 1 Mbps. In some examples, the secondary controller 130 transmits the encoded data to an external component (e.g., another IC chip) via an output signal, DATA OS . In other examples, the secondary controller 130 decodes the encoded data and subsequently transmits the encoded data to an external component via the output data signal, DATA OS . In still other examples, the secondary controller 130 decodes the data received and employs the decoded data for local processing.

Upon termination of the data transmission window, the primary controller 108 re-asserts (e.g., logical ‘1’) the enable signal, EN P and the secondary controller 130 reasserts (e.g., logical ‘1’) the enable signal, EN S thereby returning the system 100 to operation in the power transfer mode.

As noted, the system 100 also operates in the secondary side data transmission mode. In the secondary side data transmission mode, data is transferred from the primary side circuit 104 to the secondary side circuit 106 . The secondary controller 130 requests opening of a data transmission window for a predetermined number of clock cycles of a data transmission frequency. In at least one example, the data transmission frequency is the same frequency as the power transfer frequency. In other examples, the data transmission frequency is higher or lower than the power transfer frequency. FIGS. 7 and 8 illustrate an example of the system 100 operating in the secondary side data transmission mode.

In particular, FIG. 7 illustrates the system 100 operating in a high side secondary side data transmission mode, which is referred to as a “high secondary data mode” for purposes of simplification of explanation. In the high secondary data mode, it is presumed that signals A and B of the clock generator 110 in the primary side circuit 104 have turned on the PMOS M 4 (e.g., operating in saturation mode) and turned off the NMOS M 5 . Additionally, the NMOS M 6 is turned off. Concurrently, to request opening of the data transmission window, the secondary controller 130 de-asserts (e.g., logical ‘0’) the enable signal provided to the clock recovery circuit 132 , EN S . In response, the clock recovery circuit 132 turns off the PMOS M 4 and the NMOS M 5 . For example, the clock generator 110 outputs a logical ‘1’ for signal A and a logical ‘0’ for signal B. Accordingly, the primary side circuit 104 operates in a high impedance “high Z” state.

Additionally, the secondary controller 130 turns on the NMOS M 6 (e.g., by applying a logical ‘1’ to the secondary data transmission signal, Tx S ). Turning on the NMOS M 6 shorts the first secondary side node 134 with the second secondary side node 142 . That is, turning on NMOS M 6 shorts the secondary winding L S . The shorting of the secondary winding L S induces a current in the secondary winding L S that is indicated by a line 170 . The current indicated by the line 170 rises rapidly at a rate defined by the leakage inductance and the coupling factor of the transformer 102 .

The rapidly rising current in the secondary winding L S induces a current in the primary winding L p that is indicated by a line 172 . The current indicated by the line 172 reverses a current flowing from the drain to the source of the PMOS M 1 , which induces a drain-to-source voltage, V DS across the PMOS M 1 that rises to the (data) threshold level. The drain-to-source voltage, V DS across the PMOS M 1 is detected by the primary high side op-amp 114 and the primary high side op-amp 114 asserts (e.g., as a logical ‘1’) the primary high data receive signal, Rxh P . In response to the assertion (e.g., logical ‘1’) of the primary high data receive signal, Rxh P the primary controller 108 opens the data transmission window for the predetermined number of clock cycles. To open the data transmission window, the primary controller 108 sets the enable signal, EN P to a hold state that holds signals A and B to states that keeps PMOS M 1 turned on and the NMOS M 2 turned off.

During the data transmission window, the secondary controller 130 modulates the secondary data transmission signal, TX S to transmit encoded data (e.g., data provided on the data input signal, DATA IS ). The modulation of the secondary data transmission signal, TX S induces a corresponding change in the drain-to-source voltage, V DS across the PMOS M 1 that is detected by the primary high side op-amp 114 . During the data transmission window, the primary controller 108 samples the output of the primary high data receive signal, Rxh P at predetermined intervals until the end of the data transmission window. In at least one example, each clock pulse during the data transmission window (or some subset thereof) corresponds to a bit of data. In some examples, the encoded data can be transmitted from the secondary side circuit 106 to the primary side circuit 104 at a rate of up to about 1 Mbps.

FIG. 8 illustrates the system 100 operating in the low secondary side data transmission mode, which is referred to as a “low secondary data mode” for purposes of simplification of explanation. In the low secondary data mode, the secondary side circuit 106 operates in substantially the same manner as the high secondary data mode to request a data transmission window that generates the rapidly rising current indicated by the line 170 . Accordingly, the primary side circuit 104 operates in the high impedance “high Z” state.

Additionally, it is presumed that signals A and B of the clock generator 110 in the primary side circuit 104 have turned off the PMOS M 1 (e.g., operating in cutoff mode) and turned on the NMOS M 1 (e.g., operating in saturation mode). Additionally, the NMOS M 3 is turned off.

The rapidly rising current in the secondary winding L S induces a current in the primary winding L P that is indicated by a line 174 . The current indicated by the line 174 reverses a current flowing from the drain to the source of the NMOS M 2 , which induces a drain-to-source voltage, V DS across the NMOS M 2 that rises to the (data) threshold level. The drain-to-source voltage, V DS across the NMOS M 2 is detected by the primary low side op-amp 116 and the primary low side op-amp 116 asserts (e.g., as a logical ‘1’) the primary low data receive signal, Rxl P . In response to the assertion (e.g., logical ‘1’) of the primary low data receive signal, the primary controller 108 opens the data transmission window for a predetermined number of clock cycles of the power transmission clock. To open the data transmission window, the primary controller 108 sets the enable signal, EN P to a hold state that holds signals A and B to states that keeps PMOS M 1 turned off and the NMOS M 2 turned on.

During the data transmission window, the secondary controller 130 modulates the secondary data transmission signal, TX S to transmit encoded data in substantially the same manner as the high secondary data mode. The modulation of the secondary data transmission signal, TX S induces a corresponding change in the drain-to-source voltage, V DS across the PMOS M 1 that is detected by the primary low side op-amp 116 . During the data transmission window, the primary controller 108 samples the output of the secondary low data receive signal, Rxl s at predetermined intervals until the end of the data transmission window. In at least one example, each clock pulse during the data transmission window (or some subset thereof) corresponds to a bit of data. Similar to the high secondary data mode, data may be transmitted from the secondary side circuit 106 to the primary side circuit 104 at a rate of up to about 1 Mbps.

Referring back to FIG. 2 , in some examples, the encoded data transmitted in either the high primary data mode or the low primary data mode can be transmitted from the secondary side circuit 106 to the primary side circuit 104 at a rate of up to about 1 Mbps. In some examples, the primary controller 109 transmits the encoded data to an external component (e.g., another IC chip) via a data output signal, DATA OP . In other examples, the secondary controller 130 decodes the encoded data and subsequently transmits the encoded data to an external component via the data output signal, DATA OP . In still other examples, the primary controller 108 decodes the data received and employs the decoded data for local processing.

Upon termination of the data transmission window, the primary controller 108 re-asserts (e.g., logical ‘1’) the enable signal, EN P and the secondary controller 130 reasserts (e.g., logical ‘1’) the enable signal, EN S thereby returning the system 100 to operation in the power transfer mode.

As illustrated in FIGS. 5-8 , the system 100 allows for bi-directional data communication between the primary side circuit 104 and the secondary side circuit 106 . That is, the system 100 allows data to be transmitted from the primary side circuit 104 to the secondary side circuit 106 or from the secondary side circuit 106 to the primary side circuit 104 . In this manner, the same transformer 102 is employed in the power transfer mode, the primary data transmission mode and the secondary data transmission mode.

FIG. 9 illustrates a timing diagram 200 of an example of waveforms that demonstrate operation of the system 100 of FIG. 2 in the high primary data mode. The waveforms of the low primary data mode, the high secondary data mode and the low secondary data mode are similar to the waveforms illustrated in the timing diagram 200 .

In the timing diagram 200 , from time t 0 to t 1 and after time t 2 the system 100 operates in the power transfer mode. In the power transfer mode, a waveform labeled “PRIMARY SIDE” denotes a state of the primary side circuit 104 and a waveform labeled “SECONDARY SIDE” denotes a state of the secondary side circuit 106 . In particular, in a low-side on state labeled, “LS ON” in FIG. 9 , the NMOSs M 2 and M 5 are turned on (operating in the saturation mode) and the PMOSs M 1 and M 4 are turned off (operating in the cutoff mode). Conversely, in a high-side on state labeled “HS ON”, the PMOS M 1 and M 4 are turned on and the NMOSs M 2 and M 5 are turned off.

The timing diagram 200 also includes a shorting state of the primary winding L P (labeled as “L P SHORT” in FIG. 9 ). Between times t 1 and t 2 , the system 100 operates in the high primary data mode. In particular, at time t 1 , the primary data transmit signal, Tx P is asserted (e.g., logical ‘1’) and the NMOS M 3 turns on, (labeled as “M 3 ON”), thereby shorting the primary winding L P . Additionally, the primary side switches to the high impedance state (labeled as “HS HIGHZ” in FIG. 9 ), where PMOS M 1 and PMOS M 3 are turned off.

Shorting the primary winding L P induces a rapidly rising current on the secondary winding L S (labeled “I-L S ” in FIG. 9 ). The rapidly rising current induces a drain-to-source voltage (V DS ) drop across PMOS M 4 (labeled as “V DS (M 4 )” in FIG. 9 ). Upon reaching a threshold voltage, the secondary high data receive signal (labeled “Rxh s ” in FIG. 9 ) is asserted to open a data transmission window 202 for a predetermined number of clock cycles. During the data transmission window, the primary side data transmit signal, Tx P is modulated to provide data that is detected by the secondary controller 130 . Upon expiration of the data transmission window at time t 2 , the system 100 returns to the power transfer mode.

Referring back to FIG. 2 , in the primary side data transmission mode and the secondary side data transmission mode in some examples, the primary controller 108 and/or the secondary controller 130 executes an echo operation. The echo operation reduces excitation of the transformer 102 that increases power efficiency and/or increases a data transmission rate of the system 100 .

FIG. 10 illustrates the system 100 operating in the high primary data mode or the low primary data mode with an echo operation. In particular, the primary side circuit 104 induces the current indicated by the line 160 to open the data window in a manner illustrated and described with respect to FIG. 5 or FIG. 6 . Upon opening the data window, the secondary controller 130 switches the half-wave rectifier 129 of the secondary side circuit 106 into the high impedance (High Z) state. In such a situation, the secondary controller 130 causes the clock recovery circuit 132 to output signals C and D to turn off PMOS M 4 and NMOS M 5 (operate in the cutoff mode). Additionally, the secondary controller 130 controls the secondary transmission signal, TX S to turn on the NMOS M 6 (operate in the saturation mode). Turning on the NMOS M 6 shorts the secondary winding L S (shorting the first secondary side node 134 with the second secondary side node 142 ) to induce a current indicated by a line 180 , echoing the state of the primary winding L P .

Accordingly, the half-wave driver 105 of the primary side circuit 104 and the half-wave rectifier 129 of the secondary side circuit 106 are operating in the high impedance (High Z) state and both the primary winding L P and the secondary winding L S of the transformer 102 are shorted. Additionally, the data modulated on the primary side data transmission signal, TX P is detected at the secondary high side op-amp 136 or at the secondary low side op-amp 138 in the manner described herein. Additionally, because the primary winding L P and the secondary winding L S are shorted, the transformer 102 avoids further rise in the current at the secondary side driver signal, Drv S , such that additional (excess) current dissipation is reduced during the primary side data transmission mode.

FIG. 11 illustrates the system 100 operating in the high secondary data mode or the low secondary data mode with an echo operation. In particular, the secondary side circuit 106 induces the current indicated by the line 170 to open the data window in a manner illustrated and described with respect to FIG. 7 or FIG. 8 . Upon opening the data window, the primary controller 108 switches the half-wave driver 105 of the primary side circuit 104 into the high impedance (High Z) state. In such a situation, the primary controller 108 causes the clock generator 110 to output signals A and B to turn off PMOS M 1 and NMOS M 2 (operate in the cutoff mode). Additionally, the primary controller 108 controls the primary data transmission signal, TX P to turn on the NMOS M 3 (operate in the saturation mode). Turning on NMOS M 3 shorts the primary winding L P to induce a current indicated by a line 190 , echoing the state of the secondary winding L S .

Accordingly, the half-wave driver 105 of the primary side circuit 104 and the half-wave rectifier 129 secondary side circuit 106 are operating in the high impedance (High Z) state and both the primary winding L P and the secondary winding L S of the transformer 102 are shorted. Additionally, the data modulated on the secondary side data transmission signal, TX S is detected at the primary high side op-amp 114 or at the primary low side op-amp 116 in the manner described herein. Additionally, because the primary winding L P and the secondary winding L S are shorted, the transformer 102 avoids further rise in the current at the primary side driver signal, Drv P , such that additional (excess) current dissipation is reduced during the primary side data transmission mode.

FIG. 12 illustrates a timing diagram 300 of an example of waveforms that demonstrate a given echo operation of the system 100 of FIG. 2 in the high primary data mode. The waveforms of the low primary data mode, the high secondary data mode and the low secondary data mode are similar to the timing diagram 200 .

In the timing diagram 300 , from time t 0 until time t 2 and from time t 5 until time t 6 the system 100 operates in the power transfer mode. In the power transfer mode, a waveform labeled “PRIMARY SIDE” denotes a state of the primary side circuit 104 and a waveform labeled “SECONDARY SIDE” denotes a state of the secondary side circuit 106 . In particular, in a low-side on state labeled, “LS ON” in FIG. 12 , the NMOSs M 2 and M 5 are turned on (operating in the saturation mode) and the PMOSs M 1 and M 4 are turned off (operating in the cutoff mode). Conversely, in a high-side on state labeled “HS ON”, the PMOS M 1 and M 4 are turned on and the NMOSs M 2 and M 5 are turned off.

The timing diagram 300 also includes a shorting state of the primary winding L P (labeled as “L P SHORT” in FIG. 11 ). Between times t 2 and t 4 , the system 100 operates in the high primary data mode. In particular, at time t 2 , the primary data transmit signal, Tx P is asserted (e.g., logical ‘1’) and the NMOS M 3 turns on, (labeled as “M 3 ON”), thereby shorting the primary winding L P . Additionally, the primary side switches to the high impedance state (labeled as “HS HIGHZ” in FIG. 12 ), where PMOS M 1 and PMOS M 3 are turned off.

Shorting the primary winding L P induces a rapidly rising current on the secondary winding L S (labeled “I-L S ” in FIG. 12 ). The rapidly rising current causes a secondary high data receive signal (labeled “Rxh s ” in FIG. 12 ) is be asserted (e.g., logical ‘1’) to open a data transmission window 302 for a predetermined number of clock cycles. During the data transmission window 302 , the primary side data transmit signal, Tx P is modulated to provide data that is detected by the secondary controller 130 .

Additionally, starting at time t 3 , the secondary controller 130 executes an echo operation that asserts (e.g., logical ‘1’) the secondary data transmission signal, Tx s that shorts the secondary winding L S during the window indicated by 304 . Additionally, at time t 4 , the primary controller de-asserts (e.g., logical ‘0’) the primary side data transmission signal, Tx P thereby de-shorting the primary winding L P . In response, the secondary controller 130 de-asserts (e.g., logical ‘0’) the secondary data transmission signal, Tx s to de-short the secondary winding L s . Additionally, the current in the secondary winding, I-L S decays to a level, the level during the power transfer mode. Additionally, shortly after time t 4 , the system 100 returns to the power transfer mode (indicated by in FIG. 4 as “POWER”). At time t 5 , the secondary high data receive signal, Rxh s returns to a low state (e.g., logical ‘0’).

Upon expiration of the data transmission window at time t 2 , the system 100 returns to the power transfer mode. By executing the given echo operation in the manner illustrated by the timing diagram 200 , the system 100 is tuned to improve power efficiency. In particular, by shorting the secondary winding L S during the window 304 , power loss due to excess current at the secondary side circuit 106 is reduced.

FIG. 13 illustrates a timing diagram 400 of an example of waveforms that demonstrate another echo operation of the system 100 of FIG. 2 in the high primary data mode. The waveforms of the low primary data mode, the high secondary data mode and the low secondary data mode are similar to the timing diagram 400 .

In the timing diagram 400 , from time t 0 until time t 2 and after time t 7 the system 100 operates in the power transfer mode. In the power transfer mode, a waveform labeled “PRIMARY SIDE” denotes a state of the primary side circuit 104 and a waveform labeled “SECONDARY SIDE” denotes a state of the secondary side circuit 106 . In particular, in a low-side on state labeled, “LS ON” in FIG. 13 , the NMOSs M 2 and M 5 are turned on (operating in the saturation mode) and the PMOSs M 1 and M 4 are turned off (operating in the cutoff mode). Conversely, at time t 1 the system 100 operates in a high-side on state labeled “HS ON”, the PMOS M 1 and M 4 are turned on and the NMOSs M 2 and M 5 are turned off.

The timing diagram 400 also includes a shorting state of the primary winding L P (labeled as “L P SHORT” in FIG. 13 ). Between times t 2 and t 6 , the system 100 operates in the high primary data mode. In particular, at time t 2 , the primary data transmit signal, Tx P is asserted (e.g., logical ‘1’) and the NMOS M 3 turns on, (labeled as “M 3 ON”), thereby shorting the primary winding L P . Additionally, the primary side switches to the high impedance state (labeled as “HS HIGHZ” in FIG. 13 ), where PMOS M 1 and PMOS M 3 are turned off.

Shorting the primary winding L P induces a rapidly rising current on the secondary winding L S (labeled “I-L S ” in FIG. 13 ). The rapidly rising current causes a secondary high data receive signal (labeled “Rxh s ” in FIG. 13 ) is be asserted (e.g., logical ‘1’) to open a data transmission window 402 for a predetermined number of clock cycles. During the data transmission window 402 , the primary side data transmit signal, Tx P is modulated to provide data that is detected by the secondary controller 130 .

Additionally, starting at time t 4 , the secondary controller 130 executes the other echo operation that asserts (e.g., logical ‘1’) the secondary data transmission signal, Tx s that shorts the secondary winding L S during the window indicated by 404 . Additionally, at time t 5 , the primary controller de-asserts (e.g., logical ‘0’) the primary side data transmission signal, Tx P thereby de-shorting the primary winding L P . In response, at time t 6 , the secondary controller 130 de-asserts (e.g., logical ‘0’) the secondary data transmission signal, Tx s to de-short the secondary winding L S in response to the secondary winding current I-L S decaying to a level prior to the shorting of the primary winding L P noted with reference number 406 . In the other echo operation, the secondary winding L S and the primary winding L P are shorted for about the same amount of time (e.g., within about 1 microsecond). Additionally, shortly after time t 5 , at time t 7 the system 100 returns to the power transfer mode (indicated by in FIG. 4 as “POWER”). At time t 7 , the secondary high data receive signal, Rxh s returns to a low state (e.g., logical ‘0’).

Upon expiration of the data transmission window at time t 6 , the system 100 returns to the power transfer mode. By executing the other echo operation in the manner illustrated by the timing diagram 200 , the system 100 is tuned to improve power efficiency and increase bandwidth. In particular, by shorting the secondary winding L S during the window 304 , power loss due to excess current at the secondary side circuit 106 is reduced. Additionally, as compared to the given echo operation illustrated by the timing diagram 200 in FIG. 12 , the other echo operation increases a duration of the data transmission window by matching a duration of shorting of the primary winding L P with the duration of the shorting the secondary winding L S .

Referring back to FIG. 2 , as described, the system 100 allows the same transformer 102 to be employed in the power transfer mode, the primary data transmission mode and the secondary data transmission mode. Accordingly, the system 100 obviates the need for separate transformers or other signal couplers for power transfer and data transfer. Thus, the system 100 can achieve space and cost savings by eliminating the need for a (relatively large and expensive) second transformer and/or signal coupler.

In view of the foregoing structural and functional features described above, an example method will be better appreciated with reference to FIG. 14 . While, for purposes of simplicity of explanation, the example method of FIG. 14 is shown and described as executing serially, it is to be understood and appreciated that the present examples are not limited by the illustrated order, as some actions could in other examples occur in different orders, multiple times and/or concurrently from that shown and described herein. Moreover, it is not necessary that all described actions be performed to implement a method.

FIG. 14 illustrates a flowchart of an example method 500 for transferring power and transmitting data over a transformer. The method 500 could be implemented, for example, by the system 50 of FIG. 1 and/or the system 100 illustrated in FIG. 2 .

At 510 , the system transfers power from a given side circuit (e.g., a given one of the primary side circuit 58 and the secondary side circuit 60 ) to another side circuit (e.g., the other of the primary side circuit and the secondary side circuit) coupled to the transformer. That is, at 510 , the system operates in the power transfer mode.

At 520 , a given controller (e.g., a given one of the primary controller 62 or the secondary controller 64 of FIG. 1 ) shorts a given winding of the given side of the transformer is shorted to indicate a request for opening of a data transmission window. At 530 , another controller (e.g., the other of the primary controller the secondary controller of FIG. 1 ) executes an echo operation that shorts another winding of the other side of the transformer in response to opening the data transmission window. At 540 , the data is transmitted from the given side circuit to the other side circuit via the transformer. That is, at 520 - 540 , the system operates in the primary data transfer mode or the secondary data transfer mode. At 550 , the given winding is de-shorted and the method returns to 510 .

In this description, the term “based on” means based at least in part on. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.