IGBT modeling method and circuit simulation method

Embodiments of the present invention relate to the field of power semiconductor devices, and more specifically, to an IGBT (Insulated Gate Bipolar Transistor) modeling method and a circuit simulation method.

Insulated Gate Bipolar Transistors (IGBTs) are currently the most widely used active switching devices in power electronics converters. Therefore, a variety of researches have been conducted on the modeling of IGBT. The current IGBT models are mainly divided into two categories from the users' point of view, namely analytical models and behavioral models.

Analytical models are established mainly based on the principles of semiconductor physics, according to the internal structure and the carrier transport of the IGBT. The analytical models can simulate both the steady-state and transient characteristics of IGBTs accurately. The conventional analytical models include Hefner model, Kuang Sheng model, Kraus model, etc. Although the analytical models are accurate, the models suffer for complicated circuit simulations due to complex structures, difficult parameter extractions, large amount of computation and difficulties in convergence.

Behavioral models ignore some internal physical mechanisms of IGBTs, and are more focused on fitting the external characteristics of the devices. The behavioral models can be applied in circuit simulations and can be more accurate than the ideal switch model. As compared to the analytical models, behavioral models are simpler but less accurate, and are less adaptable to different working conditions. Parameter extraction of behavioral models is still complicated, since the parameters have to be extracted from experiment results.

Embodiments of the present invention aim to help overcome the drawbacks of inaccurate transient characteristics and reliance of parameter extraction on experiment results of the conventional models of IGBT.

At least one aspect of embodiments of the present invention is an IGBT modeling method. The IGBT modeling method includes creating piece-wise line functions to describe a collector-emitter voltage v ce , a collector current i c and a gate-emitter voltage v ge of the IGBT during a switching-on transient and a switching-off transient based on an internal structure of the IGBT and transient processes of the IGBT.

In at least one embodiment, in the IGBT modeling method, the creating of the piece-wise line functions to describe the collector-emitter voltage v ce , the collector current i c and the gate-emitter voltage v ge of the IGBT during the switching-on transient and the switching-off transient includes determining various periods during the switching-on transient and the switching-off transient of the IGBT.

The switching-on transient, which is after a turn-on signal and before a steady on-state, is divided into four periods: a first period starts when a gate drive sends the turn-on signal and ends when i c begins to rise, a second period starts when i c begins to rise from 0 and ends when i c reaches a maximum value, a third period starts when i c reaches the maximum value and ends when i c falls back to a load current, and a fourth period ends when v ce falls back to a saturation voltage.

The switching-off transient, which is after a turn-off signal and before a steady off-state, is divided into four periods: a first period starts when the gate drive sends the turn-off signal and ends when v ce begins to rise, a second period starts when v ce begins to rise from the saturation voltage and ends when v ce reaches a DC bus voltage, a third period starts when i c begins to fall from the load current and ends when i c falls to a tail current initial value, and a fourth period ends when i c falls to 0.

The creating of the piece-wise line functions to describe the collector-emitter voltage v ce , the collector current i c and the gate-emitter voltage v ge of the IGBT during the switching-on transient and the switching-off transient includes determining starting values and ending values of the collector-emitter voltage v ce , the collector current i c and the gate-emitter voltage v ge during the four periods of the switching-on transient and the switching-off transient and the duration of the various periods based on the transient processes of the IGBT, and determining the collector-emitter voltage v ce , the collector current i c and the gate-emitter voltage v ge during the various periods in the form of linear function or exponential function.

In at least one embodiment, in the IGBT modeling method, all the parameters used in the creating of piece-wise line functions are obtained from datasheets of the IGBT.

At least one aspect of embodiments of the present invention includes a circuit simulation method, in which an IGBT piece-wise line model is used to describe the characteristics of a commutation loop. The method includes forming a two-port network based on an IGBT, a commutation diode and stray inductance in a commutation loop. Voltages and currents of input and output ports of the two-port network are determined according to the direction of the output current. If the output current flows out of the two-port network, the voltage of the input port equals to a DC bus voltage V DC and the current of the input port equals to the collector current i c , while the current of the output port equals to a load current I L and the voltage of the output port equals to V DC -v ce , v ce is a collector-emitter voltage. If the output current flows into the two-port network, the voltage of the input port equals to the DC bus voltage V DC and the current of the input port equals to i c -I L , while the current of the output port equals to the load current I L and the voltage of the output port equals to the collector-emitter voltage v ce .

The circuit simulation method further includes obtaining a relationship between (v ce , i c ) and (V DC , I L , sw) in each period during a switching-on transient and a switching-off transient according to the above-mentioned IGBT modeling method, wherein sw represents an IGBT switching signal.

The circuit simulation method further includes adding the two-port network in its entirety to a simulation circuit for computation.

At least one aspect of embodiments of the present invention includes a computer readable storage medium, having stored thereon program codes which can be executed by one or more processors to perform the above-mentioned circuit simulation method.

Embodiments of the present invention have at least one of the following features.

Based on a typical IGBT internal structure (e.g., planar NPT IGBT) and the transient processes of the IGBT, and under certain simplification assumptions, a piece-wise line model is created to describe the collector-emitter voltage v ce and collector current i c of IGBT during switching-on and switching-off transients.

The piece-wise line model can accurately represent the important transient characteristics of the IGBT including the delay time, turn-on rise time, turn-off fall time, peak voltage, peak current, etc.

All the parameters of the model can be obtained from datasheets.

The model can be implemented conveniently in circuit simulation. There is no need to model the commutation diode in the commutation loop.

The above and other features and advantages of the present invention can be better understood from the detailed description of the preferred embodiments in conjunction with the drawings, wherein:

FIG. 1 is a piece-wise line model of IGBT during the switching-on transient according to at least one embodiment of the present invention;

FIG. 2 is a piece-wise line model of IGBT during the switching-off transient according to at least one embodiment of the present invention;

FIG. 3 illustrates an implementation of the piece-wise line model of IGBT in a simulation circuit when the current flows out of the phase arm according to at least one embodiment of the present invention;

FIG. 4 illustrates an implementation of the piece-wise line model of IGBT in a simulation circuit when the current flows into the phase arm according to at least one embodiment of the present invention;

FIG. 5 is a graph of simulation results of the piece-wise line model of IGBT during switching-on transient according to at least one embodiment of the present invention and experiment waveforms; and

FIG. 6 is a graph of simulation results of the piece-wise line model of IGBT during switching-off transient according to at least one embodiment of the present invention and experiment waveforms.

Embodiments of the present invention will be described in detail in conjunction with the accompanying drawings. These embodiments are only illustrative and for explaining the present invention, but shall not be considered as a limitation thereto. In the figures, the same or similar reference numbers denote the same or similar elements.

At least one embodiment of the present invention includes an IGBT modeling method, which creates a piece-wise line model of IGBT working in hard switching mode suitable for circuit simulation. Based on an internal structure of a typical IGBT (e.g., planar NPT IGBT) and its transient processes, and under certain simplification assumptions, the modeling method uses piece-wise lines to describe the gate-emitter voltage v ge , the collector-emitter voltage v ce and the collector current i c of IGBT during a switching-on transient and a switching-off transient. The piece-wise line model created by the proposed modeling method can represent the critical transient characteristics of the IGBT devices, and all parameters of the model can be obtained from datasheets.

Specifically, the modeling method includes determining various periods during the switching-on transient and the switching-off transient of the IGBT.

In FIG. 1 , the switching-on transient, which is after a turn-on signal and before a steady on-state, is divided into four periods. The first period [t 0 -t 1 ] starts when the gate drive sends the turn-on signal and ends when i c begins to rise. The second period [t 1 -t 2 ] starts when i c begins to rise from 0 and ends when i c reaches the maximum value. The third period [t 2 -t 3 ] starts when i c reaches the maximum value and ends when i c falls back to the load current. The fourth period [t 3 -t 4 ] ends when v ce falls back to the saturation voltage. [t 4 -t 5 ] indicates the steady on-state of the IGBT.

In FIG. 2 , the switching-off transient, which is after a turn-off signal and before a steady off-state, is divided into four periods. The first period [t 6 -t 7 ] starts when the gate drive sends the turn-off signal and ends when v ce begins to rise. The second period [t 7 -t 8 ] starts when v ce begins to rise from the saturation voltage and ends when v ce reaches the DC bus voltage. The third period [t 8 -t 9 ] starts when i c begins to fall from the load current and ends when i c falls to a tail current initial value. The fourth period [t 9 -t 10 ] ends when i c falls to 0. [t 10 -t 11 ] indicates the steady off-state of the IGBT.

The modeling method further includes creating piece-wise line models for IGBT switching-on and switching-off transients.

The following description is for creating the piece-wise line model for IGBT switching-on transient.

During the switching-on transient, the DC bus voltage is defined as V DC and the load current is defined as I L .

The various periods of the switching-on transient process of IGBT and the piece-wise line model are in FIG. 1 .

Period I [t 0 -t 1 ]: t 0 is defined as the time when the IGBT gate drive sends a turn-on signal, the output voltage of the gate drive changes from negative V g(off) to positive V g(on) , and the IGBT driver charges the gate-to-emitter capacitor C ge through the gate resistor R gon . During this period, the gate-emitter voltage v ge , collector-emitter voltage v ce and collector current i c can be expressed by the following equations:

where V g(off) and V g(on) are off-state voltage and on-state voltage of the gate drive. R gon is the turn-on resistance of the gate drive. C ge is the gate-emitter capacitance of IGBT.

t 1 is defined as the time when v ge reaches the gate threshold voltage V T .

All the parameters above can be obtained from the IGBT datasheet and the gate drive datasheet.

Period II [t 1 -t 2 ]: From t 1 , v ge keeps increasing from threshold voltage V T . t 2 is defined as the time when the collector current i c increases to the peak current I cmax . The peak current I cmax is regarded as being proportional to I L , as expressed by the following equation:

where I N is the rated current of the IGBT and I rr is the reverse recovery current of the diode under the rated current.

During this period, IGBT gate-emitter voltage v ge increases to miller-stage V ml linearly. The collector current i c rises to the maximum value I cmax at the same slope as in the rated condition. The collector-emitter voltage v ce falls at a constant slope. The gate-emitter voltage v ge , the collector-emitter voltage v ce and the collector current i c can be expressed by the following equations:

i c ( t )= i c ( t 1 )+ k i2 ( t−t 1 )  (6)

v ce ( t )= v ce ( t 1 )+ k v2 ( t−t 1 )  (7)

v ge ( t )= v ge ( t 1 )+ k vg2 ( t−t 1 )  (8)

where

where t r is the turn-on rise time of the IGBT, t rr is the reverse recovery time of the diode. V ml is the miller-stage voltage, which can be obtained from the curve of the gate charge characteristics. L s is the stray inductance.

All the parameters above can be obtained from the IGBT datasheet.

The duration of this period is expressed by the following equation.

Period III [t 2 -t 3 ]: After t 2 , the collector current i c keeps falling from the peak value until it reaches the load current I L at t 3 . During this period, v ge keeps unchanged. v ce will fall to the saturation voltage V CEsat after 2t rr from t 3 . The rate of change of the collector current i c is contrary to the previous period, as expressed by the following equations:

i c ( t )= i c ( t 2 )+ k i3 ( t−t 2 )  (13)

v ce ( t )= v ce ( t 2 )+ k v3 ( t−t 2 )  (14)

v ge ( t )= V ml   (15)

where

Where V CEsat is the saturation voltage under the corresponding collector current according to the IGBT datasheet, which can be directly obtained from a look-up table of output characteristics or calculated by a curve-fitting method.

The duration of this period is expressed by the following equation.

Period IV [t 3 -t 4 ]: v ce keeps falling after t 3 and reaches V CEsat at t 4 . During this period, the IGBT gate-emitter voltage v ge and the collector current i c keep unchanged, as expressed by the following equations.

i c ( t )= I L   (19)

v ce ( t )= v ce ( t 2 )+ k v3 ( t−t 2 )  (20)

v ge ( t )= V ml   (21)

The duration of this period is expressed by the following equation.

t 4 −t 3 =2 t rr   (22)

Steady on-state [t 4 -t 5 ]: From t 4 , v ge is further charged to the on-state voltage of the gate drive V g(on) by the RC circuit. v ce and i c keep unchanged during this period.

The capacitance C ge +C oxd equals to the value of the input capacitance C ies when v ce is the saturation voltage, which can be obtained from the capacitances-voltage curve provided by the IGBT datasheet.

This period represents the steady on-state. This period lasts until the next turn-off time t 5 .

The following description relates to creating the piece-wise line model for IGBT switching-off transient.

The various periods of the switching-off transient process of IGBT and the piece-wise line model are in FIG. 2 .

Period I [t 6 -t 7 ]: t 6 is defined as the time when the IGBT gate drive sends a turn-off signal, the output voltage of the IGBT gate drive changes from positive V g(on) to negative V g(off) , and the IGBT driver discharges the gate-to-emitter capacitor C ge through the gate resistor R goff . During this period, the gate-emitter voltage v ge , the collector-emitter voltage v ce and the collector current i c can be expressed by the following equations.

t 7 is defined as the time when v ge falls to the miller-stage voltage V ml . The duration of this period is expressed as

Period II [t 7 -t 8 ]: From t 7 , the collector-emitter voltage v ce begins to rise until it reaches the DC bus voltage V DC at t 8 .

The duration of this period is expressed as:

t doff is the IGBT turn-off delay time, which is provided by the IGBT datasheet.

During this period, the gate-emitter voltage v ge , the collector-emitter voltage v and the collector current i c can be expressed by the following equations

v ge ( t )= V ml   (31)

i c ( t )= I L   (32)

v ce ( t )= v ce ( t 7 )+ k v8 ( t−t 7 )  (33)

where

Period III [t 8 -t 9 ]: From t 8 , i c begins to fall until it reaches a tail current initial value I tail at t 9 . The tail current initial value I tail is proportional to the load current I L .

I tail =0.2 I L   (35)

During this period, the gate-emitter voltage v ge and the collector current i c can be expressed by the following equations:

v ge ( t )= v ge ( t 8 )+ k vg9 ( t−t 8 )  (36)

i c ( t )= i c ( t 8 )+ k i9 ( t−t 8 )  (37)

where

t f is the turn-off fall time of the IGBT, provided by the IGBT datasheet.

The duration of this period is expressed as:

In this period, the IGBT collector-emitter voltage v ce waveform is approximately an isosceles triangle. The time t 8 ′ is defined as

t 8 ′=t 8 +t f /1.6  (41)

v ce can be expressed by the following equation:

where

The voltage peak V cemax during this period is caused by the stray inductance, and can be approximately expressed as:

Period IV [t 9 -t 10 ]: At t 9 , v ge falls to V T . t 10 is defined as the time when the collector current falls to 0. During this period, the gate-emitter capacitor is further discharged by the gate drive through the turn-off gate resistor R goff .

The duration of this period is expressed as:

t 10 −t 9 =10 t f   (45)

During this period, the gate-emitter voltage v ge , the collector-emitter voltage v ce and the collector current i c can be expressed by the following equations.

where

Steady off-state [t 10 -t 11 ]: During this period, the gate-emitter voltage v ge , the collector-emitter voltage v ce and the collector current i c can be expressed by the following equations.

This period represents the steady off-state. The period lasts until the next turn-on time t 11 .

The IGBT piece-wise line model of embodiments of the present invention is suitable for implementation in a simulation circuit. In an embodiment, the IGBT piece-wise line model is used to describe the characteristics of the whole commutation loop. There is no need to model the diode commutating with the IGBT.

Accordingly, the present invention provides a circuit simulation method.

An IGBT, a commutation diode and stray inductance in a commutation loop are taken as a two-port network. Voltages and currents of the input and output ports of the two-port network are determined according to the direction of the output current. When the output current flows out of the phase arm (the two-port network), the voltage of the input port equals to the DC bus voltage V DC and the current of the input port equals to the collector current i c , while the current of the output port equals to the load current I L and the voltage of the output port equals to V DC -v ce , v ce is the collector-emitter voltage, as shown in FIG. 3 . When the current of the output port flows into the phase arm (the two-port network), the voltage of the input port equals to the DC bus voltage V DC and the current of the input port equals to i c -I L , while the current of the output port equals to the load current I L and the voltage of the output port equals to the collector-emitter voltage v ce , as in FIG. 4 .

The relationship between (v ce , i c ) and (V DC , I L , sw) in each period during switching-on and switching-off transients is obtained according to the above modeling method of IGBT devices, wherein sw represents the IGBT switching signal.

The two-port network in its entirety is added to a simulation circuit for computation.

According to the IGBT modeling method according to at least one embodiment of the present invention, a piece-wise line model of the 6500V/600 A FZ600R65KF1 IGBT is created and implemented in a double pulse test circuit. FIG. 5 is a graph of simulation results and experiment waveforms of the IGBT gate-emitter voltage v ge , collector-emitter voltage v ce and collector current i c during switching-on transient. FIG. 6 is graph of simulation results and experiment waveforms of the IGBT gate-emitter voltage v ge , collector-emitter voltage v ce and collector current i c during switching-off transient. As shown in the two figures, the piece-wise line model of the present invention can be applied in circuit simulation. The model is capable of accurately representing the major characteristics of the IGBT during transient process including the delay time, turn-on rise time, turn-off fall time, peak voltage, peak current, etc.

Embodiments of present invention include at least one of the following features.

Based on a typical IGBT internal structure (e.g. planar NPT IGBT) and transient processes of the IGBT, and under certain simplification assumptions, a piece-wise line model is created to describe the collector-emitter voltage v ce and collector current i c of IGBT during switching-on and switching-off transients.

The piece-wise line model can accurately represent the important transient characteristics of the IGBT including the delay time, turn-on rise time, turn-off fall time, peak voltage, peak current, etc.

All parameters of the model can be obtained from datasheets.

The model can be implemented conveniently in circuit simulation. There is no need to model the commutation diode in the commutation loop.

At least one embodiment of the present invention can also be implemented as a computer-readable storage medium. The computer-readable storage medium can store program instructions, which can be executed by one or more processors to perform the simulation method of the embodiment of the present invention. The computer-readable storage medium may include, e.g., magnetic or optical medium such as fixed or movable disks, magnetic tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW or Blue Ray disk. The computer-readable storage medium may include volatile or non-volatile storage medium, such as RAM, ROM, flash memory, USB memory, etc. The computer-readable storage medium may also include microelectromechanical system (MEMS), and storage medium accessible via communication media such as network or wireless link.

Embodiments of the present invention have been described in conjunction with the drawings. The above described embodiments are only illustrative but not intended to limit the scope of the present invention. Those skilled in the art may make various modifications, equivalent replacement and improvements without departing the spirit and principle of the present invention. The protection scope of the present invention are defined by the appended claims only.