Fin critical dimension loading optimization

This application claims priority to U.S. Provisional Patent Application Ser. No. 62/551,624 Entitled “Fin Critical Dimension Loading Optimization” and filed Aug. 29, 2017, the entire disclosure of which is hereby incorporated by reference.

The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, as fin-like field effect transistor (FinFET) technologies progress towards smaller feature sizes, FinFET fabrication processes are significantly constrained by decreasing process margins. In particular, where multiple fin densities are present, decreasing fin pitches and increasing fin heights prevent conventional etching processes from completely or sufficiently removing material between fins. Consequently, not all advantages of FinFET devices can be realized.

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A-1C , FIGS. 2A-2C , FIGS. 3A-3C , FIGS. 4A-4E , FIGS. 5A-5E , and FIGS. 6A-6E are fragmentary diagrammatic views of an integrated circuit device, in portion or entirety, at various fabrication stages according to various aspects of the present disclosure.

FIG. 7 is a flow chart of a method for fabricating an integrated circuit device according to various aspects of the present disclosure.

FIG. 8 is a fragmentary cross-sectional view of an integrated circuit device, in portion or entirety, according to various aspects of the present disclosure.

The present disclosure relates generally to integrated circuit devices, and more particularly, to fin-like field effect transistor (FinFET) devices.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.

FIGS. 1A-1C , FIGS. 2A-2C , FIGS. 3A-3C , FIGS. 4A-4E , FIGS. 5A-5E , and FIGS. 6A-6E are fragmentary diagrammatic views of an integrated circuit device 10 , in portion or entirety, at various fabrication stages according to various aspects of the present disclosure. Integrated circuit device 10 includes various device regions, such as a core region (often referred to as a logic region), a memory region (such as a static random access memory (SRAM) region), an analog region, a peripheral region (often referred to as an input/output (I/O) region), a dummy region, other suitable region, or combinations thereof. In the depicted embodiment, integrated circuit device 10 includes a core region 12 and an I/O region 14 , each of which can include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. As described herein, core region 12 and I/O region 14 each include one or more fin-like field effect transistors (FinFETs). Integrated circuit device 10 may be included in a microprocessor, a memory, and/or other integrated circuit device. In some implementations, integrated circuit device 10 may be a portion of an IC chip, a system on chip (SoC), or portion thereof. FIGS. 1A-1C , FIGS. 2A-2C , FIGS. 3A-3C , FIGS. 4A-4E , FIGS. 5A-5E , and FIGS. 6A-6E have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in integrated circuit device 10 , and some of the features described below can be replaced, modified, or eliminated in other embodiments of integrated circuit device 10 .

Turning to FIGS. 1A-1C , FIG. 1A is a top view of integrated circuit device 10 , FIG. 1B is a fragmentary cross-sectional view of integrated circuit device 10 along line 1 B- 1 B of FIG. 1A , and FIG. 1C is a fragmentary cross-sectional view of integrated circuit device 10 along line 1 C- 1 C of FIG. 1A . Core region 12 and I/O region 14 each include at least one fin structure disposed over a substrate (wafer) 16 . In the depicted embodiment, substrate 16 includes silicon. Alternatively or additionally, substrate 16 includes another elementary semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), SiPC, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. Alternatively, substrate 16 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. In some implementations, substrate 16 includes one or more group III-V materials. In some implementations, substrate 16 includes one or more group II-IV materials. Substrate 16 includes various doped regions (not shown) depending on design requirements of core region 12 and I/O region 14 . For example, core region 12 is an n-type device region, a p-type device region, or a combination thereof, and I/O region 14 is an n-type device region, a p-type device region, or a combination thereof. In some implementations, substrate 16 includes p-type doped regions (for example, p-type wells) doped with p-type dopants, such as boron, indium, other p-type dopant, or combinations thereof. In some implementations, substrate 16 includes n-type doped regions (for example, n-type wells) doped with n-type dopants, such as phosphorus, arsenic, other n-type dopant, or combinations thereof. In some implementations, substrate 16 includes doped regions formed with a combination of p-type dopants and n-type dopants. The various doped regions can be formed directly on and/or in substrate 16 , for example, providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or combinations thereof.

Core region 12 includes at least one fin structure having less than or equal to two fins, and I/O region 14 includes at least one fin structure having greater than or equal to three fins. For example, core region 12 includes a fin structure 20 A (having two fins 22 A) and a fin structure 20 B (having two fins 22 B), and I/O region 14 includes a fin structure 20 C (having six fins 22 C). Though fin structures 20 A- 20 C are multi-fin structures in the depicted embodiment, the present disclosure contemplates embodiments where fin structure 20 A and/or fin structure 20 B include only one fin. In the depicted embodiment, fin structures 20 A- 20 C belong respectively to a first FinFET device, a second FinFET device, and a third FinFET device of integrated circuit device 10 . Alternatively, in some implementations, fin structure 20 A and fin structure 20 B belong to a first FinFET device, and fin structure 20 C belongs to a second FinFET device. In some implementations, fins 22 A- 22 C are a portion of substrate 16 (such as a portion of a material layer of substrate 16 ). For example, where substrate 16 includes silicon, fins 22 A- 22 C include silicon. Alternatively, in some implementations, fins 22 A- 22 C are defined in a material layer, such as one or more semiconductor material layers, overlying substrate 16 . For example, fins 22 A- 22 C can include a semiconductor layer stack having various semiconductor layers (such as a heterostructure) disposed over substrate 16 . The semiconductor layers can include any suitable semiconductor materials, such as silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof. The semiconductor layers can include same or different materials, etching rates, constituent atomic percentages, constituent weight percentages, thicknesses, and/or configurations depending on design requirements of integrated circuit device 10 . In some implementations, the semiconductor layer stack includes alternating semiconductor layers, such as semiconductor layers composed of a first material and semiconductor layers composed of a second material. For example, the semiconductor layer stack alternates silicon layers and silicon germanium layers (for example, SiGe/Si/SiGe/Si/SiGe/Si from bottom to top). In some implementations, the semiconductor layer stack includes semiconductor layers of the same material but with alternating constituent atomic percentages, such as semiconductor layers having a constituent of a first atomic percent and semiconductor layers having the constituent of a second atomic percent. For example, the semiconductor layer stack includes silicon germanium layers having alternating silicon and/or germanium atomic percentages (for example, Si a Ge b /Si c Ge d /Si a Ge b /Si c Ge d /Si a Ge b /Si c Ge d from bottom to top, where a and c are different atomic percentages of silicon and b and d are different atomic percentages of germanium). In some implementations, fins 22 A, fins 22 B, and/or fins 22 C include the same materials and/or the same semiconductor layer stacks depending on design requirements of their respective FinFET device. In some implementations, fins 22 A, fins 22 B, and/or fins 22 C include different materials and/or different semiconductor layer stacks depending on design requirements of their respective FinFET device.

Fin critical dimension (CD) loading optimization is achieved between core region 12 and I/O region 14 for subsequent processing by configuring fin structures of core region 12 and I/O region 14 with different critical dimensions. In some implementations, a critical dimension generally refers to a dimension, such as a fin width and/or a fin pitch, defined by design requirements to achieve desired performance of integrated circuit device 10 . In FIGS. 1A-1C , fins 22 A each have a width w 1 , fins 22 B each have a width w 2 , and fins 22 C each have a width w 3 , where fin width is the critical dimension and widths w 1 , width w 2 , and width w 3 are configured to provide fin CD loading optimization. In some implementations, fin CD loading is defined as a difference between a core fin CD (or core fin width) of core region 12 and an I/O fin CD (or I/O fin width) of I/O region 14 . Fin CD loading optimizes fin-to-fin spacing for etching processes used during gate formation when fin CD loading is greater than 0 (in other words, fin CD loading=core fin CD−I/O fin CD>0). For example, where the core fin CD is greater than the I/O fin CD (in other words, fins 22 A and fins 22 B each have a width that is greater than a width of fins 22 C (for example, w 1 >w 3 and w 2 >w 3 )), a spacing S 1 (distance) between adjacent fins 22 A and/or a spacing S 2 between adjacent fins 22 B is less than a spacing S 3 between adjacent fins 22 C (in other words, S 1 <S 3 and S 2 <S 3 ). In some implementations, width w 1 is about 1 nm to about 30 nm, width w 2 is about 1 nm to about 30 nm, and width w 3 is about 1 nm to about 30 nm. In some implementations, spacing S 1 is about 10 nm to about 30 nm, spacing S 2 is about 10 nm to about 30 nm, and spacing S 3 is about 10 nm to about 30 nm. In furtherance of the depicted embodiment, fins 22 A and fins 22 B have substantially the same width (in other words, w 1 ≈w 2 ), and fins 22 A and fins 22 B have substantially the same spacing (in other words, S 1 ≈S 2 ) In some implementations, width w 1 and/or spacing S 1 of fins 22 A is different than width w 2 and/or spacing S 2 of fins 22 B depending on design requirements of core region 12 . In FIGS. 1A-1C , fins 22 A each have a height h 1 and a length l 1 ; fins 22 B each have a height h 2 and a length l 2 ; and fins 22 C each have a height h 3 and a length l 3 . In some implementations, height h 1 is about 30 nm to about 150 nm, height h 2 is about 30 nm to about 150 nm, and height h 3 is about 30 nm to about 150 nm. In some implementations, length l 1 is about 30 nm to about 60 nm, length l 2 is about 30 nm to about 60 nm, and length l 3 is about 30 nm to about 60 nm.

A pitch P 1 of fin structure 20 A generally refers to a sum of a width w 1 of fins 22 A and spacing between adjacent fins 22 A (such as S 1 ) (in other words, P 1 =w 1 +S 1 ). A pitch P 2 of fin structure 20 B generally refers to a sum of a width w 2 of fins 22 B and spacing between adjacent fins 22 B (such as S 2 ) (in other words, P 2 =w 2 +S 2 ). A pitch P 3 of fin structure 20 C generally refers to a sum of a width w 3 of fins 22 C and spacing between adjacent fins 22 C (such as S 3 ) (in other words, P 3 =w 3 +S 3 ). In the depicted embodiment, pitch P 1 , pitch P 2 , and pitch P 3 define a center-to-center distance between fins. In some implementations, pitch P 1 , pitch P 2 , and pitch P 3 are about 10 nm to about 80 nm. In some implementations, pitch P 1 is about 10 nm to about 600 nm, pitch P 2 is about 10 nm to about 600 nm, and pitch P 3 is about 10 nm to about 80 nm. In some implementations, fin structures 20 A- 20 C have about the same pitch. In some implementations, fin structures 20 A- 20 C have different pitches. In some implementations, pitch P 1 , pitch P 2 , and/or pitch P 3 is equivalent to a minimum fin pitch (P m ). In some implementations, the minimum fin pitch generally refers to a smallest fin pitch achievable by a lithography process and/or a fin fabrication process (including deposition, lithography, and/or etching processes) of a given IC technology node. In some implementations, the minimum fin pitch generally refers to a smallest fin pitch specified by design requirements for integrated circuit device 10 .

Each of fins 22 A- 22 C has an adjacent fin pitch, which can be configured to further optimize fin-to-fin spacing for etching processes used during gate formation in core region 12 and I/O region 14 . Adjacent fin pitch (P adjacent ) is a sum of a fin's right fin pitch (P R ) and a fin's left fin pitch (P L ). Right fin pitch P R defines a distance between a center of a fin and a center of an adjacent (neighboring) fin positioned to the right of the fin, and left fin pitch P L defines a distance between the center of the fin and a center of an adjacent (neighboring) fin positioned to the left of the fin. In some implementations, the fin and the adjacent fin belong to the same fin structure and/or the same FinFET device. In some implementations, the fin and the adjacent fin belong to different fin structures and/or different FinFET devices. Core region 12 includes fin structures having a core adjacent fin pitch (P adjacent-core ) that is greater than or equal to three times a minimum fin pitch (in other words, P adjacent-core ≥3P m ), and I/O region 14 includes fin structures having an I/O core adjacent fin pitch (P adjacent-IO ) that is less than or equal to two times a minimum fin pitch (in other words, P adjacent-IO ≤2P m ). For example, in core region 12 , the rightmost fin 22 A of fin structure 20 A has a left fin pitch that is equal to the minimum fin pitch (P L =P m ) and a right fin pitch that is equal to two minimum fin pitches (P R =2P m ), such that its adjacent fin pitch is equal to three times the minimum fin pitch (in other words, P adjacent-20A =P m +2P m =3P m ). In some implementations, the right fin pitch of the rightmost fin 22 C is greater than two times the minimum fin pitch and/or the left fin pitch of the rightmost fin 22 C is less than the minimum fin pitch. In contrast, in I/O region 14 , one of the center fins 22 C of fin structure 20 C has a left fin pitch that is equal to the minimum fin pitch (P L =P m ) and a right fin pitch that is equal to the minimum fin pitch (P R =P m ), such that its adjacent fin pitch is equal to two times the minimum fin pitch (in other words, P adjacent-20C =P m +P m =2P m ). In some implementations, the left fin pitch and/or the right fin pitch of the center fin 22 C is less than the minimum fin pitch. In the depicted embodiment, since fin structure 20 A and fin structure 20 B have less than or equal to two fins, fins 22 A and fins 22 B each have an adjacent fin pitch that defines the left fin pitch and/or the right fin pitch between a fin of a first FinFET device and a fin of a second FinFET device. In furtherance of the depicted embodiment, since fin structure 20 C has greater than or equal to three fins, center fins 22 C each have an adjacent fin pitch that defines the left fin pitch and the right fin pitch between fins of the same FinFET device.

The present disclosure contemplates variations in heights, widths, and/or lengths of fins 22 A- 22 C that may arise from processing and fabrication of integrated circuit device 10 . In the depicted embodiment, fins 22 A- 22 C have tapered widths along their respective heights, where width w 1 , width w 2 , and width w 3 each represent an average of the varying widths. For example, the widths of fins 22 A- 22 C decrease from lower portions of fins 22 A- 22 C to upper portions of fins 22 A- 22 C, such that average widths of the upper portions are less than average widths of the lower portions of fins 22 A- 22 C. In some implementations, the widths can vary from about 5 nm to about 15 nm along fins 22 A- 22 C depending on where the widths are measured along heights of fins 22 A- 22 C. In some implementations, fin width varies depending on a position of a fin relative to other fins and/or relative to other features of integrated circuit device 10 . For example, for fin structure 20 C, width w 3 of center fins (in the depicted embodiment, fin structure 20 C includes three center fins 22 C) is greater than width w 3 of edge fins 22 C (here, the leftmost fin 22 C and the rightmost fin 22 C enclosing the three center fins 22 C). In another example, alternatively, width w 3 of the center fins is less than width w 3 of the edge fins. In both such implementations, width w 3 is less than width w 1 and width w 2 . In furtherance of such implementations, width w 3 of the edge fins can represent an average width of the edge fins, and width w 3 of the center fins can represent an average width of the center fins. Though fins 22 A- 22 C are depicted as having tapered widths, in some implementations, fins 22 A- 22 C have substantially the same widths along their respective heights.

Fins 22 A- 22 C are formed over substrate 16 using any suitable process. In some implementations, a combination of deposition, lithography and/or etching processes are performed to define fins 22 A- 22 C extending from substrate 16 as illustrated in FIGS. 1A-1C . For example, forming fins 22 A- 22 C includes performing a lithography process to form a patterned resist layer over substrate 16 (or a material layer, such as a heterostructure, disposed over substrate 16 ) and performing an etching process to transfer a pattern defined in the patterned resist layer to substrate 16 (or the material layer, such as the heterostructure, disposed over substrate 16 ). The lithography process can include forming a resist layer on substrate 16 (for example, by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), where the mask blocks, transmits, and/or reflects radiation to the resist layer depending on a mask pattern of the mask and/or mask type (for example, binary mask, phase shift mask, or EUV mask), such that an image is projected onto the resist layer that corresponds with the mask pattern. Since the resist layer is sensitive to radiation energy, exposed portions of the resist layer chemically change, and exposed (or non-exposed) portions of the resist layer are dissolved during the developing process depending on characteristics of the resist layer and characteristics of a developing solution used in the developing process. After development, the patterned resist layer includes a resist pattern that corresponds with the mask. The etching process uses the patterned resist layer as an etch mask to remove portions of substrate 16 (or a material layer disposed over substrate 16 ). The etching process can include a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process, other suitable etching process, or combinations thereof. After the etching process, the patterned resist layer is removed from substrate 16 , for example, by a resist stripping process. Alternatively, fins 22 A- 22 C are formed by a multiple patterning process, such as a double patterning lithography (DPL) process (for example, a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) SADP process, other double patterning process, or combinations thereof), a triple patterning process (for example, a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning process, or combinations thereof), other multiple patterning process (for example, self-aligned quadruple patterning (SAQP) process), or combinations thereof. In some implementations, directed self-assembly (DSA) techniques are implemented while forming fins 22 A- 22 C. Further, in some implementations, the exposure process can implement maskless lithography, electron-beam (e-beam) writing, ion-beam writing and/or nanoprint technology for patterning the resist layer.

In some implementations, a pattern defined in the patterned resist layer (or patterned mask layer) includes first openings having a first width for defining fin structure 20 A and fin structure 20 B and second openings having a second width for defining fin structure 20 C, where the first width is greater than the second width. In such implementations, an etching process then uses the patterned resist layer as an etch mask to remove portions of substrate 16 (or a material layer disposed over substrate 16 ), such that fins 22 A- 22 C are fabricated having fin CD loading between core region 12 and I/O region 14 as described herein. In some implementations, a pattern defined in the patterned resist layer (or patterned mask layer) includes first openings, second openings, and third openings for defining fin structure 20 A, fin structure 20 B, and fin structure 20 C, where the first openings, second openings, and third openings have the same width. In such implementations, an etching process then uses the patterned resist layer as an etch mask to remove portions of substrate 16 (or a material layer disposed over substrate 16 ), such that fins 22 A- 22 C have the same width. In furtherance of such implementations, a trimming process is then performed to trim fin structure 20 C, thereby reducing a width of fins 22 C, such that fins 22 A- 22 C are fabricated having fin CD loading between core region 12 and I/O region 14 as described herein. The trimming process implements any suitable process for reducing the dimension of fins 22 C. For example, in some implementations, the trimming process includes an etching process that can selectively etch fins 22 C relative to other features of integrated circuit device 10 . The etching process is a dry etching process, a wet etching process, or combinations thereof. In some implementations, a wet etching process implements an etching solution that includes ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ), sulfuric acid (H 2 SO 4 ), tetramethylammonium hydroxide (TMAH), other suitable wet etching solution, or combinations thereof. For example, the wet etching solution can utilize an NH 4 OH:H 2 O 2 solution, an NH 4 OH:H 2 O 2 :H 2 O solution (known as an ammonia-peroxide mixture (APM)), or an H 2 SO 4 :H 2 O 2 solution (known as a sulfuric peroxide mixture (SPM)). In some implementations, a dry etching process implements an etchant gas that includes a fluorine-containing etchant gas (for example, CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), an oxygen-containing gas, a chlorine-containing gas (for example, Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), a bromine-containing gas (for example, HBr and/or CHBR 3 ), an iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof. In some implementations, the trimming process implements an oxidation process. For example, the trimming process can expose fins 22 C to an ozone environment, thereby oxidizing a portion of fins 22 C, which is subsequently removed by a cleaning process and/or an etching process.

Turning to FIGS. 2A-2C , FIG. 2A is a top view of integrated circuit device 10 , FIG. 2B is a fragmentary cross-sectional view of integrated circuit device 10 along line 2 B- 2 B of FIG. 2A , and FIG. 2C is a fragmentary cross-sectional view of integrated circuit device 10 along line 2 C- 2 C of FIG. 2A . Isolation feature(s) 30 is formed over and/or in substrate 16 to isolate various regions, such as various device regions, of integrated circuit device 10 . For example, isolation feature 30 separates and isolates core region 12 from I/O region 14 . Isolation feature 30 further separates and isolates fins 22 A- 22 C from one another. In the depicted embodiment, isolation feature 30 surrounds a bottom portion of fins 22 A- 22 C. Isolation feature 30 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (for example, including silicon, oxygen, nitrogen, carbon, or other suitable isolation constituent), or combinations thereof. Isolation feature 30 can include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and/or local oxidation of silicon (LOCOS) structures. In some implementations, STI features can be formed by depositing an insulator material over substrate 16 after forming fins 22 A- 22 C (in some implementations, such that the insulator material layer fills gaps (trenches) between fins 22 A- 22 C) and etching back the insulator material layer to form isolation feature 30 . In some implementations, STI features can be formed by etching a trench in substrate 16 (for example, by using a dry etch process and/or wet etch process) and filling the trench with insulator material (for example, by using a chemical vapor deposition process or a spin-on glass process). A chemical mechanical polishing (CMP) process may be performed to remove excessive insulator material and/or planarize a top surface of isolation feature 30 . In some implementations, isolation feature 30 includes a multi-layer structure that fills trenches, such as a bulk dielectric layer disposed over a liner dielectric layer, where the bulk dielectric layer and the liner dielectric layer include materials depending on design requirements (for example, a bulk dielectric layer that includes silicon nitride disposed over a liner dielectric layer that includes thermal oxide). In some implementations, isolation feature 30 includes a dielectric layer disposed over a doped liner layer (including, for example, boron silicate glass (BSG) or phosphosilicate glass (PSG)).

Turning to FIGS. 3A-3C , FIG. 3A is a top view of integrated circuit device 10 , FIG. 3B is a fragmentary cross-sectional view of integrated circuit device 10 along line 3 B- 3 B of FIG. 3A , and FIG. 3C is a fragmentary cross-sectional view of integrated circuit device 10 along line 3 C- 3 C of FIG. 3A . A gate layer 40 is formed over fin structures 20 A- 20 C disposed respectively in core region 12 and I/O region 14 . For example, at least one deposition process is performed to form gate layer 40 over substrate 16 , particularly over fin structures 20 A- 20 C and isolation feature 30 . Gate layer 40 fills spaces between fin structures 20 A- 20 C and fills spaces between fins 22 A- 22 C. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods, or combinations thereof. Thereafter, a CMP process may be performed to planarize a top surface of gate layer 40 . In the depicted embodiment, gate layer 40 includes a polysilicon layer. In some implementations, gate layer 40 further includes an interfacial layer (including a dielectric material, such as silicon oxide) disposed between fin structures 20 A- 20 C and the polysilicon layer. In some implementations, gate layer 40 is a dummy gate stack that includes a dummy gate electrode and a dummy gate dielectric layer. In such implementations, a deposition process is performed to form a dummy gate dielectric layer over substrate 16 , and a deposition process is performed to form a dummy gate electrode layer over the gate dielectric layer. In furtherance of such implementations, the dummy gate electrode includes polysilicon or other suitable dummy gate material, and the dummy gate dielectric includes a dielectric material (for example, silicon oxide), high-k dielectric material, other suitable dielectric material, or combinations thereof. Examples of high-k dielectric material include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy, other suitable high-k dielectric materials, or combinations thereof. Gate layer 40 may include numerous other layers, for example, capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In an example, a capping layer, such as a titanium nitride (TiN) capping layer, is disposed between the dummy gate dielectric (or substrate 16 where the dummy gate dielectric is omitted) and the dummy gate electrode.

Turning to FIGS. 4A-4C , FIG. 4A is a top view of integrated circuit device 10 , FIG. 4B is a fragmentary cross-sectional view of integrated circuit device 10 along line 4 B- 4 B of FIG. 4A , FIG. 4C is a fragmentary cross-sectional view of integrated circuit device 10 along line 4 C- 4 C of FIG. 4A , FIG. 4D is a fragmentary cross-sectional view of integrated circuit device 10 along line 4 D- 4 D of FIG. 4A , and FIG. 4E is a fragmentary cross-sectional view of integrated circuit device 10 along line 4 E- 4 E of FIG. 4A . In FIGS. 4A-4E , a patterning layer 50 is formed over gate layer 40 , where patterning layer 50 includes openings 52 that expose portions of gate layer 40 in core region 12 and openings 54 that expose portions of gate layer 40 in I/O region 14 . In the depicted embodiment, patterning layer 50 includes a mask layer 56 disposed over gate layer 40 , and a resist layer 58 (also referred to as a photoresist layer, photosensitive layer, imaging layer, patterning layer, or radiation sensitive layer) disposed over mask layer 56 . Mask layer 56 includes a material having a different etching rate than a material of gate layer 40 . For example, mask layer 56 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbon nitride, other suitable material, or combinations thereof. In some implementations, mask layer 56 includes a material that has a low etch rate relative to a material of gate layer 40 , such that gate layer 40 can be selectively etched relative to mask layer 56 . Mask layer 56 is formed by any suitable process, such as a CVD process, to any suitable thickness. In some implementations, a silicon-containing and nitrogen-containing mask layer is formed using LPCVD. In some implementations, a silicon-containing and nitrogen-containing mask layer is formed by performing a process that includes thermal nitridation of a silicon-containing layer. Resist layer 58 includes any suitable resist material. Patterning layer 50 is formed by a lithography patterning process, which includes resist coating (for example, spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing, rinsing, drying (for example, hard baking), other suitable processes, or combinations thereof. Alternatively, the lithography exposure process is assisted, implemented, or replaced by other methods, such as maskless lithography, electron-beam writing, or ion-beam writing. In yet another alternative, the lithography patterning process implements nanoimprint technology. In some implementations, the lithography process implements an etching process, such as a dry etching, wet etching, other etching method, or combinations thereof. A rinsing process, such as a de-ionized (DI) water rinse, may be performed on gate layer 40 before forming patterning layer 50 .

Turning to FIGS. 5A-5E , FIG. 5A is a top view of integrated circuit device 10 , FIG. 5B is a fragmentary cross-sectional view of integrated circuit device 10 along line 5 B- 5 B of FIG. 5A , FIG. 5C is a fragmentary cross-sectional view of integrated circuit device 10 along line 5 C- 5 C of FIG. 5A , FIG. 5D is a fragmentary cross-sectional view of integrated circuit device 10 along line 5 D- 5 D of FIG. 5A , and FIG. 5E is a fragmentary cross-sectional view of integrated circuit device 10 along line 5 E- 5 E of FIG. 5A . In FIGS. 5A-5E , an etching process is performed using patterning layer 50 as a mask to remove exposed portions of gate layer 40 , thereby forming gate structures 40 A- 40 H. The etching process can include a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process, other suitable etching process, or combinations thereof. The etching process is unable to completely remove exposed portions of gate layer 40 within openings 54 in I/O region 14 , leaving remaining gate layer portions 40 ′ disposed between fins 22 C. Gate structures 40 F- 40 H thus have widths that vary along their lengths and heights, while gate structures 40 A- 40 E have widths that are substantially the same along their lengths and heights. In FIG. 5A , along their length, a width of gate structures 40 F- 40 H disposed over fins 22 C is less than a width of gate structures 40 F- 40 H disposed between fins 22 C. Along their height, gate structures 40 F- 40 H have tapered widths. For example, in FIG. 5E , a portion of a gate structure 40 G disposed between fins 22 C has a width that decreases along its height, such that a width of the portion of gate structure 40 G proximate to isolation feature 30 (or substrate 16 ) is greater than a width of the portion of gate structure 40 G proximate to patterning layer 50 . In some implementations, a width of the portion of gate structure 40 G above a top surface of fin structure 22 C is substantially the same along its height, while a width the portion of gate structure 40 G below the top surface of fin structures 22 C decreases along its height. In conventional integrated circuit devices, where a core region and an I/O region have fin structures with substantially the same fin critical dimensions (widths), such remaining gate layer portions cause gate to source/drain breakdown, degrading device performance. In contrast, by implementing fin CD loading between core region 12 and I/O region 14 as described herein (and thus increasing fin spacing in I/O region 14 relative to fin spacing in core region 12 ), etch loading effects are minimized during the etching process, significantly reducing an amount (in particular, a thickness) of remaining gate layer portions 40 ′ compared to conventional integrated circuit devices. The disclosed fin CD loading enlarges a breakdown voltage (V BD ) window for I/O region 14 (for example, by increasing fin-to-fin spacing in I/O region 14 ) while maintaining smaller fin-to-fin spacing desired for boosting performance of core region 12 (for example, by having core fin CD that is greater than I/O fin CD). The V BD window for I/O region 14 is thus enlarged without impacting performance of core region 12 and/or without impacting the gate fabrication process (in particular, polysilicon etching processes). Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.

Turning to FIGS. 6A-6E , FIG. 6A is a top view of integrated circuit device 10 , FIG. 6B is a fragmentary cross-sectional view of integrated circuit device 10 along line 6 B- 6 B of FIG. 6A , FIG. 6C is a fragmentary cross-sectional view of integrated circuit device 10 along line 6 C- 6 C of FIG. 6A , FIG. 6D is a fragmentary cross-sectional view of integrated circuit device 10 along line 6 D- 6 D of FIG. 6A , and FIG. 6E is a fragmentary cross-sectional view of integrated circuit device 10 along line 6 E- 6 E of FIG. 6A . In FIGS. 6A-6C , after patterning layer 50 is removed from gate layer 40 , for example, by a resist stripping process, gate structures 40 A- 40 H are disposed over fins 22 A- 22 C. Gate structures 40 A- 40 H extend along the y-direction (for example, substantially perpendicular to fins 22 A- 22 C). In the depicted embodiment, gate structures 40 A- 40 E are disposed over fin structure 20 A and fin structure 20 B, such that gate structures 40 A- 40 E wrap a portion of fins 22 A and fins 22 B; and gate structures 40 F- 40 H are disposed over fin structure 20 C, such that gate structures 40 F- 40 H wrap a portion of fins 22 C. Gate structures 40 A- 40 H are active gate structures or dummy gate structures depending on design requirements of integrated circuit device 10 . “Active gate structure” generally refers to an electrically functional gate structure of integrated circuit device 10 , whereas “dummy gate structure” generally refers to an electrically non-functional gate structure of integrated circuit device 10 . In some implementations, a dummy gate structure mimics physical properties of an active gate structure, such as physical dimensions of the active gate structure, yet is inoperable (in other words, does not enable current to flow) in a FinFET. In some implementations, at least one of gate structures 40 A- 40 E wraps channel regions of fins 22 A and fins 22 B, thereby interposing source/drain regions of fins 22 A and fins 22 B; and at least one of gate structures 40 F- 40 H wraps channel regions of fins 22 C, thereby interposing source/drain regions of fins 22 C. In such implementations, the at least one of gate structures 40 A- 40 H engage the channel regions of fins 22 A- 22 C, such that current can flow between the source/drain regions of fins 22 A- 22 C during operation. In some implementations, gate structures 40 A- 40 H enable a substantially uniform processing environment, for example, enabling uniform epitaxial material growth in source/drain regions of fins 22 A- 22 C (for example, when forming epitaxial source/drain features), uniform etch rates in source/drain regions of fins 22 A- 22 C (for example, when forming source/drain recesses), and/or uniform, substantially planar surfaces (for example, by reducing (or preventing) CMP-induced dishing effects).

Integrated circuit device 10 can undergo further processing to complete fabrication. For example, in some implementations, gate spacers are formed adjacent to gate structures 40 A- 40 H. For example, the gate spacers are disposed adjacent to (for example, along sidewalls of) gate layer 40 . The gate spacers are formed by any suitable process and include a dielectric material. The dielectric material can include silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the depicted embodiment, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, can be deposited over substrate 16 and subsequently anisotropically etched to form the gate spacers. In some implementations, the gate spacers include a multi-layer structure, such as a first dielectric layer that includes silicon nitride and a second dielectric layer that includes silicon oxide. In some implementations, more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers, are formed adjacent to gate structures 40 A- 40 H. In such implementations, the various sets of spacers can include materials having different etch rates. For example, a first dielectric layer including silicon and oxygen (for example, silicon oxide) can be deposited over substrate 16 and subsequently anisotropically etched to form a first spacer set adjacent to gate structures 40 A- 40 H, and a second dielectric layer including silicon and nitrogen (for example, silicon nitride) can be deposited over substrate 16 and subsequently anisotropically etched to form a second spacer set adjacent to the first spacer set.

In some implementations, source/drain features, such as heavily doped source/drain regions and/or lightly doped source/drain (LDD) features, are formed in source/drain regions of fins 22 A- 22 C. In some implementations, epitaxial source features and epitaxial drain features (referred to as epitaxial source/drain features) are formed in source/drain regions of fins 22 A- 22 C. For example, a semiconductor material is epitaxially grown on exposed portions of fins 22 A- 22 C, forming epitaxial source/drain features. An epitaxy process can use CVD deposition techniques (for example, VPE and/or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxy process can use gaseous and/or liquid precursors, which interact with the composition of fins 22 A- 22 C. Epitaxial source/drain features are doped with n-type dopants and/or p-type dopants. In some implementations, epitaxial source/drain features are epitaxial layers including silicon and/or carbon, where silicon containing epitaxial layers or silicon carbon containing epitaxial layers are doped with phosphorous, other n-type dopant, or combinations thereof (for example, forming a Si:P epitaxial layer or a Si:C:P epitaxial layer). In some implementations, epitaxial source/drain features 260 are epitaxial layers including silicon and germanium, where the silicon germanium containing epitaxial layers are doped with boron, other p-type dopant, or combinations thereof (for example, forming a Si:Ge:B epitaxial layer). In some implementations, epitaxial source/drain features include materials and/or dopants that achieve desired tensile stress and/or compressive stress in channel regions of fins 22 A- 22 C. In some implementations, epitaxial source/drain features are doped during deposition by adding impurities to a source material of the epitaxy process. In some implementations, epitaxial source/drain features are doped by an ion implantation process subsequent to a deposition process. In some implementations, annealing processes are performed to activate dopants in epitaxial source/drain features and/or other source/drain regions of integrated circuit device 10 (for example, HDD regions and/or LDD regions formed in source/drain regions of fins 22 A- 22 C and/or epitaxial source/drain features).

A gate replacement process can then performed to replace a dummy gate stack of at least one of gate structures 40 A- 40 H with a gate, such as a metal gate stack. For example, an inter-level dielectric (ILD) layer can be formed over substrate 16 , for example, by a deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof). The ILD layer includes a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS formed oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB, SILK (Dow Chemical, Midland, Mich.), polyimide, other low-k dielectric material, or combinations thereof. The ILD layer can include a multilayer structure having multiple dielectric materials. Subsequent to the deposition of the ILD layer, a CMP process may be performed, such that a top portion of gate structures 40 A- 40 H is reached (exposed), such as a dummy gate electrode (for example, a polysilicon layer) of gate layer 40 . A portion of the at least one of gate structures 40 A- 40 H (such as the dummy gate electrode of gate layer 40 ) is then removed, thereby forming a trench (opening), which may expose an interfacial layer and/or gate dielectric. In some implementations, an etching process selectively removes the dummy gate electrode (and, in some implementations, a dummy gate dielectric). The etching process is a dry etching process, a wet etching process, or combinations thereof. A selective etching process can be tuned, such that the dummy gate electrode layer has an adequate etch rate relative to the interfacial layer, the spacers, and/or the ILD layer.

A metal gate stack of the at least one of gate structures 40 A- 40 H is then formed in the opening (trench). The metal gate stack of the at least one of gate structures 40 A- 40 H include a gate dielectric (for example, a gate dielectric layer) and a gate electrode (for example, a work function layer and a bulk (or fill) conductive layer). The gate stacks may include numerous other layers, for example, capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. The gate dielectric layer includes a dielectric material, such as silicon oxide, high-k dielectric material, other suitable dielectric material, or combinations thereof. Examples of high-k dielectric material include hafnium dioxide (HfO 2 ), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy, other suitable high-k dielectric materials, or combinations thereof. In some implementations, the gate dielectric layer is a high-k dielectric layer. The gate electrode includes a conductive material, such as polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), cobalt (Co), TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive material, or combinations thereof. In some implementations, the work function layer is a conductive layer tuned to have a desired work function (such as an n-type work function or a p-type work function), and the conductive bulk layer is a conductive layer formed over the work function layer. In some implementations, the work function layer includes n-type work function materials, such as Ti, silver (Ag), TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, manganese (Mn), zirconium (Zr), other suitable n-type work function materials, or combinations thereof. In some implementations, the work function layer includes a p-type work function material, such as TiN, TaN, ruthenium (Ru), Mo, Al, WN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , WN, other suitable p-type work function materials, or combinations thereof. The bulk conductive layer includes a suitable conductive material, such as Al, W, and/or Cu. In some implementations, the bulk conductive layer additionally or collectively includes polysilicon, Ti, Ta, metal alloys, other suitable materials, or combinations thereof. The gate dielectric layer, the work function layer, and the bulk conductive layer are formed by various deposition processes, such as ALD, CVD, PVD, and/or other suitable process. A CMP process can be performed to remove excess material (such as any excess work function layer and/or any excess metal fill layer), planarizing gate structures 40 A- 40 H. It is understood that gate structures 40 A- 40 H include gate stacks configured to achieve desired functionality according to design requirements of integrated circuit device 10 , such that gate structures 40 A- 40 H include the same or different layers and/or materials.

In some implementations, various contacts are formed to facilitate operation of integrated circuit device 10 . For example, additional ILD layers can be formed over substrate 16 (in the depicted embodiment, over the ILD layer and gate structures 40 A- 40 H). Contacts can be formed in the ILD layers, such as contacts that are electrically coupled with gate structures 40 A- 40 H and contacts that are electrically coupled with source/drain regions of fin structures 20 A- 20 C. The contacts include a conductive material, such as metal. Metals include aluminum, aluminum alloy (such as aluminum/silicon/copper alloy), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some implementations, the ILD layers and contacts are a portion of a multilayer interconnect (MLI) feature disposed over substrate 16 . The MLI feature electrically couples various components of integrated circuit device 10 , such that the various components are operable to function as specified by design requirements. The MLI feature can include a combination of metal layers and ILD layers configured to form vertical interconnect features, such as contacts and/or vias, and/or horizontal interconnect features, such as lines. The various conductive features include materials similar to the contacts. In some implementations, a damascene process and/or dual damascene process is used to form a copper-based multilayer interconnection structure. Integrated circuit device 10 can undergo subsequent processing to complete fabrication depending on design requirements.

FIG. 7 is a flow chart of a method 100 for fabricating an integrated circuit device, such as integrated circuit device 10 , according to various aspects of the present disclosure. At block 102 , method 100 includes forming a first multi-fin structure having a first critical dimension in a core region and a second multi-fin structure having a second critical dimension in an input/output region. The first critical dimension is greater than the second critical dimension. In some implementations, the first multi-fin structure and the second multi-fin structure are formed as disclosed with reference to FIGS. 1A-1C . At block 104 , method 100 includes forming a first gate structure over the first multi-fin structure and a second gate structure over the second multi-fin structure. In some implementations, the first gate structure and the second gate structure are formed as disclosed with reference to FIGS. 2A-2C , FIGS. 3A-3C , FIGS. 4A-4E , FIGS. 5A-5E , and FIGS. 6A-6E . At block 106 , method 100 can continue to complete fabrication of the FinFET device. For example, in implementations where the first gate structure and/or the second gate structure include a dummy gate, a gate replacement process is performed to replace the dummy gate(s) with a metal gate(s). Additional steps can be provided before, during, and after method 100 , and some of the steps described can be moved, replaced, or eliminated for additional embodiments of method 100 .

FIG. 8 is a fragmentary cross-sectional view of an integrated circuit device 200 , in portion or entirety, according to various aspects of the present disclosure. Integrated circuit device 200 may be included in a microprocessor, a memory, and/or other integrated circuit device. In some implementations, integrated circuit device 200 is a portion of an IC chip, a SoC, or portion thereof, that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. FIG. 8 has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in integrated circuit device 200 , and some of the features described below can be replaced, modified, or eliminated in other embodiments of integrated circuit device 200 .

In FIG. 8 , integrated circuit device 200 includes a substrate 116 , similar to substrate 16 of integrated circuit device 10 described in detail above with reference to FIGS. 1A-1C . Integrated circuit device 200 further includes a fin structure 220 A, a fin structure 220 B (including fins 222 B), and a fin structure 220 C (including fins 222 C). Fin structure 220 A is disposed between fin structure 220 B and fin structure 220 C. In the depicted embodiment, fin structure 220 A is a dense fin structure (for example, having greater than or equal to three fins), and fin structure 220 B and fin structure 220 C are isolated fin structures (for example, having less than or equal to two fins). Though fin structures 220 A- 220 C are multi-fin structures in the depicted embodiment, the present disclosure contemplates embodiments where fin structure 220 B and/or fin structure 220 C include only one fin. The present disclosure further contemplates embodiments where fin structure 220 A includes more or less fins than depicted in FIG. 8 . In some implementations, fin structures 220 A- 220 C belong to different FinFET devices of integrated circuit device 200 . In some implementations, fin structures 220 A- 220 C belong to the same FinFET device of integrated circuit device 200 . In some implementations, fin structures 220 A- 220 C belong to different regions of integrated circuit device 200 . For example, in some implementations, fin structure 220 A is disposed in an I/O region of integrated circuit device 200 , and fin structure 220 B and/or fin structure 220 C are disposed in a core region of integrated circuit device 200 .

Fin structure 220 A has inter-fins 222 A- 1 and intra-fins 222 A- 2 , where intra-fins 222 A- 2 are disposed between inter-fins 222 A- 2 . In the depicted embodiment, inter-fins 22 A- 1 are the outermost fins of fin structure 220 A, and intra-fins 222 A- 2 are the inner fins of fin structure 220 A. In some implementations, an intra-fin generally refers to a fin disposed between fins of the same fin structure (here, fin structure 220 A), whereas an inter-fin generally refers to a fin disposed between a fin of the same fin structure (or FinFET device) and a fin of a different fin structure (or FinFET device) (here, fin structure 220 B or fin structure 220 C). In some implementations, an intra-fin generally refers to a fin disposed between fins that share a gate structure and/or a source/drain feature, whereas an inter-fin generally refers to a fin disposed between fins that do not share a gate structure and/or a source/drain feature.

Fin CD loading optimization is achieved between inter-fins 222 A- 1 and intra-fins 222 A- 2 by configuring fin structure 220 A with different critical dimensions. In the depicted embodiment, inter-fins 222 A- 1 have an inter-fin CD and intra-fins 222 A- 2 have an intra-fin CD, where the inter-fin CD is greater than the intra-fin CD. In some implementations, fin CD loading for a dense fin structure is defined as a difference between inter-fin CD and intra-fin CD, and fin CD loading optimizes fin-to-fin spacing for etching processes used during gate formation when fin CD loading is greater than 0 (in other words, dense fin CD loading=inter-fin CD−intra-fin CD>0). For example, inter-fins 222 A- 1 each have a width w inter , and intra-fins 222 A- 2 each have a width w intra . When, as in the depicted embodiment, inter-fins 222 A- 1 have a width that is greater than a width of intra-fins 222 A- 2 (in other words, w inter >w intra ), a spacing S 1 (distance) between intra-fins 222 A- 2 is less than a spacing S 2 between inter-fins 222 A- 1 and intra-fins 222 A- 2 (in other words, S 1 <S 2 ). In some implementations, width w inter is about 1 nm to about 30 nm, and width w intra is about 1 nm to about 30 nm. In some implementations, spacing S 1 is about 10 nm to about 30 nm, and spacing S 2 is about 10 nm to about 30 nm. Inter-fins 222 A- 1 each have a height h inter , and intra-fins 222 A- 2 each have a height h intra . In some implementations, height h inter is nm, about 30 nm to about 150 and height h intra is about 30 nm to about 150 nm. A pitch P of fin structure 220 A generally refers to a sum of a width w of fins (collectively including inter-fins 222 A- 1 and intra-fins 222 A- 2 ) and spacing S between adjacent fins (in other words, P=w+S). In the depicted embodiment, a pitch P intra of fin structure 220 A generally refers to a center-to-center distance between intra-fins 222 A- 2 , and a pitch P inter of fin structure 220 A generally refers to a sum of a center-to-center distance between one of inter-fins 222 A- 1 and adjacent intra-fin 222 A- 2 . In some implementations, pitch P intra is about 10 nm to about 50 nm, and pitch P inter is about 30 nm to about 600 nm. In some implementations, pitch P intra and pitch P inter are the same (for example, P intra =P intra ). In some implementations, pitch P m , and pitch P inter are different. For example, in some implementations, pitch P intra is greater than pitch P inter . In some implementations, pitch P intra and/or pitch P inter is equivalent to a minimum fin pitch (P m ). In some implementations, the minimum fin pitch generally refers to a smallest fin pitch achievable by a lithography process and/or a fin fabrication process (including deposition, lithography, and/or etching processes) of a given IC technology node. In some implementations, the minimum fin pitch generally refers to a smallest fin pitch specified by design requirements for integrated circuit device 200 .

In furtherance of the depicted embodiment, inter-fins 222 A- 1 have an inter-fin adjacent pitch (P adjacent-inter ) and intra-fins 222 A- 2 have an intra-fin adjacent pitch (P adjacent-ultra ), which can be configured to further optimize fin-to-fin spacing for etching processes used during gate formation as described above. Inter-fin adjacent pitch is a sum of an inter-fin's right fin pitch and an inter-fin's left fin pitch. An inter-fin's right fin pitch (P R-inter ) defines a distance between a center of an inter-fin and a center of an adjacent (neighboring) fin positioned to the right of the fin, and an inter-fin's left fin pitch (P L-inter ) defines a distance between the center of the inter-fin and a center of an adjacent (neighboring) fin positioned to the left of the fin. One of the inter-fin left fin pitch or the inter-fin right fin pitch is defined between an inter-fin and an intra-fin of the same fin structure, while the other of the inter-fin left fin pitch or the inter-fin right fin pitch is defined between the inter-fin and a fin of a different fin structure. Intra-fin adjacent pitch is a sum of an intra-fin's right fin pitch and an intra-fin's left fin pitch. An intra-fin's right fin pitch (P R-intra ) defines a distance between a center of an intra-fin and a center of an adjacent (neighboring) intra-fin positioned to the right of the intra-fin, and an intra-fin's left fin pitch (P L-intra ) defines a distance between the center of the intra-fin and a center of an adjacent (neighboring) intra-fin positioned to the left of the intra-fin. The intra-fin left fin pitch and the intra-fin right fin pitch are defined between fins of the same fin structure. In the depicted embodiment, inter-fins 222 A- 1 have an inter-fin adjacent pitch that is greater than or equal to three times a minimum fin pitch (in other words, P adjacent-inter ≥3P m ), and intra-fins 222 A- 2 have an intra-fin adjacent pitch that is less than or equal to two times a minimum fin pitch (in other words, P adjacent-intra ≤2P m ). For example, the leftmost inter-fin 222 A- 1 of fin structure 220 A has a left fin pitch that is equal to two minimum fin pitches (P L-inter =2P m ) and a right fin pitch that is equal to the minimum fin pitch (P R-inter =P m ), such that inter fin adjacent fin pitch is equal to three times the minimum fin pitch (in other words, P adjacent-inter =2P m +P m =3P m ). In some implementations, the left fin pitch of the leftmost inter-fin 222 A- 1 is greater than two times the minimum fin pitch and/or the left fin pitch of the leftmost inter-fin 222 A- 1 is less than the minimum fin pitch. In contrast, one of intra-fins 222 A- 2 has a left fin pitch that is equal to the minimum fin pitch (P L-intra =P m ) and a right fin pitch that is equal to the minimum fin pitch (P R-intra =P m ), such that intra-fin adjacent fin pitch is equal to two times the minimum fin pitch (in other words, P adjacent-intra =P m +P m =2P m ). In some implementations, the left fin pitch and/or the right fin pitch of intra-fin 222 A- 2 is less than the minimum fin pitch.

The present disclosure contemplates variations in heights, widths, and/or lengths of inter-fins 222 A- 1 and intra-fins 222 A- 2 that may arise from processing and fabrication of integrated circuit device 200 . In the depicted embodiment, inter-fins 222 A- 1 and intra-fins 222 A- 2 have tapered widths along their respective heights, where width w intra and width w intra each represent an average of the varying widths. For example, the widths of inter-fins 222 A- 1 and/or intra-fins 222 A- 2 decrease from lower portions of inter-fins 222 A- 1 and/or intra-fins 222 A- 2 to upper portions of inter-fins 222 A- 1 and/or intra-fins 222 A- 2 , such that average widths of the upper portions are less than average widths of the lower portions. In some implementations, the widths can vary from about 5 nm to about 15 nm along inter-fins 222 A- 1 and/or intra-fins 222 A- 2 depending on where the widths are measured along heights of inter-fins 222 A- 1 and intra-fins 222 A- 2 . Though inter-fins 222 A- 1 and intra-fins 222 A- 2 are depicted as having tapered widths, in some implementations, inter-fins 222 A- 1 and/or intra-fins 222 A- 2 have substantially the same widths along their respective heights.

The present disclosure provides for many different embodiments. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width, where the first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing, where the first fin spacing is less than the second fin spacing. In some implementations, the first multi-fin structure has less than or equal to two fins, and the second multi-fin structure has greater than or equal to three fins. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch. In some implementations, the first multi-fin structure and the second multi-fin structure include fins having tapered widths.

In some implementations, the second multi-fin structure includes an inter-fin having an inter-fin width and an intra-fin having an intra-fin width, where the inter-fin width is greater than the inter-fin width. In some implementations, the inter-fin has an inter-fin adjacent fin pitch that is greater than or equal to three times a minimum fin pitch. In some implementations, the intra-fin has an intra-fin adjacent fin pitch that is less than or equal to two times the minimum fin pitch. In some implementations, the integrated circuit device further includes a first gate structure disposed over the first multi-fin structure and a second gate structure disposed over the second multi-fin structure. In some implementations, the core region further includes a third multi-fin structure having a third width that is greater than the second width, and further wherein a spacing between the first multi-fin structure and the third multi-fin structure is greater than or equal to two times a minimum fin pitch.

Another exemplary integrated circuit device includes a multi-fin structure disposed over a substrate, where the multi-fin structure includes intra-fins disposed between inter-fins. The inter-fins have an inter-fin width and the intra-fins have an intra-fin width, where the inter-fin width is greater than the inter-fin width. The inter-fins have an inter-fin adjacent fin pitch that is greater than or equal to three times a minimum fin pitch. The intra-fins have an intra-fin adjacent fin pitch that is less than or equal to two times the minimum fin pitch. In some implementations, the multi-fin structure is disposed in an input/output region. In some implementations, the intra-fin adjacent pitch includes a first pitch between a first intra-fin of the intra-fins and a second intra-fin of the intra-fins and a second pitch between the first intra-fin and a third intra-fin of the intra-fins. In such implementations, the first pitch and the second pitch are equal to the minimum fin pitch. In some implementations, the integrated circuit device further includes a gate structure disposed over the multi-fin structure, wherein the gate structure traverses the multi-fin structure. In some implementations, the inter-fins and the intra-fins have tapered widths. In some implementations, the integrated circuit device further includes the multi-fin structure is disposed in a first region. In such implementations, the inter-fin adjacent pitch includes a first pitch between an inter-fin of the inter-fins and an adjacent intra-fin of the intra-fins and a second pitch between the inter-fin and a fin disposed in a second region that is adjacent to the first region. The first pitch is equal to the minimum fin pitch. The second pitch is greater than or equals two times the minimum fin pitch. In some implementations, the first region is an input/output region and the second region is a logic region.

An exemplary method includes forming a first multi-fin structure in a core region, forming a second multi-fin structure in a peripheral region, and forming a first gate structure over the first multi-fin structure and a second gate structure over the second multi-fin structure. The first multi-fin structure has a first width. The second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has less than or equal to two fins and the second multi-fin structure has greater than or equal to three fins. In some implementations, a first adjacent fin pitch of the first multi-fin structure is at least three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch. In some implementations, the first multi-fin structure and the second multi-fin structure are formed at the same time. In some implementations, the forming the first multi-fin structure and the forming the second multi-fin structure includes forming a patterned mask layer over a substrate, where the patterned mask layer includes first openings for defining the first multi-fin structure and second openings for defining the second multi-fin structure, and etching the substrate exposed by the first openings and the second openings in the patterned mask layer. In some implementations, the first gate structure and the second gate structure include dummy gates, and the method further includes replacing the dummy gates with metal gates.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.