Low-power wide-swing sense amplifier with dynamic output stage biasing

This application relates to a wide-swing sense amplifier, and more particularly to a low-power wide-swing sense amplifier with dynamic output stage biasing.

An analog phase-locked loop (PLL) includes a charge pump that is driven by a phase detector with up and down signals. The charge pump typically includes a PMOS switch transistor that switches on responsive to an assertion of the up signal so that a PMOS current source transistor sources a current through the PMOS switch transistor to charge a control voltage at a drain terminal of the PMOS switch transistor. Such a charge pump will also include an NMOS switch transistor that switches on responsive to an assertion of the down signal so that an NMOS current source transistor sinks a current through the NMOS switch transistor to discharge the control voltage since a drain terminal for the NMOS switch transistor is connected to the drain terminal for the PMOS switch transistor. When the PMOS switch transistor is not switched on because the up signal is not asserted, a drain terminal for the PMOS current source transistor is charged to a power supply voltage. Conversely, when the NMOS switch transistor is not switched on because the down signal is not asserted, a drain terminal for the NMOS current source transistor drain is discharged. These charged drain terminals for the current source transistors then engage in charge sharing with a loop filter for the PLL when their switch transistors are switched on. The resulting charge sharing disturbs the control voltage and lowers the PLL performance.

To mitigate such charge sharing, it is conventional to keep the drain terminal voltages for the current source transistors charged to the control voltage by arranging the switch transistors in parallel with duplicate switch transistors that are driven by a complement of the corresponding up or down signals. It thus doesn't matter whether the up or down signal is asserted since either the original switch transistor or its duplicate will always be on. An operational amplifier (op-amp) maintains the drains of the duplicate PMOS and NMOS switch transistors to equal the control voltage so that the loop filter is not affected by charge sharing. But high-speed operation of a PLL results in a wide swing for the control voltage such that it may range rail to rail (from ground to the power supply voltage). The resulting op-amp must then also be wide swing. In addition, the op-amp must be able to source or sink a relatively large current to adequately support the PLL operation. But conventional op-amps such as a class AB operational amplifier 100 (which may also be denoted as a sense amplifier 100 ) shown in FIG. 1 have difficultly satisfying such output current and wide swing demands. As is known in the wide-swing sense amplifier arts, sense amplifier 100 includes not only a PMOS differential pair of transistors P 1 and P 2 but also an NMOS differential pair of transistors M 1 and M 2 . A differential input voltage formed by the difference between an input voltage inp and an input voltage inn drives the two complementary differential pairs of transistors. In particular, input voltage inp drives the gates of transistors P 1 and M 1 whereas input voltage inn drives the gates of transistors P 2 and M 2 . A current source 105 biases the sources of transistors P 1 and P 2 . Similarly, a current source 125 biases the sources of transistors M 1 and M 2 .

A class AB output stage for sense amplifier 100 is formed by a PMOS output transistor P 4 and an NMOS output transistor M 4 . A biasing network responds to the currents in the differential pairs to drive the gate of output transistor P 4 with a pgate drive voltage and to drive the gate of output transistor M 4 with an ngate drive voltage. In particular, the biasing network includes a diode-connected PMOS transistor P 6 coupled between a power supply node for the power supply voltage VCC and the drain of differential pair transistor M 1 . The gate (and drain) of diode-connected transistor P 6 connects to the gate of a PMOS transistor P 5 having its source tied to the power supply node and a drain connected to the drain of differential pair transistor P 2 . Diode-connected transistor P 6 and transistor P 5 thus form a current mirror so that transistor P 5 conducts a mirrored-version of the current conducted by differential pair transistor M 1 . An NMOS diode-connected transistor M 6 couples between the drain of differential pair transistor P 2 and ground. Diode-connected transistor M 6 thus conducts a sum current that equals a sum of the currents conducted by differential pair transistors M 1 and P 2 . Diode-connected transistor M 6 forms a current mirror with an NMOS transistor M 8 having its source tied to ground and a drain tied to an ngate node at the gate of output transistor M 4 . Transistor M 8 will thus sink a mirrored version of the sum current conducted by diode-connected transistor P 6 from the ngate node for transistor M 4 , which causes a discharge of the ngate drive voltage.

The biasing network includes analogous circuitry to source a sum current to the gate of output transistor P 4 to charge the pgate drive voltage. In particular, the drain of differential pair transistor P 1 couples to ground through an NMOS diode-connected transistor M 5 that forms a current mirror with an NMOS transistor M 7 having its source tied to ground and a drain tied to the drain of differential pair transistor M 2 . The drain of differential pair transistor M 2 couples to the power supply node through a PMOS diode-connected transistor P 7 . Diode-connected transistor P 7 will thus conduct a sum current equaling the sum of the currents conducted by differential pair transistors P 1 and M 2 . Diode-connected transistor P 7 forms a current mirror with a PMOS transistor P 8 having its source tied to the power supply node and its drain tied to the pgate node at the gate of output transistor P 4 . Transistor P 8 will thus source a mirrored-version of the sum current conducted by diode-connected transistor P 7 into the gate of output transistor P 4 to charge the pgate drive voltage.

The wide swing or rail-to-rail performance is given by the complementary differential pairs. For example, as the common mode for input voltages inp and inn rises toward the power supply voltage, the PMOS differential pair of transistors P 1 and P 2 switch off. The feedback through sense amplifier 100 causes the ngate drive voltage to discharge such that output transistor M 4 is switched off. The biasing network also includes a PMOS transistor P 3 and an NMOS transistor M 3 coupled in parallel between the gates of output transistors P 4 and M 4 . Transistor M 3 is biased by a bias voltage nbias such that it switches on as the ngate drive voltage is discharged to also discharge the pgate drive voltage. This discharge of the pgate drive voltage switches on output transistor P 4 so that an output voltage (Vout) at the drains of output transistors P 4 and M 4 may be charged towards the power supply voltage VCC. But due to offsets in the differential pair of transistors M 1 and M 2 , the pgate drive voltage cannot be pulled sufficiently low enough to fully drive output transistor P 4 in the deep triode region as the output voltage approaches the power supply voltage VCC. A similar offset in the differential pair of transistors P 1 and P 2 affects the output voltage when the common mode for input voltages inp and inn is discharged. In that case, differential pair transistors M 1 and M 2 are switched off. Feedback through sense amplifier 100 then charges the pgate drive voltage towards the power supply voltage. Transistor P 3 is biased by a bias voltage pbias such that it switches on to charge the ngate drive voltage ngate as the pgate drive voltage is charged. The output transistor M 4 is thus switched on while output transistor P 4 is switched off to discharge the output voltage. But again due to an offset voltage between differential pair transistors P 1 and P 2 , the ngate drive voltage cannot be driven sufficiently high enough to fully drive output transistor M 4 on in the deep triode region. It is thus conventional to oversize output transistors M 4 and P 4 so that they can conduct the required amount of currents at these corner conditions. The quiescent current consumption is then increased, which hampers low power operation.

Accordingly, there is a need in the art for wide swing sense amplifiers with reduced power consumption.

A wide-swing sense amplifier is provided with a first current differential amplifier for an NMOS differential pair of transistors and with a second current differential amplifier for a PMOS differential pair of transistors. The first current differential amplifier sinks a first difference current from a gate of a PMOS output transistor while a common mode for a differential input voltage is charged towards the power supply voltage to enhance the response to such a high common mode value. The first difference current is proportional to a difference between a first current through a first one of the NMOS transistors in the NMOS differential pair and a second current through a second one of the NMOS transistors in the NMOS differential pair. Similarly, the second current differential amplifier sources a second difference current to a gate of an NMOS output transistor while the common mode is discharged towards ground. The second difference current is proportional to a difference between a third current through a first one of the PMOS transistors in the PMOS differential pair and a fourth current through a second one of the PMOS transistors in the PMOS differential pair. The PMOS output transistor and the NMOS output transistor are arranged in series in an amplifier output stage to produce an output voltage at their drains.

The first and second current differential amplifiers enhance the ability of the wide-swing sense amplifier to drive the output voltage towards either rail (the power supply voltage or ground) while sourcing or sinking a desired amount of current. In this fashion, low power operation is improved since the PMOS and NMOS output transistors need not be oversized to conduct a sufficient amount of current yet rail to rail performance is improved.

These and other advantageous features may be better appreciated through the following detailed description.

FIG. 1 is a circuit diagram of a conventional wide-swing sense amplifier.

FIG. 2A and FIG. 2B illustrate a wide-swing sense amplifier in accordance with an aspect of the disclosure.

FIG. 3 illustrates the integration of the wide-swing sense amplifier of FIGS. 2A and 2B in a PLL.

FIG. 4 is a flowchart for a method of operation for a wide-swing sense amplifier in accordance with an aspect of the disclosure.

Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

A sense amplifier is provided with complementary differential pairs of transistors (a PMOS pair and an NMOS pair) arranged in parallel between a dynamically-adjusted biasing network and an amplifier output stage to have reduced power consumption yet have wide swing for its output voltage. As a common mode for a differential input voltage driving the gates of the transistors in the differential pairs is charged toward a power supply voltage, the differential pair of PMOS transistors becomes inactive such that only the differential pair of NMOS transistors conducts current to discharge a gate of a PMOS output transistor in the amplifier output stage through the biasing network. The biasing network includes a first current differential amplifier that amplifies a difference between the drain currents conducted by the differential pair of NMOS transistors. The amplified difference current from the first current differential amplifier sinks from the gate of the PMOS output transistor through a pair of NMOS switch transistors controlled by the differential input voltage to assist the discharge of the gate of the PMOS output transistor. The resulting sense amplifier may thus source sufficient current through the PMOS output transistor despite an output voltage at the drain of the PMOS output transistor being charged towards the power supply voltage.

Similarly, as a common mode for the differential input voltage is discharged towards ground, the differential pair of NMOS transistors becomes inactive such that only the differential pair of PMOS transistors conducts current to charge a gate of an NMOS output transistor in the output stage (e.g., a class AB output stage) through the biasing network. The biasing network includes a second current differential amplifier that amplifies a difference between the drain currents conducted by the differential pair of PMOS transistors. The amplified difference current from the second current differential amplifier sources to the gate of the NMOS output transistor through a pair of PMOS switch transistors controlled by the differential input voltage to assist the charging of the gate of the NMOS output transistor. The sense amplifier may thus sink sufficient current through the NMOS output transistor despite an output voltage at the drain of the NMOS output transistor being discharged towards ground. The output voltage may thus be wide swing (from ground to the power supply voltage) yet the output transistors need not be oversized so as to conduct a sufficient amount of current at these corner conditions.

An example sense amplifier 200 is shown in FIG. 2A and in FIG. 2B . The connections between FIGS. 2A and 2B are indicated by nodes A, B, C, and D. As discussed with regard to conventional sense amplifier 100 , sense amplifier 200 includes the PMOS differential pair of transistors P 1 and P 2 and the NMOS differential pair of transistors M 1 and M 2 . The differential input voltage inp and inn drives the gates for the two complementary differential pairs of transistors. In particular, input voltage inp drives the gates of differential pair transistors P 1 and M 1 whereas input voltage inn drives the gates of differential pair transistors P 2 and M 2 . Current source 105 biases the sources of differential pair transistors P 1 and P 2 . Similarly, current source 125 biases the sources of differential pair transistors M 1 and M 2 .

As also discussed with regard to sense amplifier 100 , the class AB output stage for sense amplifier 200 is formed by a PMOS output transistor P 4 and an NMOS output transistor M 4 . A biasing network for biasing output transistors P 4 and M 4 in response to the currents in the differential pair transistors includes diode-connected PMOS transistor P 6 coupled between a power supply node for the power supply voltage VCC and the drain of differential pair transistor M 1 . The gate (and drain) of diode-connected transistor P 6 connects to the gate of PMOS transistor P 5 having its source tied to the power supply node and a drain connected to the drain of differential pair transistor P 2 . Diode-connected transistor P 6 and transistor P 5 thus form a current mirror so that transistor P 5 conducts a mirrored-version of the current conducted by differential pair transistor M 1 . NMOS diode-connected transistor M 6 couples between the drain of differential pair transistor P 2 and ground. Diode-connected transistor M 6 thus conducts a sum current that equals or is proportional to a sum of the currents conducted by differential pair transistors M 1 and P 2 . Diode-connected transistor M 6 forms a current mirror with NMOS transistor M 8 having its source tied to ground and a drain tied to the gate of output transistor M 4 . Transistor M 8 will thus sink a mirrored version of the sum current conducted by diode-connected transistor M 6 from the ngate node at the gate of transistor M 4 , which causes a discharge of the ngate drive voltage.

The biasing network includes analogous circuitry to source a sum current to the gate of output transistor P 4 to charge the pgate drive voltage. In particular, the drain of differential pair transistor P 1 couples to ground through NMOS diode-connected transistor M 5 that forms a current mirror with NMOS transistor M 7 having its source tied to ground and a drain tied to the drain of differential pair transistor M 2 . The drain of differential pair transistor M 2 couples to the power supply node through PMOS diode-connected transistor P 7 . Diode-connected transistor P 7 will thus conduct a sum current equaling the sum of the currents conducted by differential pair transistors P 1 and M 2 . Diode-connected transistor P 7 forms a current mirror with PMOS transistor P 8 having its source tied to the power supply node and drain tied to the gate of output transistor P 4 . Transistor P 8 will thus source a mirrored-version of the sum current conducted by diode-connected transistor P 7 into the pgate node at the gate of output transistor P 4 to charge the pgate drive voltage. Transistors M 3 and P 3 couple in parallel between the gates of output transistors P 4 and M 4 as discussed above. Transistors M 3 , P 3 , M 5 , M 6 , P 5 , P 6 , P 7 , M 7 , P 8 , M 9 may be deemed to form a means for biasing the gate voltage for the NMOS output transistor M 4 responsive to a sum of the currents in the differential pair transistors P 2 and M 1 and for biasing a gate voltage for the PMOS output transistor responsive to a sum of the currents in the differential pair transistors P 1 and M 2 .

Should the common mode for the input voltages inp and inn rise above a first threshold voltage toward the power supply voltage, differential pair transistors P 1 and P 2 substantially switch off such that the sum circuit conducted by diode-connected transistor M 6 equals just the drain current I 1 conducted by differential pair transistor M 1 . Transistor M 8 thus drains a mirrored version of current I 1 from the node for the ngate drive voltage such that it discharges towards ground. The discharge of the ngate drive voltage switches off output transistor M 4 and lowers the source of transistor M 3 with regard to the nbias voltage on its gate so that transistor M 3 switches on to pull the pgate drive voltage low as well. To assist the discharge of the pgate drive voltage, sense amplifier 200 includes a first current differential amplifier 220 that amplifies a difference between the drain currents I 1 and I 2 for differential pair transistors M 1 and M 2 , respectively.

As will be explained further herein, the input voltage inp for sense amplifier 200 may be the control voltage (Vctrl) for a PLL's charge pump. In such an embodiment, the output voltage (Vout) for sense amplifier 200 would also be the input voltage inn. As discussed earlier, the control voltage for a high speed PLL may range from rail to rail (from ground to the power supply). But a conventional sense amplifier such as sense amplifier 100 cannot push the output voltage Vout rail to rail while conducting the desired amount of current without oversizing output transistors P 4 and M 4 and thus increasing the power consumption. Differential input voltage inp will thus always be more positive than differential input voltage inn as the common mode for the differential input voltage rises towards the power supply voltage such that current I 1 will be greater than current I 2 at this corner condition. First current differential amplifier 220 is thus configured to only amplify the difference between currents I 1 and I 2 should I 1 be bigger than I 2 .

First current differential amplifier 220 amplifies the difference between currents I 1 and I 2 and sinks the resulting current from the node for the pgate drive voltage. The output current from first current differential amplifier 220 is gated by a parallel combination of an NMOS transistor M 15 and an NMOS transistor M 16 that have their gates driven by the input voltages inn and inp, respectively. Transistors M 15 and M 16 thus act as switches that are switched on should the common mode for input voltages inp and inn rise towards the power supply voltage. The resulting sinking of the amplified difference current from the node for the pgate drive voltage is quite advantageous as the pgate drive voltage may then be further reduced as the common mode voltage rises towards the supply rail. Output transistor P 4 may then be more fully switched on in the deep triode mode of operation as its drain voltage rises towards the power supply voltage (VCC) at its source. In this fashion, sense amplifier 200 may source sufficient current through output transistor P 4 at the power supply corner condition (Vout being charged nearly to the power supply voltage).

Sense amplifier 200 has an analogous second current differential amplifier 210 that functions at the ground corner condition (the output voltage Vout at the drains of output transistors P 4 and N 4 being discharged below a second threshold voltage nearly to ground) responsive to the common mode for input voltages inp and inn being discharged towards ground. As the common mode drops towards ground, the output voltage Vout will be higher than the common mode due to the offsets within sense amplifier 200 . Second current differential amplifier 210 addresses this problem by reducing the difference between the control voltage (inp) and the output voltage. Second current differential amplifier 210 thus amplifies the difference between currents I 3 and I 4 only when current I 3 is greater than current I 4 to source the resulting amplified difference current into the ngate node for the ngate drive voltage. The resulting increase in the ngate drive voltage provides sufficient drive for output transistor M 4 to sink the desired amount of current as the output voltage Vout drops towards ground and forces output transistor M 4 into the deep triode region of operation. Transistors P 4 and M 4 thus need not be oversized yet sense amplifier 200 conducts a sufficient amount of current at the corner conditions so that low power operation is enhanced. Additional circuit details for first current differential amplifier 220 and second current differential amplifier 210 will now be discussed.

Second current differential amplifier 210 includes a diode-connected PMOS transistor P 9 having a source tied to the power supply node and a drain connected to a drain of a current mirror NMOS transistor M 9 that mirrors the sum current I 4 conducted by diode-connected transistor M 6 . Diode-connected transistor P 9 thus conducts a mirrored version of the sum current I 4 . In addition, diode-connected transistor P 9 forms a current mirror with a PMOS transistor P 10 whose source is tied to the power supply node and whose drain is connected to the drain of an NMOS transistor M 10 . Transistor M 10 has its gate connected to the gate/drain of diode-connected transistor M 5 and thus mirrors the current I 3 conducted by differential pair transistor P 1 . The drain of transistor M 10 also connects to a drain of a PMOS diode-connected transistor P 11 that forms a current mirror with a PMOS transistor P 12 . The sources of diode-connected transistor P 11 and transistor P 12 are tied to the power supply node. Since transistor P 10 mirrors the current I 4 whereas transistor M 10 mirrors the current I 3 , only the difference current (I 3 −I 4 ) is conducted by diode-connected transistor P 11 when current I 3 is greater than current I 4 . Should current I 3 be less than current I 4 , diode-connected transistor P 11 does not conduct. Transistor P 12 may be several times larger than diode-connected transistor P 11 so that the mirrored current that transistor P 12 conducts is an amplified version of the difference current (I 3 −I 4 ). In other embodiments, transistor P 12 may be the same size as diode-connected transistor P 11 such that the difference current (I 3 −I 4 ) is not amplified by transistor P 12 . When the common mode of the differential input voltage is sufficiently low, differential pair transistors M 1 and M 2 are not conducting. The sum current I 4 then becomes equal to the drain current for differential pair transistor P 2 such that the current difference (I 3 −I 4 ) is the difference between the current conducted by differential pair transistor P 1 and the current conducted by differential pair transistor P 2 . This difference current mirrored by transistor P 12 flows through a pair of PMOS switch transistors P 15 and P 16 arranged in parallel. Input voltage inp drives the gate of switch transistor P 15 whereas input voltage inn drives the gate of switch transistor P 16 . Switch transistors P 15 and P 16 will thus be switched on when the common mode voltage is sufficiently low to boost the charging of the ngate drive voltage so that output transistor M 4 can conduct the desired amount of current despite operating in the deep triode region of operation as the output voltage is discharged.

Should the common mode for input voltages inn and inp rise towards the power supply voltage (VCC), the differential pair transistors P 1 and P 2 will stop conducting such that the sum current I 2 conducted by diode-connected transistor P 7 equals the current conducted by differential pair transistor M 2 . Diode-connected transistor P 7 is in a current mirror configuration with a PMOS transistor P 13 having a source tied to the power supply node. Transistor P 13 will thus conduct a mirrored version of sum current I 2 . First current differential amplifier 220 includes a diode-connected transistor M 11 having a source tied to ground and a drain connected to the drain for transistor P 13 . Transistor M 11 has its gate and drain connected to the gate of an NMOS transistor M 12 having its source tied to ground so that diode-connected transistor M 11 and transistor M 12 form a current mirror. Transistor M 12 thus conducts a mirrored-version of the sum current I 2 .

To mirror the current I 1 conducted by differential pair transistor M 1 into first current differential amplifier 220 , the gate and drain of diode-connected transistor P 6 are tied to the gate of a PMOS transistor P 14 having its source tied to the power supply node. The drain of transistor P 14 is tied to the drain of transistor M 12 and also to the drain of an NMOS diode-connected transistor M 13 having its source tied to ground. Diode-connected transistor M 13 thus conducts the difference current (I 1 −I 2 ) when current I 1 is greater than current I 2 . Diode-connected transistor M 13 forms a current mirror with an NMOS transistor M 14 having its source tied to ground. Transistor M 14 may be larger than diode-connected transistor so that transistor M 14 conducts an amplified version of the difference current (I 1 −I 2 ). In alternative embodiments, transistor M 14 may be the same size as diode-connected transistor M 13 . The drain of transistor M 14 couples to the pgate node through NMOS switch transistors M 15 and M 16 as discussed earlier. Switch transistors M 15 and M 16 will thus be conducting when the common mode for the differential input voltage is sufficiently high so that the amplified version of the difference current (I 1 −I 2 ) may sink from the pgate node to assist in the discharge of the pgate drive voltage so that output transistor P 4 may conduct a sufficient amount of current as the output voltage Vout rises towards the power supply voltage VCC. In this fashion, output transistor P 4 may source the desired amount of current yet does not need to be oversized such that low power operation is achieved.

The wide swing yet low power operation of sense amplifier 200 reduces charge sharing in PLL applications. An example portion of a PLL 300 is shown in FIG. 3 . A phase detector (PFD) 305 compares a reference clock signal Vref to a divided feedback signal Vfeedback. Should the divided feedback signal be lagging the reference clock, PFD 305 asserts an up signal. Conversely, PFD 305 asserts a down signal should the reference clock signal be lagging the divided feedback signal. A charge pump 301 responds to the assertion of the up signal or the down signal to either charge or discharge a control voltage (Vctrl) accordingly. The up signal is inverted in an inverter 310 to drive a gate of a PMOS switch transistor P 19 . The source of transistor P 19 is biased by the drain current of a PMOS current source transistor P 17 having its gate biased by a bias voltage biasp. The control voltage is produced at the drain of switch transistor P 19 . This control voltage is the charge pump output voltage. PLL 300 includes a loop filter (not illustrated) that filters the control voltage to produce a filtered control voltage for controlling the output frequency of a PLL output signal produced by a voltage-controlled oscillator (not illustrated). A feedback divider (not illustrated) divides the PLL output signal to produce the divided feedback signal.

The down signal drives a gate of an NMOS switch transistor M 19 having its drain tied to the drain of switch transistor P 19 . An NMOS current source transistor M 17 biased by a bias voltage biasn biases the source of transistor M 19 . Charge pump 301 also includes a PMOS duplicate switch transistor P 18 and an NMOS duplicate transistor M 18 arranged in series between the drains of current source transistors P 17 and M 17 . The up signal drives the gate of duplicate switch transistor P 18 whereas an inverter 315 inverts the down signal to drive the gate of duplicate switch transistor M 18 . As discussed previously, duplicate switch transistors P 18 and M 18 in combination with switch transistors P 19 and M 19 keep the drains for the current source transistors P 17 and M 17 charged to the control voltage to prevent charge sharing from affecting the PLL operation. In particular, feedback through sense amplifier 200 keeps the drain voltages (Vout) for duplicate switch transistors P 18 and M 18 equal to the control voltage (Vctl) drain voltages of transistors M 19 and P 19 to prevent charge sharing from affecting the control voltage.

A method of operation for a sense amplifier will now be discussed with regard to the flowchart of FIG. 5 . The method is directed to the driving of the sense amplifier while a common mode voltage for a differential input voltage is greater than a first threshold voltage and includes an act 500 of driving a pair of gates for a differential pair of PMOS transistors with the differential input voltage to substantially shut off a first current in a first one of the PMOS transistors and to substantially shut off a second current in a second one of PMOS transistors. The switching off of transistors P 1 and P 2 in response to a sufficiently high common mode for the differential input voltage is an example of act 500 . The method also includes an act 505 of driving a pair of gates for a differential pair of NMOS transistors with the differential input voltage to conduct a third current in a first one of NMOS transistors and to conduct a fourth current in a second one of the NMOS transistors. The conducting of currents I 1 and I 2 as discussed with regard to transistors M 1 and M 2 is an example of act 505 . The method further includes an act 510 of sinking a current proportional to a sum of the second current and the third current from a gate of an NMOS output transistor to partially discharge the gate of the NMOS output transistor and to also partially discharge a gate of a PMOS output transistor through a biasing network. The mirroring of the sum current I 4 through diode-connected transistor M 6 and transistor M 8 to sink the mirrored sum current from the ngate node is an example of act 510 . Finally, the method includes an act 515 of sinking a difference current proportional to a difference between the third current and the fourth current from the gate of the PMOS output transistor to further discharge the gate of the PMOS output transistor, wherein the further discharging of the gate of the PMOS output transistor also further discharges the gate of the NMOS output transistor through the biasing network. The discharging of the pgate drive voltage by first current differential amplifier 220 is an example of act 515 .

It will be appreciated that many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.