GOA unit and method of driving the same, GOA circuit and display apparatus

This is a National Phase Application filed under 35 U.S.C. 371 as a national stage of PCT/CN2017/112088, filed on Nov. 21, 2017, an application claiming the benefit of Chinese Patent Application No. 201710041956.X, filed on Jan. 20, 2017, the contents of which are incorporated by reference in the entirety.

The present disclosure relates to the field of display technologies, and particularly, to a gate driver-on-array (GOA) unit and a method of driving the same, a GOA circuit, and a display apparatus.

In liquid crystal display (LCD) apparatuses and organic light emitting diode (OLED) display apparatuses, pixels are typically controlled by thin film transistors (TFTs) to realize an image display. Controls on the pixels include a row-control and a column-control. The row-control is performed by a GOA circuit to scan the pixels row by row, while the column-control is performed by a data driving circuit to transmit display data of the pixels. A conventional GOA circuit includes a plurality of cascaded GOA units, each of which has a same circuit configuration.

In an aspect, the present disclosure provides a gate driver-on-array (GOA) unit including a pulling-up circuit, a pulling-down circuit and an output holding circuit. The pulling-up circuit, the pulling-down circuit and the output holding circuit are coupled with an output terminal of the GOA unit. The pulling-up circuit and the output holding circuit are coupled with a pulling-up node. The pulling-up circuit and the pulling-down circuit are coupled with a pulling-down node. The pulling-down circuit is coupled with a low voltage level terminal and a first voltage level terminal. The pulling-up circuit is coupled with a high voltage level terminal, the first voltage level terminal and a second voltage level terminal. The output holding circuit is coupled with the second voltage level terminal. The pulling-up circuit is configured to output a gate scanning signal from the output terminal, under the control of a trigger signal, a first control signal and a second control signal; the output holding circuit is configured to hold the gate scanning signal output from the output terminal, under the control of the trigger signal, the first control signal and the second control signal; and the pulling-down circuit is configured to reset the gate scanning signal and hold the gate scanning signal in a reset state for a set time period, under the control of the trigger signal, the first control signal and the second control signal.

Optionally, the output holding circuit includes a ninth transistor and a third capacitor; a first end of the third capacitor and a gate electrode and a first electrode of the ninth transistor are coupled with the pulling-up node; a second end of the third capacitor is coupled with the output terminal; and a second electrode of the ninth transistor is coupled with the second voltage level terminal.

Optionally, the pulling-up circuit includes a first capacitor, a fourth transistor, a fifth transistor and a seventh transistor; a first end of the first capacitor is coupled with a terminal for providing the first control signal, and a second end of the first capacitor is coupled with a gate electrode of the fourth transistor and the pulling-down circuit; a first electrode of the fourth transistor is coupled with a gate electrode of the fifth transistor, the pulling-up node and a gate electrode of the seventh transistor, and a second electrode of the fourth transistor is coupled with the second voltage level terminal; a first electrode of the fifth transistor is coupled with the pulling-down node, and a second electrode of the fifth transistor is coupled with the first voltage level terminal; and a first electrode of the seventh transistor is coupled with the output terminal, and a second electrode of the seventh transistor is coupled with the high voltage level terminal.

Optionally, the pulling-up circuit further includes an eighth transistor; a gate electrode of the eighth transistor is coupled with the pulling-up node, a first electrode of the eighth transistor is coupled with the pulling-down node, and a second electrode of the eighth transistor is coupled with the first voltage level terminal.

Optionally, the pulling-down circuit includes a first transistor, a second transistor, a third transistor, a sixth transistor and a second capacitor; a gate electrode of the first transistor is coupled with a terminal for providing the trigger signal and a first electrode of the second transistor, a first electrode of the first transistor is coupled with the first voltage level terminal, and a second electrode of the first transistor is coupled with the pulling-up circuit; a gate electrode of the second transistor is coupled with the terminal for providing the first control signal, and a second electrode of the second transistor is coupled with the pulling-down node; a gate electrode of the third transistor is coupled with a gate electrode of the sixth transistor, a first end of the second capacitor and the pulling-down node, a first electrode of the third transistor is coupled with the first voltage level terminal, and a second electrode of the third transistor is coupled with the pulling-up circuit; a second end of the second capacitor is coupled with a terminal for providing the second control signal; and a first electrode of the sixth transistor is coupled with the low voltage level terminal, and a second electrode of the sixth transistor is coupled with the output terminal.

Optionally, the first voltage level terminal is of a high voltage level, and the second voltage level terminal is of a low voltage level; and the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor are each a P-type transistor.

Optionally, the first voltage level terminal is of a low voltage level, and the second voltage level terminal is of a high voltage level; and the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor are each an N-type transistor.

In another aspect, the present disclosure provides a gate driver-on-array (GOA) circuit, which includes any one of the GOA units described herein.

In another aspect, the present disclosure provides a display apparatus, which includes the GOA circuit described herein.

In another aspect, the present disclosure provides a method of driving any one of the above GOA units, including: in a pulling-up stage, outputting, by the pulling-up circuit under the control of the trigger signal, the first control signal and the second control signal, a gate scanning signal from the output terminal of the GOA unit; in an output holding stage, holding, by the output holding circuit under the control of the trigger signal, the first control signal and the second control signal, the gate scanning signal output from the output terminal; in a pulling-down stage, resetting the gate scanning signal by the pulling-down circuit under the control of the trigger signal, the first control signal and the second control signal; and in a pulling-down holding stage, holding, by the pulling-down circuit under the control of the trigger signal, the first control signal and the second control signal, the gate scanning signal in a reset state for a set time period.

The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present invention, in which:

FIG. 1 is a schematic circuit diagram of a gate driver-on-array (GOA) unit according to an embodiment of the present disclosure;

FIG. 2 is a circuit diagram of a GOA unit according to an embodiment of the present disclosure;

FIG. 3 is a timing diagram illustrating a process of driving the GOA unit in FIG. 2 ;

FIG. 4 is diagram illustrating a comparison between an output signal and a signal at a pulling-up node of the GOA unit in FIG. 2 and an output signal and a signal at a pulling-up node of an existing GOA unit; and

FIG. 5 is a timing diagram illustrating a process of driving a GOA unit according to an embodiment of the present disclosure.

The disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.

In a conventional gate driver-on-array (GOA) circuit, it suffers from unstable output signals of GOA units, for example, the GOA units of the GOA circuit often output a signal with an unsmooth waveform. Moreover, the difference in amplitude between a waveform of an output signal of a GOA unit and a waveform of an input signal of the GOA unit, based on which the output signal is generated, is relatively large, resulting in that the GOA circuit cannot scan and drive the pixels row by row in a stable manner. As a result, the LCD apparatus or the OLED apparatus, in which the GOA circuit is used, cannot perform an image display in a stable manner.

Accordingly, the present disclosure provides, inter alia, a gate driver-on-array (GOA) unit and a method of driving the same, a GOA circuit, and a display apparatus that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.

In an aspect, embodiments of the present disclosure provide a gate driver-on-array (GOA) unit. FIG. 1 is a schematic circuit diagram of a gate driver-on-array (GOA) unit according to an embodiment of the present disclosure. A shown in FIG. 1 , the GOA unit includes a pulling-up circuit 1 , a pulling-down circuit 2 and an output holding circuit 3 . The pulling-up circuit 1 , the pulling-down circuit 2 and the output holding circuit 3 are coupled with an output terminal Output of the GOA unit. The pulling-up circuit 1 and the output holding circuit 3 are coupled with a pulling-up node Net 2 . The pulling-up circuit 1 and the pulling-down circuit 2 are coupled with a pulling-down node Net 1 . The pulling-down circuit 2 is coupled with a low voltage level terminal VGL and a first voltage level terminal V 1 . The pulling-up circuit 1 is coupled with a high voltage level terminal VGH, the first voltage level terminal V 1 and a second voltage level terminal V 2 . The output holding circuit 3 is coupled with the second voltage level terminal V 2 . The pulling-up circuit 1 is configured to output a gate scanning signal from the output terminal Output, under the control of a trigger signal STV, a first control signal CK and a second control signal CB. The output holding circuit 3 is configured to hold the gate scanning signal output from the output terminal Output, under the control of the trigger signal STV, the first control signal CK and the second control signal CB. The pulling-down circuit 2 is configured to reset the gate scanning signal and hold the gate scanning signal in a reset state for a set time period, under the control of the trigger signal STV, the first control signal CK and the second control signal CB.

By having the output holding circuit 3 , the present GOA unit is capable of outputting a gate scanning signal from the output terminal Output thereof in a more stable manner. The gate scanning signal, compared to that in the related art, has a smoother waveform and a reduced difference in amplitude between the waveform of the gate scanning signal and a waveform of an input signal, based on which the gate scanning signal is generated. As a result, the present GOA unit is capable of performing a scanning and driving operation in a more stable manner.

FIG. 2 is a circuit diagram of a GOA unit according to an embodiment of the present disclosure. As shown in FIG. 2 , the output holding circuit 3 in the present embodiment includes a ninth transistor T 9 and a third capacitor C 3 ; a first end of the third capacitor C 3 and a gate electrode and a first electrode of the ninth transistor T 9 are coupled with the pulling-up node Net 2 , a second end of the third capacitor C 3 is coupled with the output terminal Output; and a second electrode of the ninth transistor T 9 is coupled with the second voltage level terminal V 2 .

The pulling-up circuit 1 in the present embodiment includes a first capacitor C 1 , a fourth transistor T 4 , a fifth transistor T 5 and a seventh transistor T 7 . A first end of the first capacitor C 1 is coupled with a terminal for providing the first control signal CK, and a second end of the first capacitor C 1 is coupled with a gate electrode of the fourth transistor T 4 and the pulling-down circuit 2 . A first electrode of the fourth transistor T 4 is coupled with a gate electrode of the fifth transistor T 5 , the pulling-up node Net 2 and a gate electrode of the seventh transistor T 7 , and a second electrode of the fourth transistor T 4 is coupled with the second voltage level terminal V 2 . A first electrode of the fifth transistor T 5 is coupled with the pulling-down node Net 1 , and a second electrode of the fifth transistor T 5 is coupled with the first voltage level terminal V 1 . A first electrode of the seventh transistor T 7 is coupled with the output terminal Output, and a second electrode of the seventh transistor T 7 is coupled with the high voltage level terminal VGH.

Optionally, the pulling-up circuit 1 in the present embodiment further includes an eighth transistor T 8 . A gate electrode of the eighth transistor T 8 is coupled with the pulling-up node Net 2 , a first electrode of the eighth transistor T 8 is coupled with the pulling-down node Net 1 , and a second electrode of the eighth transistor T 8 is coupled with the first voltage level terminal V 1 . By having the eighth transistor T 8 , the present GOA unit is capable of further switching off the pulling-down circuit 2 in an output holding stage, thereby preventing the pulling-down circuit 2 from disturbing the gate scanning signal. As a result, the present GOA unit can output the gate scanning signal in a more stable manner.

In the present embodiment, the pulling-down circuit 2 includes a first transistor T 1 , a second transistor T 2 , a third transistor T 3 , a sixth transistor T 6 and a second capacitor C 2 . A gate electrode of the first transistor T 1 is coupled with a terminal for providing the trigger signal STV and a first electrode of the second transistor T 2 , a first electrode of the first transistor T 1 is coupled with the first voltage level terminal V 1 , and a second electrode of the first transistor T 1 is coupled with the pulling-up circuit 1 . A gate electrode of the second transistor T 2 is coupled with the terminal for providing the first control signal CK, and a second electrode of the second transistor T 2 is coupled with the pulling-down node Net 1 . A gate electrode of the third transistor T 3 is coupled with a gate electrode of the sixth transistor T 6 , a first end of the second capacitor C 2 and the pulling-down node Net 1 , a first electrode of the third transistor T 3 is coupled with the first voltage level terminal V 1 , and a second electrode of the third transistor T 3 is coupled with the pulling-up circuit 1 . A second end of the second capacitor C 2 is coupled with a terminal for providing the second control signal CB. A first electrode of the sixth transistor T 6 is coupled with the low voltage level terminal VGL, and a second electrode of the sixth transistor T 6 is coupled with the output terminal Output.

In the present embodiment, the first voltage level terminal V 1 is of a high voltage level, and the second voltage level terminal V 2 is of a low voltage level; and the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5 , the sixth transistor T 6 , the seventh transistor T 7 , the eighth transistor T 8 and the ninth transistor T 9 are each a P-type transistor.

Based on the structure of the circuit of the above GOA unit, the present embodiment further provides a method of driving the GOA unit. FIG. 3 is a timing diagram illustrating a process of driving the GOA unit in FIG. 2 . Next, the driving method will be described with reference to FIGS. 2 and 3 .

As shown in FIG. 3 , the driving method includes: in a pulling-up stage L 1 , outputting, by the pulling-up circuit 1 under the control of the trigger signal STV, the first control signal CK and the second control signal CB, a gate scanning signal from the output terminal Output of the GOA unit.

In the pulling-up stage L 1 , the trigger signal STV is of a high voltage level, the first control signal CK is of a low voltage level, and the second control signal CB is of a high voltage level, thus the second transistor T 2 is turned on, a voltage level at the pulling-down node Net 1 is pulled up, and the sixth transistor T 6 is turned off. Meanwhile, a voltage level at the first end of the first capacitor C 1 is pulled down by the first control signal CK, and a voltage level at the gate electrode of the fourth transistor is pulled down to about −6V (volt) by utilizing the capacitance characteristics of the first capacitor C 1 ; at this time, the fourth transistor T 4 and the fifth transistor T 5 are turned on, the sixth transistor T 6 is turned off due to a high voltage level signal input from the first voltage level terminal V 1 coupled with the second electrode of the fifth transistor T 5 that has turned on, and the seventh transistor T 7 is turned on due to a low voltage level signal input from the second voltage level terminal V 2 coupled with the second electrode of the fourth transistor T 4 that has turned on. As a result, a high voltage level signal (i.e., a gate scanning signal), which is input from the high voltage level terminal VGH, is output from the output terminal Output of the GOA unit. Meanwhile, a low voltage level signal, which is input from the second voltage level terminal V 2 coupled with the second electrode of the fourth transistor T 4 that has turned on, is stored at the first end (i.e., the pulling-up node Net 2 ) of the third capacitor C 3 .

The driving method further includes: in an output holding stage L 2 , holding, by the output holding circuit 3 under the control of the trigger signal STV, the first control signal CK and the second control signal CB, the gate scanning signal output from the output terminal Output.

In the output holding stage L 2 , the trigger signal STV is of a low voltage level, the first control signal CK is of a high voltage level, and the second control signal CB is of a low voltage level. As the low voltage level signal in the previous stage (i.e., the pulling-up stage L 1 ) is stored at the first end (i.e., the pulling-up node Net 2 ) of the third capacitor C 3 , the fifth transistor T 5 is turned on, and the sixth transistor T 6 is turned off due to a high voltage level signal input from the second electrode of the fifth transistor T 5 . Meanwhile, the eighth transistor T 8 is turned on, and the sixth transistor T 6 is further turned off due to a high voltage level signal input from the first voltage level terminal V 1 , which is coupled with the second electrode of the eighth transistor T 8 . As a result, a low voltage level of the low voltage level terminal VGL, which is coupled with the first electrode of the sixth transistor T 6 , will not disturb the gate scanning signal output from the GOA unit, such that the output of the gate scanning signal is more stable. The seventh transistor T 7 remains on, so the output terminal Output outputs a high voltage level signal (i.e., a gate scanning signal). At this time, the ninth transistor T 9 is turned on, a low voltage level signal from the second voltage level terminal V 2 , which is coupled with the second electrode of the ninth transistor T 9 , is input to the pulling-up node Net 2 , and thus the voltage level at the pulling-up node Net 2 is further pulled down. As a result, the seventh transistor T 7 stably maintains on.

FIG. 4 is diagram illustrating a comparison between an output signal and a signal at the pulling-up node of the GOA unit in FIG. 2 and an output signal and a signal at a pulling-up node of an existing GOA unit. In the present embodiment, as shown in FIG. 4 , by having the third capacitor C 3 , the low voltage level signal in the previous stage (i.e., the pulling-up stage L 1 ) of the output holding stage L 2 is stored at the pulling-up node Net 2 (i.e., the first end of the third capacitor C 3 ), so that the fluctuation of the voltage at the pulling-up node Net 2 in a transition from the pulling-up stage L 1 to the output holding stage L 2 is reduced, as compared to a case in which the third capacitor C 3 is not provided in the prior art. As a result, the output of the GOA unit is secured to be more stable. Meanwhile, as the low voltage level signal is stored at the first end of the third capacitor C 3 , the ninth transistor T 9 is turned on, and a low voltage level signal from the second voltage level terminal V 2 , which is coupled with the second electrode of the ninth transistor T 9 , is input to the pulling-up node Net 2 , resulting in that the seventh transistor T 7 stably maintains on. As a result, compared to a case in which the ninth transistor T 9 is not provided in the prior art, it is possible to ensure the gate scanning signal output from the GOA unit in the pulling-up stage L 1 and the output holding stage L 2 has a smoother waveform, while the difference in amplitude between the waveform of the gate scanning signal and a waveform of an input signal (i.e., a high voltage level signal input from the high voltage level terminal VGH), based on which the gate scanning signal is generated, can be reduced. That is, an amplitude of the waveform of the output gate scanning signal and an amplitude of the waveform of the high voltage level signal input from the high voltage level terminal VGH are substantially the same. As a result, the GOA unit can perform a scanning and driving operation in a more stable manner. As shown in FIG. 4 , without provision of the ninth transistor T 9 and the third capacitor C 3 , the smaller the size of a display panel, the higher the voltage level at the pulling-up node Net 2 is, resulting in that the seventh transistor T 7 is unable to be turned on in the output holding stage L 2 , thereby adversely affecting output of the GOA unit.

Referring to FIG. 3 again, the driving method further includes: in a pulling-down stage L 3 , resetting the gate scanning signal by the pulling-down circuit 2 under the control of the trigger signal STV, the first control signal CK and the second control signal CB.

In the pulling-down stage L 3 , the trigger signal STV is of a low voltage level, the first control signal CK is of a low voltage level, and the second control signal CB is of a high voltage level. As a result, the second transistor T 2 is turned on, and the trigger signal STV is input via the first electrode thereof, such that the sixth transistor T 6 is turned on, and a low voltage level signal, which is input to the first electrode of the sixth transistor T 6 , is output from the output terminal Output of the GOA unit. Meanwhile, the first transistor T 1 is turned on and a high voltage level signal from the first voltage level terminal V 1 is input via the first electrode of the first transistor T 1 , so the fourth transistor T 4 is turned off. The third transistor T 3 is turned on and a high voltage level signal from the first voltage level terminal V 1 is input via the first electrode of the third transistor T 3 , so the fifth transistor T 5 , the seventh transistor T 7 and the ninth transistor T 9 are turned off, thereby resetting the high-level gate scanning signal output from the output terminal Output.

The driving method further includes: in a pulling-down holding stage L 4 , holding, by the pulling-down circuit 2 under the control of the trigger signal STV, the first control signal CK and the second control signal CB, the gate scanning signal in a reset state for a set time period.

In the pulling-down holding stage L 4 , the trigger signal STV is of a low voltage level, the first control signal CK is of a high voltage level and the second control signal CB is of a low voltage level. As a result, a voltage level at the second end of the second capacitor C 2 is pulled down by the second control signal CB, and a voltage level at the first end (i.e., the pulling-down node Net 1 ) of the second capacitor C 2 is also pulled down at the same time by utilizing the capacitance characteristics of the second capacitor C 2 . Due to the residual voltage level from the previous stage (i.e., the pulling-down stage L 3 ), the pulling-down node Net 1 is pulled down to about −15V, while the sixth transistor T 6 maintains on. As a result, the output terminal Output of the GOA unit outputs a low voltage level signal, thereby maintaining the gate scanning signal in a reset state until the next pulling-up stage L 1 starts.

An embodiment of the present disclosure further provides a GOA unit, which differs from that in the above embodiment in that, the first voltage level terminal is of a low voltage level, the second voltage level terminal is of a high voltage level, and the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth transistors are each an N-type transistor.

Other circuit structures of the GOA unit in the present embodiment are the same as those in the above embodiments.

Accordingly, based on the above circuit structures of the GOA unit in the present embodiment, the present embodiment further provides a method of driving the GOA unit. FIG. 5 is a timing diagram illustrating a process of driving a GOA unit according to the present embodiment. As shown in FIG. 5 , it differs from the driving method in the above embodiment in that, in each of the pulling-up stage L 1 , the output holding stage L 2 , the pulling-down stage L 3 and the pulling-down holding stage L 4 , the trigger signal STV, the first control signal CK and the second control signal CB each has a voltage level opposite to that in the above embodiment.

The steps of the method of driving the GOA unit in the present embodiment are similar to those in the above embodiment, and will not be described herein.

By having the output holding circuit, the GOA unit of the present disclosure is capable of outputting a gate scanning signal from the output terminal of the GOA unit in a more stable manner. The gate scanning signal, compared to that in the related art, has a smoother waveform and a reduced difference in amplitude between the waveform of the gate scanning signal and a waveform of an input signal, based on which the gate scanning signal is generated. As a result, the present GOA unit is capable of performing a scanning and driving operation in a more stable manner.

In another aspect, the present disclosure further provides a gate driver-on-array (GOA) circuit, which includes any one of the above GOA units.

By having any one of the above GOA units provided by the embodiments of the present disclosure, the GOA circuit can scan and drive a gate in a more stable manner.

In another aspect, the present disclosure provides a display apparatus, which includes the GOA circuit provided by the present disclosure.

By having the GOA circuit provided by the present disclosure, the display apparatus can have an improved stability of image display, thereby improving its display effect.

The display apparatus may be any product or part with a display function, such as a liquid crystal display panel, a liquid crystal display television, a display, a mobile phone and a navigator.

It can be understood that the foregoing implementations are merely exemplary implementations used for describing the principle of the present disclosure, but the present disclosure is not limited thereto. Those ordinary skilled in the art may make various variations and improvements without departing from the spirit and essence of the present disclosure, and these variations and improvements shall fall into the protection scope of the present disclosure.