Uninterruptible power supply device

The present invention relates to an uninterruptible power supply device, and particularly to an uninterruptible power supply device of a two-phase three-wire type.

A two-phase three-wire type is a power feeding type in which a two-phase alternating-current (AC) voltage and a neutral point voltage are fed to consumers. In Japan, the phases of the two-phase AC voltage are shifted by 180 degrees from each other, which is referred to as a single-phase three-wire type. An AC voltage in one phase of the two-phase AC voltage and a neutral point voltage are supplied to an electrical device of 100V A two-phase AC voltage is supplied to an electrical device of 200V In North America, a two-phase AC voltage of the three-phase AC voltage is supplied to consumers, and the phases of the two-phase AC voltage are shifted by 120 degrees from each other.

Japanese Patent Laying-Open No. 06-253549 (PTD 1) discloses an uninterruptible power supply device of a single-phase three-wire type. This uninterruptible power supply device includes: a converter configured to convert a two-phase AC voltage supplied from a commercial AC power supply into a direct-current (DC) voltage; and an inverter configured to convert the DC voltage generated by the converter or a DC voltage from a power storage device into a two-phase AC voltage and supply the converted two-phase AC voltage to a load.

Patent Document

PTD 1: Japanese Patent Laying-Open No. 06-253549

Technical Problem

Such an uninterruptible power supply device is provided with a voltage detector configured to detect an instantaneous value of the two-phase AC voltage from the commercial AC power supply, in which the converter and the inverter are controlled in synchronization with a signal output from the voltage detector. When an abnormality occurs in the voltage detector, the operation of the converter is stopped while the operation of the inverter is continued. Then, the DC voltage from the power storage device is converted into a two-phase AC voltage and supplied to the load. When the voltage across terminals of the power storage device decreases and reaches a discharge cut-off voltage, supply of the two-phase AC voltage from the inverter to the load is stopped. Then, the two-phase AC voltage from the commercial AC power supply is directly supplied to the load through a bypass switch pair.

Accordingly, the conventional uninterruptible power supply device causes a problem that supply of the two-phase AC voltage to the load is instantaneously interrupted when a failure occurs in the voltage detector.

Thus, a main object of the present invention is to provide an uninterruptible power supply device capable of supplying a two-phase AC voltage to a load without instantaneous interruption even when an abnormality occurs in a voltage detector.

Solution to Problem

An uninterruptible power supply device according to the present invention is provided as an uninterruptible power supply device of a two-phase three-wire type. The uninterruptible power supply device includes a converter configured to convert a two-phase AC voltage supplied from a commercial AC power supply into a DC voltage, an inverter configured to convert the DC voltage generated by the converter or a DC voltage supplied from a power storage device into a two-phase AC voltage, and supply the two-phase AC voltage to a load; a bypass switch pair having one terminal pair receiving the two-phase AC voltage from the commercial AC power supply and the other terminal pair connected to the load; a semiconductor switch pair connected in parallel to the bypass switch pair, a first voltage detector and a second voltage detector each configured to detect an instantaneous value of the two-phase AC voltage from the commercial AC power supply, and generate an output signal indicating a detected value; an abnormality detector configured to determine whether the first voltage detector normally functions or not, and generate an output signal indicating a determination result, and a control circuit configured to control the uninterruptible power supply device based on the output signals from the first voltage detector and the second voltage detector and the output signal from the abnormality detector. When the first voltage detector normally functions, the control circuit is configured to turn off the bypass switch pair and the semiconductor switch pair, and control the converter and the inverter in synchronization with the output signal from the first voltage detector. When an abnormality occurs in the first voltage detector, the control circuit is configured to stop an operation of the converter, control the inverter in synchronization with the output signal from the second voltage detector to convert the DC voltage from the power storage device into a two-phase AC voltage, and to match a phase of the two-phase AC voltage with a phase of the two-phase AC voltage from the commercial AC power supply, turn on the bypass switch pair and the semiconductor switch pair when a voltage across terminals of the power storage device decreases and reaches a predetermined voltage, and turn off the semiconductor switch pair after a lapse of a predetermined time period.

Another uninterruptible power supply device according to the present invention is provided as an uninterruptible power supply device of a two-phase three-wire type. The uninterruptible power supply device includes a converter configured to convert a two-phase AC voltage supplied from a commercial AC power supply into a DC voltage, an inverter configured to convert the DC voltage generated by the converter or a DC voltage supplied from a power storage device into a two-phase AC voltage, and supply the two-phase AC voltage to a load; a bypass switch pair having one terminal pair receiving the two-phase AC voltage from the commercial AC power supply and the other terminal pair connected to the load; a semiconductor switch pair connected in parallel to the bypass switch pair, a first voltage detector and a second voltage detector each configured to detect an instantaneous value of an AC voltage in one phase of the two-phase AC voltage from the commercial AC power supply, and generate an output signal indicating a detected value, a third voltage detector configured to detect an instantaneous value of an AC voltage in the other phase of the two-phase AC voltage from the commercial AC power supply, and generate an output signal indicating a detected value, an abnormality detector configured to determine whether the first voltage detector normally functions or not, and generate an output signal indicating a determination result, and a control circuit configured to control the uninterruptible power supply device based on the output signals from the first voltage detector, the second voltage detector and the third voltage detector and the output signal from the abnormality detector. When the first voltage detector normally functions, the control circuit is configured to turn off the bypass switch pair and the semiconductor switch pair, and control the converter and the inverter in synchronization with the output signal from the first voltage detector. When an abnormality occurs in the first voltage detector, the control circuit is configured to stop an operation of the converter, control the inverter in synchronization with the output signal from the second voltage detector to convert the DC voltage from the power storage device into a two-phase AC voltage, and to match a phase of the two-phase AC voltage with a phase of the two-phase AC voltage from the commercial AC power supply, turn on the bypass switch pair and the semiconductor switch pair when a voltage across terminals of the power storage device decreases and reaches a predetermined voltage, and turn off the semiconductor switch pair after a lapse of a predetermined time period.

Advantageous Effects of Invention

In the uninterruptible power supply device according to the present invention, when an abnormality occurs in the first voltage detector, the inverter is controlled in synchronization with the output signal from the second voltage detector to convert the DC voltage from the power storage device into a two-phase AC voltage, and to match a phase of the two-phase AC voltage with the phase of the two-phase AC voltage from the commercial AC power supply, so as to turn on the bypass switch pair and the semiconductor switch pair when the voltage across terminals of the power storage device decreases to a prescribed voltage. Accordingly, even when an abnormality occurs in the first voltage detector, the two-phase AC voltage can be supplied to the load without instantaneous interruption.

FIG. 1 is a circuit block diagram showing the configuration of an uninterruptible power supply device according to the first embodiment of the present invention

FIG. 2 is a circuit diagram showing the configurations of a converter and an inverter that are shown in FIG. 1 .

FIG. 3 is a circuit diagram showing the configuration of an input voltage detection circuit shown in FIG. 1 .

FIG. 4 is a block diagram showing the configuration of an abnormality detector shown in FIG. 1

FIG. 5 is a circuit diagram for illustrating an abnormality in the voltage detector shown in FIG. 3

FIG. 6 is a circuit diagram showing the configuration of an output voltage detection circuit shown in FIG. 1 .

FIG. 7 is a circuit block diagram showing a main part in a control circuit shown in FIG. 1 .

FIG. 8 is a time chart for illustrating the operation of a phase conversion unit shown in FIG. 7

FIG. 9 is a diagram showing the operation of the uninterruptible power supply device shown in FIG. 1 .

FIG. 10 is another diagram showing the operation of the uninterruptible power supply device shown in FIG. 1 .

FIG. 11 is a diagram showing the operation of an uninterruptible power supply device provided as a comparative example of the first embodiment.

FIG. 12 is another diagram showing the operation of the uninterruptible power supply device provided as a comparative example of the first embodiment.

FIG. 13 is a circuit block diagram showing the configuration of an input voltage detection circuit included in an uninterruptible power supply device according to the second embodiment of the present invention.

FIG. 14 is a circuit block diagram showing a main part in a control circuit included in the uninterruptible power supply device illustrated in FIG. 13 .

First Embodiment

FIG. 1 is a circuit block diagram showing the configuration of an uninterruptible power supply device according to the first embodiment of the present invention. In FIG. 1 , this uninterruptible power supply device is of a two-phase three-wire type, and includes input terminals TI 1 to TI 3 , battery terminals TB 1 , TB 2 , and output terminals TO 1 to TO 3 . Input terminals TI 1 , TI 2 and TI 3 receive an AC voltage VI 1 , an AC voltage VI 2 and a neutral point voltage VN, respectively, that are supplied from a commercial AC power supply 51 . For example, in Japan, the phase of AC voltage VI 1 is advanced by 180 degrees from the phase of AC voltage VI 2 . The effective value of each of AC voltages VI 1 and VI 2 is 100V. Neutral point voltage VN is 0V.

Battery terminals TB 1 and TB 2 are connected to a positive electrode and a negative electrode, respectively, of a battery 52 (power storage device). A capacitor may be connected in place of battery 52 . Output terminals TO 1 , TO 2 and TO 3 receive an AC voltage VO 1 , an AC voltage VO 2 and a neutral point voltage VN, respectively, and connected to a load 53 . The phase of AC voltage VO 1 is advanced by 180 degrees from the phase of AC voltage VO 2 .

Load 53 includes an electrical device receiving an AC voltage of 100V from output terminals TO 1 and TN, another electrical device receiving an AC voltage of 100V from output terminals TO 2 and TN, and still another electrical device receiving an AC voltage of 200V from output terminals TO 1 and TO 2 .

This uninterruptible power supply device further includes switches S 1 to S 8 , semiconductor switches S 9 , S 10 , a converter 1 , a DC positive bus L 1 , a DC negative bus L 2 , a DC neutral point bus L 3 , smoothing capacitors C 1 . C 2 . DC voltage detectors DT 1 to DT 3 , a bidirectional chopper 2 , an inverter 3 , an input voltage detection circuit 4 , an abnormality detector 5 , an output voltage detection circuit 6 , and a control circuit 7 .

Switches S 1 and S 2 have one terminals connected to input terminals TI 1 and TI 2 , respectively, and the other terminals connected to converter 1 . Input terminal TI 3 is connected to DC neutral point bus L 3 through converter 1 . Switches S 1 and S 2 are controlled by control circuit 7 to be: turned on in the normal state where a two-phase AC power is supplied from commercial AC power supply 51 , turned off during a power failure in which supply of the two-phase AC power from commercial AC power supply 51 is stopped; and turned off when an abnormality occurs in input voltage detection circuit 4 .

Converter 1 is controlled by control circuit 7 to convert the two-phase AC power from commercial AC power supply 51 into DC power in the normal state where the two-phase AC power is supplied from commercial AC power supply 51 . In other words, in the normal state, converter 1 generates a positive voltage V 1 and a negative voltage VD 2 based on two-phase AC voltages VI 1 and VI 2 supplied from commercial AC power supply 51 . As to converter 1 , during a power failure in which supply of the two-phase AC power from commercial AC power supply 51 is stopped, the operation of converter 1 is stopped. When an abnormality occurs in input voltage detection circuit 4 , the operation of converter 1 is stopped.

DC positive bus L 1 is connected between converter 1 and inverter 3 , and positive voltage VD 1 is transmitted through this DC positive bus L 1 . DC negative bus L 2 is connected between converter 1 and inverter 3 , and negative voltage VD 2 is transmitted through this DC negative bus L 2 . DC neutral point bus L 3 is connected between converter 1 and inverter 3 , and neutral point voltage VN is transmitted through this DC neutral point bus L 3 .

Smoothing capacitor C 1 is connected between buses L 1 and L 3 , and serves to smooth the voltage between buses L 1 and L 3 . Smoothing capacitor C 2 is connected between buses L 3 and L 2 , and serves to smooth the voltage between buses L 3 and L 2 . DC voltage detector DT 1 detects a voltage across terminals of smoothing capacitor C 1 , and outputs a signal indicating the detected value to control circuit 7 . The detected value from DC voltage detector DT 1 is used for setting the voltage across terminals of smoothing capacitor C to a target capacitor voltage VCT. DC voltage detector DT 2 detects a voltage across terminals of smoothing capacitor C 2 , and outputs a signal indicating the detected value to control circuit 7 . The detected value from DC voltage detector DT 2 is used for setting the voltage across terminals of smoothing capacitor C 2 to target capacitor voltage VCT

Switches S 3 and S 4 have one terminals connected to battery terminals TB 1 and TB 2 , respectively, and have the other terminals connected to buses L 1 to L 3 through bidirectional chopper 2 . Switches S 3 and S 4 are turned on when the uninterruptible power supply device is used and turned off during the maintenance of the uninterruptible power supply device and battery 52 , for example.

DC voltage detector DT 3 detects a voltage VB across terminals of battery 52 , and outputs a signal indicating the detected value to control circuit 7 . The detected value from DC voltage detector DT 3 is used for setting voltage VB across terminals of battery 52 to target battery voltage VBT during charging of battery 52 and used for detecting that voltage VI across terminals of battery 52 has reached a discharge cut-off voltage VBL.

Bidirectional chopper 2 is controlled by control circuit 7 to store the DC power generated by converter 1 in battery 52 in the normal state where the two-phase AC power is supplied from commercial AC power supply 51 . Bidirectional chopper 2 supplies the DC power of battery 52 to inverter 3 during a power failure in which supply of the two-phase AC power from commercial AC power supply 51 is stopped, and at the time when an abnormality occurs in input voltage detection circuit 4 .

In other words, bidirectional chopper 2 causes a DC current to flow from each of capacitors C 1 and C 2 through battery 52 to set voltage VI across terminals of battery 52 to target battery voltage VBT. During a power failure and at the time when an abnormality occurs in input voltage detection circuit 4 , bidirectional chopper 2 causes a current to flow from battery 52 through each of capacitors C 1 and C 2 to set the voltage across terminals on each of capacitors C 1 and C 2 to target capacitor voltage VCT.

When voltage VB across terminals of battery 52 decreases and reaches discharge cut-off voltage VBL while the DC power of battery 52 is discharged toward capacitors C 1 and C 2 , bidirectional chopper 2 stops supply of the DC power from battery 52 toward capacitors C 1 and C 2 .

Inverter 3 is controlled by control circuit 7 to convert the DC power generated by converter 1 into a two-phase AC power in the normal state where the two-phase AC power is supplied from commercial AC power supply 51 . During a power failure and at the time when an abnormality occurs in input voltage detection circuit 4 , inverter 3 converts the DC power supplied from battery 52 through bidirectional chopper 2 into a two-phase AC power.

In other words, in the normal state, inverter 3 generates two-phase AC voltages VO 1 and VO 2 based on positive voltage VD 1 , negative voltage VD 2 and neutral point voltage VN that are supplied through buses L 1 , L 2 and L 3 , respectively, from converter 1 . During a power failure and at the time when an abnormality occurs in input voltage detection circuit 4 , inverter 3 generates two-phase AC voltages VO 1 and VO 2 based on positive voltage VD 1 , negative voltage VD 2 and neutral point voltage VN that are supplied through buses L 1 , L 2 and L 3 , respectively, from bidirectional chopper 2 .

Switches S 5 and S 6 have one terminals connected to inverter 3 and the other terminals connected to output terminals TO 1 and TO 2 , respectively. Output terminal TO 3 is connected to DC neutral point bus L 3 through inverter 3 . Switches S 5 and S 6 are controlled by control circuit 7 to be turned on in an inverter power feeding mode in which the two-phase AC power generated by inverter 3 is supplied to load 53 , and turned off in a bypass power feeding mode in which the two-phase AC power from commercial AC power supply 51 is directly supplied to load 53 .

Then, converter 1 and inverter 3 will be hereinafter described in detail. As shown in FIG. 2 , converter 1 includes rectification circuits 1 a and 1 b , and inverter 3 includes inversion circuits 3 a and 3 b Rectification circuit 1 a includes transistors Q 1 . Q 2 , diodes D 1 , D 2 , a reactor 11 , and a capacitor 12 . Rectification circuit 1 b includes transistors Q 3 , Q 4 , diodes D 3 , D 4 , a reactor 13 , and a capacitor 14 . Inversion circuit 3 a includes transistors Q 5 , Q 6 , diodes D 5 , 06 , a reactor 15 , and a capacitor 16 . Inversion circuit 3 b includes transistors Q 7 , Q 8 , diodes D 7 , D 8 , a reactor 17 , and a capacitor 18 . Each of transistors Q 1 to Q 8 is an insulated gate bipolar transistor (IGBT), for example.

Collectors of transistors Q 1 , Q 3 , Q 5 , and Q 7 are connected to DC positive bus L 1 . Emitters of transistors Q 1 , Q 3 , Q 5 , and Q 7 are connected to collectors of transistors Q 2 , Q 4 , Q 6 , and Q 8 , respectively. Emitters of transistors Q 2 , Q 4 , Q 6 , and Q 8 are connected to DC negative bus L 2 . Each of transistors Q 1 to Q 8 is pulse-width-modulation (PWM) controlled by control circuit 7 . Each of diodes D 1 to D 8 is connected in anti-parallel to a corresponding one of transistors Q 1 to Q 8 .

Reactors 11 and 13 have one terminals connected to emitters of transistors Q 1 and Q 3 , respectively, and the other terminals connected to the other terminals of switches S 1 and S 2 , respectively, and also connected to DC neutral point bus L 3 through capacitors 12 and 14 , respectively. Reactors 15 and 17 have one terminals connected to emitters of transistors Q 5 and Q 7 , respectively, and the other terminals connected to one terminals of switches S 5 and S 6 , respectively, and also connected to DC neutral point bus L 3 through capacitors 16 and 18 , respectively.

In rectification circuit 1 a , when transistor Q 1 is turned on in a time period during which AC voltage VI 1 supplied from commercial AC power supply 51 to input terminal TI 1 is a positive voltage, a current flows through a path extending through input terminal TI 1 , switch S 1 , reactor 11 , transistor Q 1 . DC positive bus L 1 , capacitor C 1 , DC neutral point bus L 3 , and input terminal TI 3 . Thereby, capacitor C 1 is charged and positive DC voltage VD 1 is supplied to DC positive bus L 1 .

When transistor Q 2 is turned on in a time period during which AC voltage VI 1 supplied from commercial AC power supply 51 to input terminal TI 1 is a negative voltage, a current flows through a path extending through input terminal TI 3 , DC neutral point bus L 3 , capacitor C 2 , DC negative bus L 2 , transistor Q 2 , reactor 11 , switch S 1 , and input terminal TI 1 . Thereby, capacitor C 2 is charged and negative DC voltage VD 2 is supplied to DC negative bus L 2 .

Reactor 11 and capacitor 12 constitute a low-pass filter, which allows AC voltage VI 1 having a commercial frequency supplied from commercial AC power supply 51 to pass through transistors Q 1 and Q 2 , and which prevents the signal having a switching frequency generated in each of transistors Q 1 and Q 2 from passing therethrough to the commercial AC power supply 51 side.

In rectification circuit 1 b , when transistor Q 3 is turned on in a time period during which AC voltage VI 2 supplied from commercial AC power supply 51 to input terminal TI 2 is a positive voltage, a current flows through a path extending through input terminal TI 2 , switch S 2 , reactor 13 , transistor Q 3 , DC positive bus L 1 , capacitor C 1 . DC neutral point bus L 3 , and input terminal TI 3 . Thereby, capacitor C 1 is charged and positive DC voltage VD is supplied to DC positive bus L 1 .

When transistor Q 4 is turned on in a time period during which AC voltage VI 2 supplied from commercial AC power supply 51 to input terminal TI 2 is a negative voltage, a current flows through a path extending through input terminal TI 3 , DC neutral point bus L 3 , capacitor C 2 , DC negative bus L 2 , transistor Q 4 , reactor 13 , switch S 2 , and input terminal TI 2 . Thereby, capacitor C 2 is charged and negative DC voltage VD 2 is supplied to DC negative bus L 2 .

Reactor 13 and capacitor 14 constitute a low pass filter, which allows AC voltage VI 2 having a commercial frequency supplied from commercial AC power supply 51 to pass through transistors Q 3 and Q 4 , and which prevents the signal having a switching frequency generated in each of transistors Q 3 and Q 4 from passing therethrough to the commercial AC power supply 51 side.

Rectification circuit 1 a converts AC voltage VI 1 into DC voltages VD 1 and VD 2 , and converts AC power into DC power. Rectification circuit 1 b converts AC voltage VI 2 into DC voltages VD 1 and VD 2 , and converts AC power into DC power.

In inversion circuit 3 a , when transistor Q 5 is turned on, a positive current flows through a path extending through DC positive bus L 1 , transistor Q 5 , reactor 15 , switch S 5 , output terminal TO 1 , load 53 , output terminal TO 3 , and DC neutral point bus L 3 . In contrast, when transistor Q 6 is turned on, a negative current flows through a path extending through DC negative bus L 2 , transistor Q 6 , reactor 15 , switch S 5 , output terminal TO 1 , load 53 , output terminal TO 3 , and DC neutral point bus L 3 .

Reactor 15 and capacitor 16 constitute a low pass filter, which allows AC voltage VO 1 having a commercial frequency generated by each of transistors Q 5 and Q 6 through load 53 , and which prevents the signal having a switching frequency generated in each of transistors Q 5 and Q 6 from passing therethrough to the load 53 side. In other words, reactor 15 and capacitor 16 each serve to convert a rectangular wave-shaped AC voltage generated by turning on and off each of transistors Q 5 and Q 6 into a sinusoidal wave-shaped AC voltage VO 1 , and supply the converted AC voltage VO 1 to load 53 .

In inversion circuit 3 b , when transistor Q 7 is turned on, a positive current flows through a path extending through DC positive bus L 1 , transistor Q 7 , reactor 17 , switch S 6 , output terminal TI 2 , load 53 , output terminal TI 3 , and DC neutral point bus L 3 . In contrast, when transistor Q 8 is turned on, a negative current flows through a path extending through DC negative bus L 2 , transistor Q 8 , reactor 17 , switch S 6 , output terminal TO 2 , load 53 , output terminal TO 3 , and DC neutral point bus L 3 .

Reactor 17 and capacitor 18 constitute a low pass filter, which allows AC voltage VO 2 having a commercial frequency generated by each of transistors Q 7 and Q 8 to pass through load 53 , and which prevents the signal having a switching frequency generated in each of transistors Q 7 and Q 8 from passing therethrough to the load 53 side. In other words, reactor 17 and capacitor 18 each serve to convert the rectangular wave-shaped AC voltage generated by turning on and off each of transistors Q 7 and Q 8 into a sinusoidal wave-shaped AC voltage VO 2 , and supply the converted AC voltage VO 2 to load 53 .

Inversion circuit 3 a converts DC voltages VD 1 and VD 2 into AC voltage VO 1 , and converts DC power into AC power. Inversion circuit 3 b converts DC voltages VD 1 and VD 2 into AC voltage VO 2 , and converts DC power into AC power.

Referring back to FIG. 1 , switches S 7 and S 8 (bypass switch pair) have one terminals connected to input terminals TI 1 and TI 12 , respectively, and the other terminals connected to output terminals TO 1 and TO 2 , respectively. Semiconductor switches S 9 and S 10 (semiconductor switch pair) are connected in parallel to switches S 7 and S 8 , respectively. Semiconductor switches S 9 and S 10 include thyristors connected in anti-parallel with each other, for example. Input terminal TI 3 is directly connected to output terminal TO 3 .

Switches S 7 and S 8 are controlled by control circuit 7 to be turned off in the inverter power feeding mode in which the two-phase AC power generated by inverter 3 is supplied to load 53 , and turned on in the bypass power feeding mode in which the two-phase AC power from commercial AC power supply 51 is directly supplied to load 53 .

Semiconductor switches S 9 and S 10 are turned on by a prescribed time period when the inverter power feeding mode is switched to the bypass power feeding mode. The response speeds of semiconductor switches S 9 and S 10 are sufficiently higher than the response speeds of switches S 7 and S 8 . Semiconductor switches S 9 and S 10 are turned on by a prescribed time period, which is for the purpose of preventing semiconductor switches S 9 and S 10 from being damaged by heat generated in semiconductor switches S 9 and S 10 .

For example, when a failure occurs in inverter 3 in the inverter power feeding mode, semiconductor switches S 9 and S 10 are instantaneously turned on, and the two-phase AC power from commercial AC power supply 51 is supplied to load 53 through semiconductor switches S 9 and S 10 Then, switches S 7 and S 8 with slow response time are turned on, switches S 5 and S 6 with slow response time are turned off, and then, semiconductor switches S 9 and S 10 are turned off.

Input voltage detection circuit 4 detects voltages VI 1 , VI 2 and VN on input terminals TI 1 , TI 2 and TI 3 , respectively, and supplies a signal indicating the detected value to control circuit 7 . Abnormality detector 5 determines whether a part corresponding to input voltage VI 1 in input voltage detection circuit 4 is normal or not, and outputs a signal ϕ 5 indicating the determination result to control circuit 7 . Output voltage detection circuit 6 detects voltages VO 1 , VO 2 and VN on output terminals TO 1 , TO 2 and TO 3 , respectively, and supplies a signal indicating the detected value to control circuit 7 . Control circuit 7 controls the entire uninterruptible power supply device based on the output signals from input voltage detection circuit 4 , abnormality detector 5 , output voltage detection circuit 6 , and IC voltage detectors DT 1 to DT 3 .

Specifically, input voltage detection circuit 4 includes input terminals T 1 to T 3 , output terminals TI 1 to TI 3 , and voltage detectors 4 a to 4 c , as shown in FIG. 3 . Input terminals T 1 , T 2 and T 3 are connected to input terminals TI 1 , TI 2 and TI 3 , respectively, and receive an AC voltage VI 1 , an AC voltage VI 2 and a neutral point voltage VN, respectively.

Voltage detector 4 a includes: a plurality of (five in the figure) resistance elements 21 connected in series between input terminal T 1 and output terminal T 11 ; and a plurality of (two in the figure) resistance elements 22 connected in series between output terminal T 11 and the line of reference voltage VSS. An AC voltage VI 11 D, which is obtained by dividing AC voltage VI 1 by a prescribed voltage dividing ratio, appears on output terminal TI 1 .

Each of voltage detectors 4 b and 4 c has the same configuration as that of voltage detector 4 a . An AC voltage VI 2 D, which is obtained by dividing AC voltage VI 2 by a prescribed voltage dividing ratio, appears on output terminal TI 2 . A voltage VND, which is obtained by dividing neutral point voltage VN by a prescribed voltage dividing ratio, appears on output terminal T 13 . Voltages VI 1 D. VI 2 D and VND on output terminals T 11 , T 12 and T 13 are supplied to control circuit 7 as output signals from voltage detectors 4 a . 4 b and 4 c , respectively.

Output signal VI 1 D from voltage detector 4 a is used for controlling each of transistors Q 1 to Q 8 included in converter 1 and inverter 3 , that is, for controlling the phases of output voltages VO 1 and VO 2 . Output signal VI 2 D from voltage detector 4 b is used for detecting that the effective value of AC voltage VI 2 falls outside of the allowable range, that is, for detecting that supply of the two-phase AC power from commercial AC power supply 51 is stopped (that a power failure occurs).

As shown in FIG. 4 , abnormality detector 5 includes effective value calculators (RMS) 31 , 32 , a subtractor 33 , an absolute value calculator (ABS) 34 , and a comparator 35 . Effective value calculator 31 calculates the effective value of output signal VI 1 D from voltage detector 4 a . Effective value calculator 32 calculates the effective value of output signal VI 2 D from voltage detector 4 b Subtractor 33 calculates the difference between the effective value of signal VI 1 D calculated by effective value calculator 31 and the effective value of signal VI 2 D calculated by effective value calculator 32 .

Absolute value calculator 34 calculates an absolute value A 1 of the difference between the effective value of signal VI 1 D and the effective value of signal VI 2 D that are calculated by subtractor 33 . Comparator 35 compares absolute value A 1 calculated by absolute value calculator 34 and a threshold value VT 1 . Then, in the case where A 1 <VT 1 , comparator 35 sets an abnormality detection signal ϕ 5 at an “L” level as a deactivation level. In the case where A 1 >VT 1 , comparator 35 sets abnormality detection signal ϕ 5 at an “H” level as an activation level.

When voltage detectors 4 a and 4 b normally function, the effective values of signals VID 1 and VID 2 are the same, so that absolute value A 1 becomes zero, in which case A 1 ≤VT 1 . Thus, abnormality detection signal ϕ 5 turns into an “L” level as a deactivation level. When an abnormality occurs in voltage detector 4 a , there occurs a difference between the effective values of signals VID 1 and VID 2 . Thus, absolute value A 1 becomes large, which leads to A 1 >VT 1 , so that abnormality detection signal ϕ 5 turns into an “H” level as an activation level.

In addition, there is an extremely low possibility that abnormalities occur simultaneously in voltage detectors 4 a and 4 b . When an abnormality occurs in voltage detector 4 b , the effective value of output signal VI 2 D from voltage detector 4 b exceeds the allowable range. Accordingly it is determined that a power failure occurs. Thus, when abnormality detection signal ϕ 5 is turned into an “H” level, an abnormality occurs in voltage detector 4 a.

FIGS. 5( a ) to 5( d ) each are a diagram showing the state where an abnormality occurs in voltage detector 4 a . FIG. 5( a ) shows the state where resistance element 21 is ruptured. In this case, signal VI 1 D becomes 0V. Thus, the effective value of signal VI 1 D is smaller than that in the state where voltage detector 4 a normally functions, so that abnormality detection signal ϕ 5 turns into an “H” level as an activation level. FIG. 5( b ) shows the state where resistance element 22 is ruptured. In this case, AC voltage VI 1 is output as signal VI 1 D as it is, the effective value of signal VI 1 D is larger than that in the state where voltage detector 4 a normally functions. Thus, abnormality detection signal ϕ 5 turns into an “H” level as an activation level.

FIG. 5( c ) shows the state where a short circuit occurs between the terminals of resistance element 21 . In this case, the effective value of signal VI 1 D is larger than that in the state where voltage detector 4 a normally functions, and abnormality detection signal ϕ 5 turns into an “H” level as an activation level FIG. 5( d ) shows the state where a short circuit occurs between the terminals of resistance element 22 . In this case, the effective value of signal VI 1 D is smaller than that in the state where voltage detector 4 a normally functions, and abnormality detection signal ϕ 5 turns into an “H” level as an activation level.

As shown in FIG. 6 , output voltage detection circuit 6 includes input terminals T 21 to T 23 , output terminals T 31 to T 133 , and voltage detectors 6 a to 6 c . Input terminals T 21 . T 22 and T 23 are connected to output terminals TO 1 , TO 2 and TO 3 , respectively, and receive AC voltage VO 1 , AC voltage VO 2 and neutral point voltage VN, respectively.

Voltage detector 6 a includes a plurality of (five in the figure) resistance elements 21 connected in series between input terminal T 21 and output terminal T 31 , and a plurality of (two in the figure) resistance elements 22 connected in series between output terminal T 31 and the line of reference voltage VSS. An AC voltage VO 1 D, which is obtained by dividing AC voltage VO 1 by a prescribed voltage dividing ratio, appears on output terminal T 21 .

Each of voltage detectors 6 b and 6 c has the same configuration as that of voltage detector 6 a . An AC voltage VO 2 D, which is obtained by dividing AC voltage VO 2 by a prescribed voltage dividing ratio, appears on output terminal T 32 . A voltage VND, which is obtained by dividing neutral point voltage VN by the prescribed voltage dividing ratio, appears on output terminal T 33 Voltages VO 1 D, VO 2 D and VND on output terminals T 31 . T 32 and T 33 are supplied to control circuit 7 as output signals from voltage detectors 6 a . 6 b and 6 c , respectively.

Control circuit 7 controls the entire uninterruptible power supply device based on output signals VI 1 D, VI 2 D and VND from voltage detectors 4 a , 4 b and 4 c , output signal ϕ 5 from abnormality detector 5 , output signals VO 1 D. VO 2 D and VND from voltage detectors 6 a , 6 b and 6 c , output signals from DC voltage detectors DT 1 , TT 2 and DT 3 .

In other words, when abnormality detection signal ϕ 5 is at an “L” level as a deactivation level in the inverter power feeding mode, control circuit 7 controls converter 1 in synchronization with output signal VI 1 D from voltage detector 4 a to convert AC voltage VI 1 into DC voltages VD 1 and VD 2 , and convert AC voltage VI 2 into DC voltages VD 1 and VD 2 . In this case, control circuit 7 controls inverter 3 such that the phase of output signal VO 1 D from voltage detector 6 a matches with the phase of output signal VI 1 D from voltage detector 4 a.

When abnormality detection signal ϕ 5 is turned into an “H” level as an activation level in the inverter power feeding mode, control circuit 7 stops the operation of converter 1 to fix each of transistors Q 1 to Q 4 in the OFF state, so as to turn off switches S 1 and S 2 Control circuit 7 controls bidirectional chopper 2 to cause each of capacitors C 1 and C 2 to be charged with DC power of battery 52 . Control circuit 7 controls inverter 3 such that the phase of output signal VO 1 D from voltage detector 6 a matches with the phase of the monitor signal obtained by advancing the phase of output signal VI 2 D from voltage detector 4 b by 180 degrees.

When voltage VB across terminals of battery 52 decreases and reaches discharge cut-off voltage VBL, control circuit 7 stops the operation of bidirectional chopper 2 , to turn on semiconductor switches S 9 , S 10 and switches S 7 , S 8 , and to turn off switches S 5 and S 6 . Thereby, the two-phase AC power from commercial AC power supply 51 is supplied to load 53 without instantaneous interruption.

When a failure occurs in inverter 3 in the inverter power feeding mode, control circuit 7 turns on semiconductor switches S 9 . S 10 and switches S 7 , S 8 and turns off switches S 5 . S 6 . Thereby, the two-phase AC power from commercial AC power supply 51 is supplied to load 53 without instantaneous interruption.

When supply of the two-phase AC power from commercial AC power supply 51 is stopped in the inverter power feeding mode (that is, when a power failure occurs), control circuit 7 stops the operation of converter 1 to fix each of transistors Q 1 to Q 4 in the OFF state, so as to turn off switches S 1 and S 2 . Control circuit 7 controls bidirectional chopper 2 to cause each of capacitors C 1 and C 2 to be charged with DC power from battery 52 .

Control circuit 7 stores the phase of output signal VI 1 D from voltage detector 4 a before occurrence of a power failure. This control circuit 7 controls inverter 3 such that the stored phase of signal VI 1 D matches with the phase of output signal VO 1 D from voltage detector 6 a . When voltage VB across terminals of battery 52 decreases and reaches discharge cut-off voltage VBL, control circuit 7 stops the operations of bidirectional chopper 2 and inverter 3 , to turn off switches S 5 and S 6 . Accordingly, even when a power failure occurs, the operation of load 53 can be continued in the time period during which DC power is stored in battery 52 .

FIG. 7 is a block diagram showing a main part in control circuit 7 . In FIG. 7 , control circuit 7 receives output signal VO 1 D from voltage detector 6 a , output signal VI 1 D from voltage detector 4 a , output signal VI 2 D from voltage detector 4 b , selection signals SE 1 , SE 2 , and abnormality detection signal ϕ 5 .

Signal VO 1 D is obtained by dividing output voltage VO 1 from inversion circuit 3 a by voltage detector 6 a , and provided as a signal that varies in a sinusoidal waveform in a commercial frequency. Signal VI 1 D is obtained by dividing AC voltage VI 1 from commercial AC power supply 51 by voltage detector 4 a , and provided as a signal that varies in a sinusoidal waveform in a commercial frequency. Signal VI 2 D is obtained by dividing AC voltage VI 2 from commercial AC power supply 51 by voltage detector 4 b , and provided as a signal that varies in a sinusoidal waveform in a commercial frequency.

FIG. 8 is a time chart showing waveforms of signals VI 1 D and VI 2 D. As shown in FIG. 8 , the phase of signal VI 2 D delays by 180 degrees from the phase of signal VI 1 D. The phase of signal VI 2 D is advanced by 180 degrees, so that a monitor signal in phase with signal VI 1 D can be generated.

In Japan, the phase of signal VI 2 D delays by 180 degrees from the phase of signal VI D. In North America, the phase of signal VI 2 D delays by 120 degrees from the phase of signal VI 1 D, for example. In this case, the phase of signal VI 2 D is advanced by 120 degrees, so that a monitor signal in phase with signal VI 1 D can be generated.

Referring back to FIG. 7 , selection signal SE is set at an “H” level in Japan, and set at an “L” level in North America Selection signal SE 2 serves as a signal used for setting whether the phase of signal VI 2 D is to be converted or not. In other words, the uninterruptible power supply device in the present first embodiment can also be used as an uninterruptible power supply device of a single-phase two-wire type. In this case, input terminals TI 1 and TI 2 are connected to each other, and receive AC voltage VI 1 from commercial AC power supply 51 , and input terminal TI 3 receives neutral point voltage VN. Output terminals TO 1 and TO 2 are connected to each other and used for outputting AC voltage VO 1 The load receives AC voltage VO 1 from output terminals TO 1 and TO 2 and receives neutral point voltage VN from output terminal TO 3 . The load includes an electrical device of 100V.

In this case, since the phase of signal VI 1 D matches with the phase of signal VI 2 D, the phase of signal VI 2 D does not have to be converted. Selection signal SE 2 is turned into an “H” level when the phase of signal VI 2 D is converted, but turned into an “L,” level when the phase of signal VI 2 D is not converted.

As described above, abnormality detection signal ϕ 5 is turned into an “H” level when an abnormality occurs in voltage detector 4 a , and turned into an “L” level when an abnormality does not occur in voltage detector 4 a.

Control circuit 7 includes a phase conversion unit 41 , switching circuits 42 and 43 , a phase comparison unit 44 , and a PWM control unit 45 . When selection signal SE 1 is turned into an “H” level for the purpose of allowing an uninterruptible power supply device to be used in Japan, phase conversion unit 41 generates a monitor signal, which is obtained by advancing the phase of output signal VI 2 D from voltage detector 4 b by 180 degrees. When selection signal SE 1 is turned into an “L” level for the purpose of allowing an uninterruptible power supply device to be used in North America, phase conversion unit 41 generates a monitor signal, which is obtained by advancing the phase of output signal VI 2 D from voltage detector 4 b by 120 degrees.

Switching circuit 42 receives signal VI 2 D and the output signal from phase conversion unit 41 . Then, when signal SE 2 is turned into an “H” level for converting the phase of signal VI 2 D, switching circuit 42 selects the output signal from phase conversion unit 41 and supplies the selected output signal to switching circuit 43 . When signal SE 2 is turned into an “L” level since the phase of signal VI 2 D does not have to be converted, switching circuit 42 selects signal VI 2 D and supplies the selected signal VI 2 D to switching circuit 43 .

When abnormality detection signal ϕ 5 is turned into an “L” level since voltage detector 4 a normally functions, switching circuit 43 supplies signal VI 1 D to phase comparison unit 44 . When abnormality detection signal ϕ 5 is turned into an “H” level since an abnormality occurs in voltage detector 4 a , switching circuit 43 supplies the signal supplied from switching circuit 42 to phase comparison unit 44 .

Phase comparison unit 44 compares the phase of signal VO 1 D with the phase of the signal (for example, signal VI 1 D) supplied from switching circuit 43 , and outputs a signal indicating the comparison result. Specifically, phase comparison unit 44 detects a first zero cross point at which signal VO 1 D becomes 0V when it changes from a negative voltage to a positive voltage and a second zero cross point at which the signal supplied from switching circuit 43 (for example, signal VI 1 D) becomes 0V when it changes from a negative voltage to a positive voltage. Then, phase comparison unit 44 detects a phase difference Δθ (degree) between the first zero cross point and the second zero cross point, and outputs a signal indicating the detected value.

Based on the output signal from phase comparison unit 44 , PWM control unit 45 adjusts the timing at which each of transistors Q 5 to Q 8 in inverter 3 is turned on/off such that phase difference Δθ between the first zero cross point and the second zero cross point becomes zero degree.

FIGS. 9( a ), 9( b ) and FIGS. 10( a ), 10( b ) each are a diagram schematically showing the operation of the uninterruptible power supply device. FIGS. 9 ( a ), ( b ) and FIGS. 10 ( a ), ( b ) each show only an area related to AC voltage VI 1 in one phase for the sake of simplification of illustration and description, but do not show bidirectional chopper 2 and the like.

In FIG. 9( a ) , when voltage detector 4 a normally functions in the inverter power feeding mode, switches S 1 and S 5 are turned on while switch S 7 and semiconductor switch S 9 are turned off. Then, a current II, flows from commercial AC power supply 51 to load 53 through input terminal TI 1 , switch S 1 , rectification circuit 1 a , inversion circuit 3 a , switch S 5 , and output terminal TO 1 . In this case, control circuit 7 controls inversion circuit 3 a in synchronization with output signal VI 1 D from voltage detector 4 a so as to cause the phase of output voltage VO 1 from inversion circuit 3 a to match with the phase of AC voltage VI 1 from commercial AC power supply 51 .

In FIG. 9( b ) , when an abnormality occurs in voltage detector 4 a , the operation of rectification circuit 1 a is stopped and switch S 1 is turned off. Then, current II, flows from battery 52 to load 53 through inversion circuit 3 a , switch S 5 and output terminal 101 . In this case, control circuit 7 controls inversion circuit 3 a in synchronization with output signal VI 2 D from voltage detector 4 b in place of voltage detector 4 a to cause the phase of output voltage VO 1 from inversion circuit 3 a to match with the phase of AC voltage VI 1 from commercial AC power supply 51 .

In FIG. 10( a ) , when voltage VB across terminals of battery 52 decreases and reaches discharge cut-off voltage VBL, semiconductor switch S 9 is instantaneously turned on. Then, current IL flows from commercial AC power supply 51 into load 53 through input terminal TI 1 , semiconductor switch S 9 and output terminal TO 1 .

In addition, the control electrode of semiconductor switch S 9 and the control electrode of switch S 7 are simultaneously supplied with signals for turning on these control electrodes. In this case, since the response speed of semiconductor switch S 9 is higher than the response speed of switch S 7 , switch S 7 is turned on after semiconductor switch S 9 is instantaneously turned on. There may be a time period in which each of semiconductor switch S 9 and switch S 5 is turned on, and AC power is supplied to load 53 from each of commercial AC power supply 51 and inversion circuit 3 a.

In FIG. 10( b ) , switch S 7 is turned on, switch S 5 is turned off, and then, semiconductor switch S 9 is turned off. Then, current IL flows from commercial AC power supply 51 into load 53 through input terminal TI 1 , switch S 7 and output terminal TO 1 . In this way, in the present first embodiment, even when an abnormality occurs in voltage detector 4 a , the two-phase AC power is supplied to load 53 without instantaneous interruption.

FIGS. 11( a ) and 11( b ) are diagrams showing comparative examples of the present first embodiment, and illustrated as compared with FIGS. 10( a ) and 10( b ) . In this comparative example, when an abnormality occurs in voltage detector 4 a , output signal VI 2 D from voltage detector 4 b cannot be used in place of output signal VI 1 D from voltage detector 4 a.

In FIG. 11( a ) , the operation performed when voltage detector 4 a normally functions in the inverter power feeding mode is the same as that in the first embodiment. Thus, switches S 1 and S 5 are turned on while switch S 7 and semiconductor switch S 9 are turned off. Then, current IL flows from commercial AC power supply 51 into load 53 through input terminal TI 1 , switch S 1 , rectification circuit 1 a , inversion circuit 3 a , switch S 5 , and output terminal TO 1 . In this case, control circuit 7 controls inversion circuit 3 a in synchronization with output signal VI 1 D from voltage detector 4 a to cause the phase of output voltage VO 1 from inversion circuit 3 a to match with the phase of AC voltage VI 1 from commercial AC power supply 51 .

In FIG. 11( b ) , when an abnormality occurs in voltage detector 4 a , the operation of rectification circuit 1 a is stopped and switch S 1 is turned off. Then, current IL flows from battery 52 into load 53 through inversion circuit 3 a , switch S 5 and output terminal TO 1 . In this case, control circuit 7 controls inversion circuit 3 a based on the phase information stored before occurrence of an abnormality. Accordingly, the phase of output voltage VO 1 from inversion circuit 3 a cannot be matched with the phase of AC voltage VI 1 from commercial AC power supply 51 .

In FIG. 12( a ) , when voltage VB across terminals of battery 52 decreases and reaches discharge cut-off voltage VBL, the operation of inversion circuit 3 a is stopped. In this case, since the phase of VO 1 and the phase of VI 1 do not necessarily match with each other, semiconductor switch S 9 cannot be turned on, so that power supply to load 53 is stopped for a moment.

In FIG. 12( b ) , switch S 7 is turned on while switch S 5 is turned off. Then, current IL flows from commercial AC power supply 51 into load 53 through input terminal T 11 switch S 7 and output terminal TO 1 . In this way, in the comparative example, when an abnormality occurs in voltage detector 4 a , supply of the two-phase AC power to load 53 is instantaneously interrupted.

As described above, in the present first embodiment, when an abnormality occurs in voltage detector 4 a , inverter 3 is controlled in synchronization with output signal VI 2 D from voltage detector 4 b to cause the phases of output voltages VO 1 and VO 2 from inverter 3 to match with the phases of AC voltages VI 1 and VI 2 , respectively. Then, semiconductor switches S 9 , S 10 and switches S 7 , S 8 are turned on while switches S 5 and S 6 are turned off. Accordingly, even when an abnormality occurs in voltage detector 4 a , the two-phase AC voltage can be supplied to load 53 without instantaneous interruption.

Second Embodiment

In the first embodiment, when an abnormality occurs in voltage detector 4 a , inverter 3 is controlled using output signal VI 2 D from voltage detector 4 b in place of output signal VI 1 D from voltage detector 4 a In contrast, in the present second embodiment, a preliminary voltage detector 4 d is provided. Thus, when an abnormality occurs in voltage detector 4 a , inverter 3 is controlled using an output signal VI 1 DA from preliminary voltage detector 4 d in place of output signal VI 1 D from voltage detector 4 a.

FIG. 13 is a circuit diagram showing the configuration of an input voltage detection circuit 4 A included in an uninterruptible power supply device according to the second embodiment of the present invention, and illustrated as compared with FIG. 3 . Referring to FIG. 13 , this input voltage detection circuit 4 A is different from input voltage detection circuit 4 in FIG. 3 in that it additionally includes preliminary voltage detector 4 d and output terminal TI 4 .

Voltage detector 4 d includes a plurality of (five in the figure) resistance elements 21 connected in series between input terminal T 1 and output terminal T 14 , and a plurality of (two in the figure) resistance elements 22 connected in series between output terminal TI 1 and the line of reference voltage VSS. An AC voltage VI 1 DA, which is obtained by dividing AC voltage VI 1 by a prescribed voltage dividing ratio, appears on output terminal TI 4 . AC voltage VI 1 D is the same as AC voltage VI 1 D appearing on output terminal T 11 . Voltages VI 1 D, VI 2 D, VND, and V 1 DA on output terminals TI 1 , TI 2 , TI 3 , and TI 4 are supplied to control circuit 7 A as output signals from voltage detectors 4 a , 4 b , 4 c , and 4 d , respectively.

FIG. 14 is a block diagram showing a main part in control circuit 7 A, and illustrated as compared with FIG. 7 . Referring to FIG. 14 , control circuit 7 A is different from control circuit 7 in FIG. 7 in that it does not include phase conversion unit 41 and switching circuit 42 .

Switching circuit 43 receives output signal VI 1 D from voltage detector 4 a and output signal VI 1 DA from preliminary voltage detector 4 d . Then, when abnormality detection signal ϕ 5 is turned into an “L” level since voltage detector 4 a normally functions, switching circuit 43 supplies signal VI 1 D to phase comparison unit 44 . When abnormality detection signal ϕ 5 is turned into an “H” level since an abnormality occurs in voltage detector 4 a , switching circuit 43 supplies signal VI 1 DA to phase comparison unit 44 . Since other configurations and operations are the same as those in the first embodiment, the description thereof will not be repeated.

In the present second embodiment, when an abnormality occurs in voltage detector 4 a , inverter 3 is controlled in synchronization with output signal VI 1 DA from preliminary voltage detector 4 d to cause the phases of output voltages VO 1 and VO 2 from inverter 3 to match with the phases of AC voltages VI 1 and VI 2 , respectively. Then, semiconductor switches S 9 . S 10 and switches S 7 . S 8 are turned on while switches S 5 , S 6 are turned off. Accordingly, even when an abnormality occurs in voltage detector 4 a , the two-phase AC voltage can be supplied to load 53 without instantaneous interruption.

It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the meaning and scope equivalent to the terms of the claims.

TI 1 to TI 3 , T 1 to T 3 , T 21 to T 23 input terminal, TB 1 , TB 2 battery terminal, TO 1 to TO 3 , TI 1 to TI 4 , T 31 to T 33 output terminal, S 1 to S 8 switch, S 9 , S 10 semiconductor switch, 1 converter, 1 a , 1 b rectification circuit, L 1 DC positive bus, L 2 DC negative bus, L 3 DC neutral point bus, C 1 , C 2 , 12 , 14 , 16 , 18 capacitor, 2 bidirectional chopper, 3 inverter. 3 a , 3 b inversion circuit, 4 , 4 A input voltage detection circuit, 4 a to 4 d . 6 a to 6 c voltage detector, 5 abnormality detector, 6 output voltage detection circuit, DT 1 to DT 3 DC voltage detector, 7 , 7 A control circuit, Q 1 to Q 8 transistor, D 1 to D 8 diode, 11 , 13 , 15 , 17 reactor, 21 , 22 resistance element, 31 , 32 effective value calculator, 33 subtractor, 34 absolute value calculator, 35 comparator, 41 phase conversion unit, 42 , 43 switching circuit, 44 phase comparison unit, 45 PWM control unit, 51 AC power supply, 52 battery, 53 load.