Pixel sensing circuit and driving method therefor, image sensor, and electronic device

The application is a U.S. National Phase Entry of International Application No. PCT/CN2017/087181 filed on Jun. 5, 2017, designating the United States of America and claiming priority to Chinese Patent Application No. 201610985469.4, filed Nov. 9, 2016. The present application claims priority to and the benefit of the above-identified applications and the above-identified applications are incorporated by reference herein in their entirety.

Embodiments of the present disclosure relate to a pixel sensing circuit and driving method therefor, an image sensor, and an electronic device.

Active pixel sensor (APS) is used to convert light image into electrical signals, and is widely used in digital camera, mobile phone with camera, vision system, and so on. Active pixel sensors can be divided into Charge Coupled Device (CCD) type and Complementary Metal Oxide Semiconductor (CMOS) type. A CMOS-type APS can be manufactured on a silicon substrate through a semiconductor manufacturing process, thus the CMOS-type APS can be easily integrated with a peripheral system having an amplifier circuit and a signal processing module. Compared with a CCD-type APS, a CMOS-type APS has lower manufacturing costs, higher processing speed and lower power consumption.

An embodiment of the present disclosure provides a pixel sensing circuit, comprising: a photoelectric conversion element configured to generate electric charges in response to incident light; a transmission element configured to output the electric charges generated by the photoelectric conversion element; and a source follower circuit configured to compensate an output current of the transmission element. The source follower circuit comprises a first source follower transistor, a second source follower transistor and a first storage capacitor, the first source follower transistor and the second source follower transistor have threshold voltages equal to each other, a gate electrode of the first source follower transistor, an output terminal of the first source follower transistor, a gate electrode of the second source follower transistor, and a first end of the first storage capacitor are all coupled to a first node, and a second end of the first storage capacitor and an input terminal of the second source follower transistor are coupled to a supply voltage line.

For example, the pixel sensing circuit provided by an embodiment of the present disclosure further comprises a readout element, the readout element is configured to transmit an output current of the source follower circuit to an external circuit in response to a selection signal, and an output terminal of the second source follower transistor is coupled to an input terminal of the readout element.

For example, the pixel sensing circuit provided by an embodiment of the present disclosure further comprises a first reset element, the first reset element is configured to reset a voltage at an output node of the photoelectric conversion element, and the output node is coupled to an input terminal of the transmission element.

For example, the pixel sensing circuit provided by an embodiment of the present disclosure further comprises a switching element, and the switching element is coupled between the output node and the photoelectric conversion element.

For example, the pixel sensing circuit provided by an embodiment of the present disclosure further comprises a second photoelectric conversion element which is configured to generate electric charges in response to the incident light and a second switching element, and the second switching element is coupled between the output node and the second photoelectric conversion element.

For example, the pixel sensing circuit provided by an embodiment of the present disclosure further comprises a second storage capacitor, a first end of the second storage capacitor is coupled to the output node, and a second end of the second storage capacitor is coupled to ground or a common voltage.

For example, the pixel sensing circuit provided by an embodiment of the present disclosure further comprises a second reset element, and the second reset element is configured to reset a voltage of the first node.

For example, in the pixel sensing circuit provided by an embodiment of the present disclosure, the first reset element and the second reset element are coupled to a same reset signal line.

For example, in the pixel sensing circuit provided by an embodiment of the present disclosure, the transmission element, the switching element, the first reset element or the second reset element comprises transistors.

For example, in the pixel sensing circuit provided by an embodiment of the present disclosure, the transistors are N-type transistors or P-type transistors.

For example, in the pixel sensing circuit provided by an embodiment of the present disclosure, the photoelectric conversion element comprises a photodiode.

Another embodiment of the present disclosure provides an image sensor, comprising a plurality of pixel units arranged in an array, and at least one pixel unit comprising any one of the pixel sensing circuits described above.

For example, the image sensor provided by an embodiment of the present disclosure is prepared on a silicon substrate.

Further another embodiment of the present disclosure provides an electronic device, comprising the image sensor described above.

Still further another embodiment of the present disclosure provides a driving method for the pixel sensing circuit described above, comprising: generating the electric charges in response to the incident light by the photoelectric conversion element; outputting the electric charges generated by the photoelectric conversion element to the source follower circuit by the transmission element; and compensating the output current of the transmission element by the source follower circuit.

For example, the pixel sensing circuit provided by an embodiment of the present disclosure further comprises a readout element, and an output terminal of the second source follower transistor is coupled to an input terminal of the readout element. Accordingly, the method further comprises: transmitting an output current of the source follower circuit to an external circuit in response to a selection signal by the readout element.

For example, the pixel sensing circuit provided by an embodiment of the present disclosure further comprises a first reset element, and an output node is coupled to an input terminal of the transmission element. Accordingly, the method further comprises: resetting a voltage at the output node of the photoelectric conversion element by the first reset element before generating the electric charges in response to the incident light by the photoelectric conversion element.

For example, the pixel sensing circuit provided by an embodiment of the present disclosure further comprises a switching element and a second storage capacitor, the switching element is coupled between the output node and the photoelectric conversion element, a first end of the second storage capacitor is coupled to the output node, and a second end of the second storage capacitor is coupled to ground or a common voltage. Accordingly, the method further comprises: turning on the switching element, storing the electric charges in the second storage capacitor, and then outputting the electric charges generated by the photoelectric conversion element to the source follower circuit by the transmission element after generating the electric charges in response to the incident light by the photoelectric conversion element.

For example, the pixel sensing circuit provided by an embodiment of the present disclosure further comprises a second reset element. Accordingly, the method further comprises: resetting a voltage of the first node by the second reset element before outputting the electric charges generated by the photoelectric conversion element to the source follower circuit by the transmission element.

For example, in the driving method for the pixel sensing circuit provided by an embodiment of the present disclosure, resetting of the voltage at the output node of the photoelectric conversion element by the first reset element and resetting of the voltage of the first node by the second reset element are performed by a same reset signal.

In order to clearly illustrate the technical solution of the embodiments of the disclosure, the drawings of the embodiments will be briefly described in the following. It is obvious that the described drawings are only related to some embodiments of the disclosure and thus are not limitative of the disclosure.

FIG. 1 is a schematic block diagram illustrating a CMOS image sensor;

FIG. 2 is a circuit diagram illustrating a CMOS active pixel sensing circuit with a four-transistor configuration;

FIG. 3 is a circuit diagram illustrating a CMOS active pixel sensing circuit with a three-transistor configuration;

FIG. 4 is a schematic diagram of a pixel sensing circuit provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a pixel sensing circuit provided by another embodiment of the present disclosure;

FIG. 6A to FIG. 6D are schematic diagrams of operating processes of the pixel sensing circuit as illustrated in FIG. 5 ; and

FIG. 7 is a schematic diagram of a pixel sensing circuit provided by still another embodiment of the present disclosure.

In order to make objects, technical details and advantages of the embodiments of the disclosure apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the disclosure.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the description and the claims of the present application for disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. Also, the terms such as “a,” “an,” etc., are not intended to limit the amount, but indicate the existence of at least one. The terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. The phrases “connect”, “connected”, “coupled”, etc., are not intended to define a physical connection or mechanical connection, but may include an electrical connection, directly or indirectly. “On,” “under,” “right,” “left” and the like are only used to indicate relative position relationship, and when the position of the object which is described is changed, the relative position relationship may be changed accordingly.

FIG. 1 is a schematic block diagram illustrating a CMOS image sensor. As shown in FIG. 1 , the CMOS image sensor comprises a pixel unit array and a peripheral circuit, which, for example, can be integrated on a same silicon-based chip. The pixel unit array comprises pixel units arranged in an array. As shown in the drawing, the pixel unit array is arranged in a rectangle array in X and Y directions, and each of the pixel units in the rectangle array has its address in both the X and Y directions (for example, row and column directions) and can be selected by an address decoder in the two directions respectively via a corresponding row line and a corresponding column line. Output current/voltage signals are amplified, and then sent to an A/D converter for analog-digital conversion into digital signals for output.

Each of the pixel units of the above CMOS image sensor comprises an active pixel sensing circuit, and the active pixel sensing circuit may generally have a three-transistor configuration and a four-transistor configuration. In the four-transistor configuration, the CMOS active pixel sensor comprises a photodiode and four MOS transistors; and photogenerated charges that are produced and collected on the photodiode are sensed under a control of the four MOS transistors. In the three-transistor configuration, the CMOS active pixel sensor comprises a photodiode and three MOS transistors; and photogenerated charges that are produced and collected on the photodiode are sensed under a control of the three MOS transistors.

FIG. 2 is a circuit diagram illustrating a CMOS active pixel sensing circuit with a four-transistor configuration. Referring to FIG. 2 , the CMOS active pixel sensing circuit 100 comprises a photodiode PD, a transmission transistor M 11 , a reset transistor M 12 , a source follower transistor M 13 and a selection transistor M 14 .

When the gate voltage RG of the reset transistor M 12 increases and the reset transistor M 12 turns on, the electric potential of a sensing node (i.e., floating diffusion node FD) increases until it becomes equal to the level of a supply voltage VDD. The source follower transistor M 13 and the selection transistor M 14 sample the electric potential of the floating diffusion node FD, and the sampled electric potential is a reference electric potential.

During a light sensing accumulation phase period, when light is incident on the photodiode PD, electron-hole pairs (EHP) are generated in response to the incident light. When the gate voltage TG of the transmission transistor M 11 increases after the light sensing accumulation phase ends, electric charges accumulated (or stored) in the photodiode PD are transmitted to the floating diffusion node FD. When the electric potential of the floating diffusion node FD that is substantially proportional to the quantity of the transmitted electric charges decreases observably, the source electric potential of the source follower transistor M 13 changes. When the gate voltage SEL of the selection transistor M 14 increases, the selection transistor M 14 turns on, and the source voltage of the source follower transistor M 13 is output as an output voltage Vout. Light sensing is accomplished by measuring the difference between the reference electric potential and the output voltage Vout. After that, the reset operation and so on are repeated.

FIG. 3 is a circuit diagram illustrating a CMOS active pixel sensing circuit with a three-transistor configuration. Referring to FIG. 3 , the CMOS active pixel sensing circuit 200 comprises a photodiode PD, a transmission transistor M 21 , a reset transistor M 22 and a source follower transistor M 23 . The CMOS active pixel sensing circuit 200 with the three-transistor configuration may not comprise the selection transistor M 14 as shown in FIG. 2 , and, for example, a dynamic voltage source voltage DVD is employed.

When the gate voltage RG of the reset transistor M 22 increases and the reset transistor M 22 turns on while the dynamic voltage source voltage DVD has a high supply voltage, the electric potential of the sensing node (i.e., floating diffusion node FD) increases to the level of a high supply voltage. The source follower transistor M 23 samples the electric potential of the floating diffusion node FD and outputs the sampled electric potential to an external circuit. The sampled electric potential is a reference electric potential. After that, the dynamic voltage source voltage DVD is reduced to a low supply voltage.

During light sensing accumulation phase period, when light is incident on the photodiode PD, electron-hole pairs (EHP) are generated in response to the incident light. When the gate voltage TG of the transmission transistor M 21 increases after the light accumulation phase, electric charges accumulated (or stored) in the photodiode PD are transmitted to the floating diffusion node FD. When the electric potential of the floating diffusion node FD that is substantially proportional to the quantity of the transmitted electric charges decreases, and the dynamic voltage source voltage DVD has a high supply voltage, and the source voltage of the source follower transistor M 23 changes. The source voltage of the source follower transistor M 23 is output to an external circuit as an output voltage Vout. After that, the reset operation and so on is repeated as shown in FIG. 2 . The active pixel sensing circuit senses a signal based on the electric potential change of the floating diffusion node FD, i.e., light sensing is accomplished by measuring the difference between the reference electric potential and the output voltage Vout.

However, in the manufacturing process of semiconductor manufacturing process on the silicon substrate, there may be incurred device fluctuation as to the source followers in the active pixel sensing circuits in different pixel units due to heterogeneity of raw materials, process conditions, etc., so there is produced difference between the current amount that is finally sensed and the current amount that is generated by the actual light irradiation, and thus there is distortion of the captured image.

At least one embodiment of the present disclosure provides a pixel sensing circuit and a driving method therefor, and also provides an image sensor with the pixel sensing circuit. By a redesigned circuit, the pixel sensing circuit eliminates the problem that output currents are not uniform due to the source followers' variations.

An embodiment of the present disclosure provides a pixel sensing circuit, comprising: a photoelectric conversion element configured to generate electric charges in response to incident light; a transmission element configured to output the electric charges generated by the photoelectric conversion element; and a source follower circuit configured to compensate an output current of the transmission element. The source follower circuit comprises a first source follower transistor, a second source follower transistor and a first storage capacitor, the first source follower transistor and the second source follower transistor have threshold voltages equal to each other, a gate electrode of the first source follower transistor, an output terminal of the first source follower transistor, a gate electrode of the second source follower transistor, and a first end of the first storage capacitor are all coupled to a first node, and a second end of the first storage capacitor and an input terminal of the second source follower transistor are coupled to a supply voltage line.

Another embodiment of the present disclosure provides a driving method for the pixel sensing circuit described above, comprising: generating electric charges in response to incident light by the photoelectric conversion element; outputting the electric charges generated by the photoelectric conversion element to the source follower circuit by the transmission element; and compensating the output current of the transmission element by the source follower circuit.

As known by those skilled in the art, the transistors may be N-type transistors or P-type transistors. In the embodiments of the present disclosure, for N-type transistors, the (current) input terminal is a drain electrode and the output terminal is a source electrode; for P-type transistors, the (current) input terminal is a source electrode and the output terminal is a drain electrode.

In the following description of the present disclosure, P-type transistors (for example, P-type MOS transistors) are described as an example. However, those skilled in the art should know that any one of them may be implemented using an N-type transistor (for example, an N-type MOS transistor).

FIG. 4 is a schematic diagram of a pixel sensing circuit provided by an embodiment of the present disclosure. As shown in FIG. 4 , the pixel sensing circuit is an active pixel sensing circuit 400 , comprising: a photodiode PD, a transmission transistor T 3 , and a source follower circuit. The photodiode PD serves as a photoelectric conversion element which generates electric charges in response to incident light; the transmission transistor T 3 serves as a transmission element which outputs the electric charges generated by the photodiode; and the source follower circuit is configured to compensate an output current of the transmission transistor T 3 .

The source follower circuit comprises a first source follower transistor M 1 , a second source follower transistor M 2 and a first storage capacitor C 1 . The first source follower transistor M 1 and the second source follower transistor M 2 have threshold voltages (Vth) equal to each other, a gate electrode of the first source follower transistor M 1 , a drain electrode of the first source follower transistor M 1 , a gate electrode of the second source follower transistor M 2 , and a first end of the first storage capacitor C 1 are all coupled to a first node a, and a second end of the first storage capacitor C 1 and a source electrode of the second source follower transistor M 2 are coupled to a supply voltage line Vdd.

The transmission transistor T 3 is disposed between the photodiode PD and the source follower circuit. As shown in the figure, the anode of the photodiode PD is connected to, for example, ground or a common voltage, and the cathode of the photodiode is connected to a source electrode of the transmission transistor T 3 . A drain electrode of the transmission transistor T 3 is coupled to a source electrode of the first source follower transistor M 1 , and a gate electrode of the transmission transistor T 3 is coupled to a second scan line Scan 2 .

The active pixel sensing circuit may further comprise a readout element. For example, the readout element is configured to transmit an output current of the source follower circuit to an external circuit in response to a selection signal, and an output terminal of the second source follower transistor is coupled to an input terminal of the readout element.

Specifically, as shown in FIG. 4 , the active pixel sensing circuit comprises a readout transistor T 5 serving as a readout element and coupled between a drain electrode of the second source follower transistor M 2 and a readout line RL (e.g., a column line), and a gate electrode of the readout transistor T 5 is connected to a selection signal line EM (e.g., a row line).

The first source follower transistor M 1 and the second source follower transistor M 2 have threshold voltages (Vth) equal to each other, but the values of the threshold voltages not required to be exactly equal. For example, they may be substantially equal. For example, the difference between them is within 5%, preferably within 3%. Factors that affect the threshold voltage of a transistor comprise the material and the thickness of a gate insulating layer, the material and the doping content of an active layer, the operating temperature and so on. In order for the first source follower transistor M 1 and the second source follower transistor M 2 to have threshold voltages (Vth) equal to each other, the first source follower transistor M 1 and the second source follower transistor M 2 may be of the same type, and for example, when preparing the first source follower transistor M 1 and the second source follower transistor M 2 , both of them are prepared as close as possible and the same preparation parameters (comprising the thickness of a gate insulating layer, the thickness of an active layer, the breadth length ratio (W/L) of a channel region, and so on) are adopted, but the embodiments of the present disclosure are not limited thereto. In the schematic diagram of FIG. 4 , the first source follower transistor M 1 and the second source follower transistor M 2 are oppositely disposed, and the threshold voltages of both are equal to each other, so they can be regarded disposed in a symmetrical arrangement (or a mirror arrangement).

As described above, in the embodiment as illustrated in FIG. 4 , the transmission transistor T 3 , the first source follower transistor M 1 , the second source follower transistor M 2 , and the readout transistor T 5 are all P-type transistors. The photodiode PD serves as an example of the photoelectric conversion element, but the embodiments of the present disclosure are not limited thereto.

The driving method for the active pixel sensing circuit 400 according to the embodiment as shown in FIG. 4 may comprise a photoelectric conversion phase, an electric discharging phase, and a signal readout phase.

First of all, during the photoelectric conversion phase, when incident light is irradiated onto the photodiode PD, light quantum excites at the PN junction of the photodiode to generate electron-hole pairs, thereby the photodiode PD performs photoelectric conversion in response to the incident light to generate electric charges that accumulate on the photodiode PD, and a data voltage Vdata is generated.

Next, during the electric discharging phase, the electric charges generated by the photodiode are output to the source follower circuit by the transmission transistor T 3 . Specifically, a low level signal is applied to the second scan line Scan 2 , the transmission transistor T 3 turns on, and the first source follower transistor M 1 also turns on. Thereby the first node a is charged through the first source follower transistor M 1 until a voltage of V data −V tH1 . V data is the data voltage generated by the photodiode PD, and V th1 is the threshold voltage of the first source follower transistor M 1 , and this voltage is stored in the first storage capacitor C 1 .

Then, during the signal readout phase, the output current of the transmission transistor is compensated by the source follower circuit and then the output current of the source follower circuit is transmitted to the external circuit by the readout transistor T 5 in response to the selection signal EM. Specifically, a low level signal is applied to the selection signal line EM, the readout transistor T 5 turns on, the source electrode of the second source follower transistor M 2 is connected to the supply voltage Vdd, and an electrical current Iout flows out through the second source follower transistor M 2 and the readout transistor T 5 and is then transmitted to the external circuit for further processing such as amplification, analog/digital conversion, and so on.

Based on the saturation current formula of a transistor, the current flowing through the second source follower transistor M 2 is:

V GS in the above formula is a voltage difference between the gate electrode and the source electrode of the transistor M 2 , V dd is the supply voltage, V th2 is the threshold voltage of the second source follower transistor M 2 , and the threshold voltage V th1 is equal to V th2 , i.e., V th1 =V th2 . In addition, V GS =V dd −(V data −V th1 ).

It can be seen from the above formula that in this case the output current Iout is not affected any more by the threshold voltage Vth 1 or Vth 2 of the source follower transistor M 1 or M 2 , and is only related to the supply voltage Vdd and the data voltage Vdata. The data voltage Vdata is directly generated by the PN junction of the photodiode PD due to the illumination of the incident light. This solves the problem that the threshold voltage (Vth) of the source follower transistor drifts due to the manufacturing process and long-term operation, so as to ensure the accuracy of signal data.

Based on the embodiment shown in FIG. 4 , other embodiments can be obtained by incorporating other circuits. For example, the active pixel sensing circuit shown in FIG. 4 may further comprise a first reset element configured to reset a voltage at an output node (for example, this output node may correspond to the node between an input terminal of the transmission transistor T 3 and the cathode of the photodiode PD in FIG. 4 ) of the photodiode. The output node is coupled to the input terminal of the transmission transistor, and the first reset element may be a reset transistor.

Alternatively, for example, the active pixel sensing circuit shown in FIG. 4 may further comprise a second reset element configured to reset a voltage of the first node a, and the second reset element may also be a reset transistor. The first reset element and the second reset element described above do not necessarily have to be incorporated simultaneously.

Alternatively, for example, the active pixel sensing circuit shown in FIG. 4 may further comprise a switching element and a second storage capacitor. The switching element is coupled between the output node and the photodiode, a first end of the second storage capacitor is coupled to the output node, and a second end of the second storage capacitor is coupled to ground or a common voltage. Thereby, the voltage generated by the photodiode can be selectively buffered.

FIG. 5 is a schematic diagram of a pixel sensing circuit provided by another embodiment of the present disclosure. As shown in FIG. 5 , compared with the embodiment shown in FIG. 4 , the pixel sensing circuit is an active pixel sensing circuit 500 , which further comprises a switching transistor T 1 , a first reset transistor T 2 , a second storage capacitor C 2 , and a second reset transistor T 4 , in addition to the photodiode PD, the transmission transistor T 3 , the source follower circuit, and the output transistor T 5 .

The first reset transistor T 2 serves as a first reset element configured to reset the voltage of an output node N 2 of the photodiode. The output node N 2 is coupled to the input terminal of the transmission element, i.e., the source electrode of the transmission transistor T 3 . As illustrated in FIG. 5 , a control terminal of the first reset transistor T 2 is connected to a reset line Reset, a terminal of this transistor is coupled to the output node N 2 , and another terminal thereof is coupled to a common voltage Vcom.

The switching transistor T 1 serves as a switching element configured to control whether or not to output the data voltage generated by the photodiode PD in response to the incident light. The switching transistor T 1 is coupled between the output node N 2 and the photodiode PD. As shown in FIG. 5 , a gate electrode of the switch transistor T 1 is connected to a first scan line Scan 1 , a source electrode of the switch transistor T 1 is coupled to the cathode of the photodiode PD, and a drain electrode of the switch transistor T 1 is coupled to the output node N 2 .

A first end of the second storage capacitor C 2 is coupled to the output node N 2 , and a second end of the second storage capacitor C 2 is coupled to ground or a common voltage. The second storage capacitor C 2 may be configured to store the voltage of the output node N 2 .

The second reset transistor T 4 serves as a second reset element configured to reset the voltage of the first node a. As shown in FIG. 5 , a control terminal of the second reset transistor T 4 is connected to the reset line Reset, a terminal of this transistor is coupled to the first node a, and another terminal is coupled to an initial voltage Vint. The first reset transistor T 2 and the second reset transistor T 4 may be coupled to the same reset line Reset, or may be connected to different reset lines Reset and both are applied with reset signals in synchronization.

As shown in FIG. 5 , the switching transistor T 1 , the first reset transistor T 2 , the second storage capacitor C 2 , and the second reset transistor T 4 may be P-type transistors (for example, P-type MOS transistors); similarly, those skilled in the art would know that any one of them may be an N-type transistor (for example, an N-type MOS transistor).

The right side of FIG. 5 shows the timing diagrams of the reset signal Reset, the selection signal EM, the first scan signal Scan 1 , and the second scan signal Scan 2 . The driving method for the active pixel sensing circuit according to the embodiment as shown in FIG. 5 is described below in connection with the timing diagram and FIGS. 6A-6D . The driving method for the active pixel sensing circuit according to the embodiment as shown in FIG. 5 may comprise a reset phase, a photoelectric conversion phase, an electric discharging phase, and a signal readout phase.

First of all, during the reset phase, as shown in the timing diagrams on the right side of FIG. 6A , the reset signal Reset changes to a low level, and the selection signal EM, the first scan signal Scan 1 and the second scan signal Scan 2 are kept at high levels, corresponding to the shaded portion of the timing diagram. At this time, the first reset transistor T 2 and the second reset transistor T 4 turn on and respectively reset the voltages of the output node N 2 and the first node a to the common voltage Vcom and the initial voltage Vint, while the other transistors T 1 , T 3 , and T 5 are in turning-off states. The initial voltage Vint is a low voltage signal, so that the first source follower transistor M 1 and the second source follower transistor M 2 are in turning-on states. However, because the readout transistor T 5 is in a turning-off state, there is no signal readout that occurs.

Secondly, during the photoelectric conversion phase, as shown in the timing diagrams on the right side of FIG. 6B , when incident light is irradiated onto the photodiode PD, light quantum excites at the PN junction of the photodiode to generate electron-hole pairs, thereby the photodiode PD performs photoelectric conversion in response to the incident light to generate electric charges that accumulate on the photodiode PD to generate a voltage. At this time, the reset signal Reset changes to a high level, and the selection signal EM and the second scan signal Scan 2 are kept at high levels, while the first scan signal Scan 1 changes to a low level. Thereby the switching transistor T 1 turns on while the other transistors T 2 , T 3 , T 4 , and T 5 are in turning-off states. Thus, the electric potential of the output node N 2 is the data voltage Vdata and is stored in the second storage capacitor C 2 .

Next, during the electric discharging phase, the electric charges generated by the photodiode are output to the source follower circuit by the transmission transistor T 3 . Specifically, as shown in the timing diagrams on the right side of FIG. 6C , the second scan signal Scan 2 changes to a low level, while the reset signal Reset, the selection signal EM, and the first scan signal Scan 1 change to high levels. The transmission transistor T 3 turns on, and the first source follower transistor M 1 also turns on, while the other transistors T 1 , T 2 , T 4 , and T 5 are in turning-off states. Thereby the first node a is charged through the first source follower transistor M 1 until the voltage of V data −V th1 . V th1 is the threshold voltage of the first source follower transistor M 1 , and this voltage is stored in the first storage capacitor C 1 . At this time, the second source follower transistor M 2 also turns on. However, because the readout transistor T 5 is in the off state, there is no signal readout that occurs.

Then, during the signal readout phase, the output current of the transmission transistor is compensated by the source follower circuit and then the output current of the source follower circuit is transmitted to the external circuit by the readout transistor T 5 in response to the selection signal EM. Specifically, as shown in the timing diagrams on the right side of FIG. 6D , the selection signal EM changes to a low level, while the reset signal Reset, the first scan signal Scan 1 , and the second scan signal Scan 2 are at high levels. Thereby the readout transistor T 5 turns on while the other transistors T 1 , T 2 , T 3 , and T 4 are in the turning-off states. When the source electrode of the second source follower transistor M 2 is connected to the supply voltage and the second source follower transistor M 2 maintains the turning-on state under a control of the voltage of the first node a, the current Iout flows out through the second source follower transistor M 2 and the readout transistor T 5 and is then transmitted to the external circuit for further processing such as amplification, analog/digital conversion, and so on.

Based on the saturation current formula of the transistor, the current flowing through the second source follower transistor M 2 is:

V GS in the above formula is a voltage difference between the gate electrode and the source electrode of the transistor M 2 , V dd is the supply voltage, V th2 is the threshold voltage of the second source follower transistor M 2 , and the threshold voltage V th1 is equal to V th2, i.e., V th1 =V th2 . In addition, V GS =V dd −(V data −V th1 ).

It can be seen from the above formula that in this case the output current Iout here is not affected any more by the threshold voltage Vth 1 or Vth 2 of the source follower transistor M 1 or M 2 , and is only related to the supply voltage Vdd and the data voltage Vdata. The data voltage Vdata is directly generated by the PN junction of the photodiode PD due to the illumination of the incident light. This solves the problem that the threshold voltage (Vth) of the source follower transistor drifts due to the manufacturing process and long-time operation, so as to ensure the accuracy of the signal data.

FIG. 7 is a schematic diagram of a pixel sensing circuit provided by another embodiment of the present disclosure, and shows a circuit diagram illustrating an active pixel sensing circuit with a shared structure.

Referring to FIG. 7 , the pixel sensing circuit is an active pixel sensing circuit 700 with a shared structure, which can increase a pixel occupancy ratio of the pixel unit array. The pixel occupancy ratio may be defined here as a ratio of the area occupied by the photodiodes to the area occupied by other transistors such as the reset transistors, the source follower transistors, and so on.

Compared with the embodiment shown in FIG. 5 , in the active pixel sensing circuit 700 with a shared structure, for example, four sets of combinations of a photodiode and a switching transistor are commonly coupled to the output node N 2 and share the first reset transistor T 2 , the second storage capacitor C 2 , the transmission transistor T 3 , the source follower circuit (comprising the first source follower transistor M 1 , the second source follower transistor M 2 and the first storage capacitor C 1 ), and the readout transistor T 5 . The four sets of combinations of a photodiode and a switching transistor belong to four pixel units. A first pixel unit comprises a photodiode PD 1 and a switching transistor T 11 , the switching transistor T 11 being connected to a scan line Scan 11 ; a second pixel unit comprises a photodiode PD 2 and a switching transistor T 12 , the switching transistor T 12 being connected to a scan line Scan 12 ; a third pixel unit comprises a photodiode PD 3 and a switching transistor T 13 , the switching transistor T 13 being connected to a scan line Scan 13 ; and a fourth pixel unit comprises a photodiode PD 4 and a switching transistor T 14 , the switching transistor T 14 being connected to a scan line Scan 14 .

For example, the first to the fourth sub-pixels may be sequentially scanned in four adjacent scan periods to read out electric charges generated by the photodiodes therein in response to incident light. Each of the four scan periods comprises a reset phase, a photoelectric conversion phase, an electric discharging phase, and a signal readout phase. The difference is that low level signals are respectively applied to the scan lines Scan 11 , Scan 12 , Scan 13 , and Scan 14 to respectively read out voltages generated by the photodiodes PD 1 , PD 2 , PD 3 , and PD 4 .

Those skilled in the art can understand that the embodiments of the present disclosure are not limited to the four sets of combinations of a photodiode and a switching transistor as shown in FIG. 7 , and two or more sets of combinations of a photodiode and a switching transistor may be acceptable.

An embodiment of the present disclosure also provides an image sensor, comprising a plurality of pixel units arranged in an array, and at least one pixel unit comprising any one of the pixel sensing circuits provided by an embodiment of the present disclosure. The image sensor, for example, comprises a pixel unit array of X rows and Y columns, and X row lines (selection signal lines Em) and Y column lines (readout lines RL) are prepared accordingly.

In addition to the pixel unit array, the image sensor may further comprise peripheral circuits such as a row driving circuit, a column driving circuit, an amplifying circuit, a pre-processing circuit, and so on. The pixel unit array and the peripheral circuits, for example, may be prepared on a silicon substrate by semiconductor integrated circuit manufacturing processes (e.g., CMOS integrated circuit manufacturing processes), and the silicon substrate, for example, may be a monocrystalline silicon substrate or a silicon on insulator (SOI) substrate etc.

An embodiment of the present disclosure also provides an electronic device, comprising the above image sensor provided by an embodiment of the present disclosure. The electronic device may be a digital camera, a mobile phone, a tablet computer, a laptop, or the like.

What are described above is related to the illustrative embodiments of the disclosure only and not limitative to the scope of the disclosure; the scopes of the disclosure are defined by the accompanying claims.

The application claims priority to the Chinese patent application No. 201610985469.4, filed Nov. 9, 2016, the entire disclosure of which is incorporated herein by reference as part of the present application.