Pixel circuit, a driving method thereof and a display apparatus

This application is a Section 371 National Stage Application of International Application No. PCT/CN2017/097589, which claims the benefit of Chinese Patent Application No. 201710034618.3, filed on Jan. 18, 2017, the entire contents of which are incorporated herein by reference.

Embodiment of the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a driving method thereof, and a display device.

A CMOS (Complementary Metal-Oxide Semiconductor) image sensor may receive an external light, convert the light into an electrical signal, and output the electrical signal. As being a detection circuit of a CMOS image sensor, an Active Pixel Sensor (APS) circuit has a non-uniform outputting current during a photoelectric conversion process of a photosensitive device, since the process of the source follower thin film transistors (TFT) may have a difference. Thus, the outputting current of the source follower TFT will be affected by its own threshold voltage, causing a display distortion.

Embodiments of the present disclosure provide a pixel circuit, a driving method thereof and a display apparatus.

According to an aspect of the embodiments of the disclosure, there is provided a pixel circuit comprising a resetting sub-circuit, a charging sub-circuit, a compensating sub-circuit and an outputting sub-circuit, wherein:

the resetting sub-circuit is connected to a first signal terminal, a first voltage terminal, a second signal terminal, a first node and a second node respectively, and configured to control potentials of the first node and the second node according to inputting signals of the first signal terminal and the second signal terminal;

the charging sub-circuit is connected to a third signal terminal and the second node, and configured to control a potential of the second node according to an inputting signal of the third signal terminal;

the compensating sub-circuit is connected to the second node, the first node, the first voltage terminal, a fourth signal terminal, a third node, the second voltage terminal and a fifth signal terminal, and configured to control the potentials of the first node and the third node according to inputting signals of the fourth signal terminal and the fifth signal terminal and the potential of the second node; and

the outputting sub-circuit is connected to a first terminal of a light emitting device which has its second terminal connected to a ground, wherein the outputting sub-circuit is connected to the third node, a sixth signal terminal, a reading terminal and a seventh signal terminal, and configured to control a signal outputted to the first terminal of the light emitting device and an outputting signal of the reading terminal according to the inputting signal of the sixth signal terminal and the seventh signal terminal and the potential of the third node.

For example, the outputting sub-circuit comprises:

a reading circuit, connected to the third node, the reading terminal and the sixth signal terminal, and configured to control the outputting signal of the reading terminal according to the input signal of the sixth signal terminal and the potential of the third node; and

a light emitting circuit, connected to the third node, the seventh signal terminal and a first terminal of the light emitting device, and configured to control a signal outputted to the first terminal of the light emitting device according to the input signal of the seventh signal terminal and the potential of the third node.

For example, the resetting sub-circuit comprises a first transistor and a second transistor;

the first transistor has a gate connected to the first signal terminal, a first electrode connected to the first voltage terminal and a second electrode connected to the second node; and

the second transistor has a gate connected to the second signal terminal, a first electrode connected to the ground and a second electrode connected to the first node.

For example, the charging sub-circuit comprises a third transistor and a first capacitor, wherein:

the third transistor has a first electrode connected to a second electrode of a photosensitive device whose first electrode is connected to a ground, a gate connected to the third signal terminal, and a second electrode connected to the second node; and

the first capacitor has a first terminal connected to the ground and a second terminal connected to the second node.

For example, the compensating sub-circuit comprises a fourth transistor, a fifth transistor, a sixth transistor and a second capacitor, wherein:

the fourth transistor has a gate connected to the fifth signal terminal, a first electrode connected to the second node and a second electrode connected to the second voltage terminal;

the fifth transistor has a gate connected to the first node, a first electrode connected to the second node and a second electrode connected to the third node;

the sixth transistor has a gate connected to the fourth signal terminal, a first electrode connected to the first node and a second electrode connected to the third node; and

the second capacitor has a first terminal connected to the first node and a second terminal connected to the first voltage terminal.

For example, the reading circuit comprises a seventh transistor, wherein the seventh transistor has a gate connected to the sixth signal terminal, a first electrode connected to the third node and a second electrode connected to the reading terminal.

For example, the reading circuit comprises an eighth transistor, wherein the eighth transistor has a gate connected to the seventh signal terminal, a first electrode connected to the third node and a second electrode connected to the first terminal of the light emitting device.

For example, the transistors are an N-type transistor or a P-type transistor.

For example, the photosensitive device comprises a photodiode.

According to another aspect of the embodiments of the present disclosure, there is provided a display apparatus comprising the pixel circuit according to the embodiments of the present disclosure.

According to another aspect of the embodiments of the present disclosure, there is provided a method of driving a pixel circuit, comprising the pixel circuit according to the embodiments of the present disclosure, wherein the first voltage terminal is applied to a voltage at a first level, and the second voltage terminal is applied to a data signal voltage;

the method of driving the pixel circuit comprises:

applying, a second level to the first signal terminal, the second level to the second signal terminal, the second level to the third signal terminal, the first level to the fourth signal terminal, the first level to the fifth signal terminal, the first level to the sixth signal terminal and the first level to the seventh signal terminal, during a first period;

applying, the first level to the first signal terminal, the first level to the second signal terminal, the second level to the third signal terminal, the first level to the fourth signal terminal, the first level to the fifth signal terminal, the first level to the sixth signal terminal and the first level to the seventh signal terminal, during a second period;

applying, the first level to the first signal terminal, the first level to the second signal terminal, the first level to the third signal terminal, the second level to the fourth signal terminal, the first level to the fifth signal terminal, the first level to the sixth signal terminal and the first level to the seventh signal terminal, during a third period; and

applying, the second level to the first signal terminal, the first level to the second signal terminal, the first level to the third signal terminal, the first level to the fourth signal terminal, the first level to the fifth signal terminal, the second level to the sixth signal terminal and the first level to the seventh signal terminal, during a fourth period.

For example, the method further comprises:

applying, a first level to the first signal terminal, the second level to the second signal terminal, the first level to the third signal terminal, the first level to the fourth signal terminal, the first level to the fifth signal terminal, the first level to the sixth signal terminal and the first level to the seventh signal terminal, during a fifth period;

applying, the first level to the first signal terminal, the first level to the second signal terminal, the first level to the third signal terminal, the second level to the fourth signal terminal, the second level to the fifth signal terminal, the first level to the sixth signal terminal and the first level to the seventh signal terminal, during a sixth period; and

applying, the second level to the first signal terminal, the first level to the second signal terminal, the first level to the third signal terminal, the first level to the fourth signal terminal, the first level to the fifth signal terminal, a high level to the sixth signal terminal and the second level to the seventh signal terminal, during a seventh period.

FIG. 1 shows a schematic structural diagram illustrating a pixel circuit according to an embodiment of the present disclosure;

FIG. 2 shows a schematic structural diagram illustrating another pixel circuit according to an embodiment of the present disclosure;

FIG. 3 shows detailed structural diagram illustrating the pixel circuit shown in FIG. 2 ;

FIG. 4 shows a flowchart illustrating a driving method for a pixel circuit according to an embodiment of the present disclosure;

FIG. 5 shows an operation timing diagram of the pixel circuit according to an embodiment of the present disclosure;

FIG. 6 shows a schematic diagram of the current flow of the pixel circuit during the first period according to the driving method of FIG. 4 ;

FIG. 7 shows a schematic diagram of the current flow of the pixel circuit during the second period according to the driving method of FIG. 4 ;

FIG. 8 shows a schematic diagram of the current flow of the pixel circuit during the third period according to the driving method of FIG. 4 ;

FIG. 9 shows a schematic diagram of the current flow of the pixel circuit during the fourth period according to the driving method of FIG. 4 ;

FIG. 10 shows a schematic diagram of the current flow of the pixel circuit during the fifth period according to the driving method of FIG. 4 ;

FIG. 11 shows a schematic diagram of the current flow of the pixel circuit during the sixth period according to the driving method of FIG. 4 ; and

FIG. 12 shows a schematic diagram of the current flow of the pixel circuit during the seventh period according to the driving method of FIG. 4 .

In order to make a better understanding of technical solutions in embodiments of the present disclosure for those skilled in the art, a pixel circuit, a driving method thereof and a display apparatus according to the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

FIG. 1 shows a schematic structural diagram illustrating a pixel circuit according to an embodiment of the present disclosure. As shown in FIG. 1 , the pixel circuit may comprise a resetting sub-circuit 101 , a charging sub-circuit 102 , a compensating sub-circuit 103 and an outputting sub-circuit 104 .

In one embodiment, the pixel circuit is connected to a light emitting device OLED which has its first terminal connected to the outputting sub-circuit 104 and its second terminal connected to a ground.

In one embodiment, the pixel circuit is connected to a photosensitive device PD which has its first terminal connected to the ground and its second terminal connected to the charging sub-circuit 102 .

In one embodiment, the photosensitive device PD comprises a photodiode, and the light emitting device OLED is an organic electroluminescent device.

Referring to FIG. 1 , in the pixel sub-circuit according to the embodiment of the disclosure, the resetting sub-circuit 101 is connected to a first signal terminal Reset, a first voltage terminal Vdd, a second signal terminal Reset 1 , a first node N 1 and a second node N 2 , and configured to control potentials of the first node N 1 and the second node N 2 according to inputting signals of the first signal terminal Reset and the second signal terminal Reset 1 . The charging sub-circuit 102 is connected to the third signal terminal Scan 1 and the second node N 2 , and configured to control a potential of the second node N 2 according to an inputting signal of the third signal terminal Scan 1 . The compensating sub-circuit 103 may be connected to the second node N 2 , the first node N 1 , the first voltage terminal Vdd, a fourth signal terminal Scan 2 , the third node N 3 , a second voltage terminal Vdata and a fifth signal terminal Scan 3 , and configured to control the potentials of the first node N 1 and the third node N 3 according to inputting signals of the fourth signal terminal Scan 2 and the fifth signal terminal Scan 3 and the potential of the second node N 2 . The outputting sub-circuit 104 may be connected to the third node N 3 , the sixth signal terminal EM 1 , a reading terminal ReadLine and a seventh signal terminal EM 2 , and configured to control a signal outputted to the first terminal of the light emitting device OLED and an outputting terminal of the reading terminal ReadLine according to the inputting signal of the sixth signal terminal EM 1 and the seventh signal terminal EM 2 and the potential of the third node N 3 .

FIG. 2 shows a schematic structural diagram illustrating another pixel circuit according to an embodiment of the present disclosure. As shown in FIG. 2 , the outputting sub-circuit 104 comprises a reading circuit 201 and a light emitting circuit 202 . The reading circuit 201 is connected to the third node N 3 , the reading terminal ReadLine and the sixth signal terminal EM 1 , and configured to control the outputting signal of the reading terminal ReadLine according to the input signal of the sixth signal terminal EM 1 and the potential of the third node N 3 . The light emitting circuit 202 is connected to the third node N 3 , the seventh signal terminal EM 2 and a first terminal of the light emitting device OLED, and configured to control a signal outputted from the first terminal of the light emitting device OLED according to the input signal of the seventh signal terminal EM 2 and the potential of the third node N 3 .

FIG. 3 shows detailed structural diagram illustrating the pixel circuit shown in FIG. 2 . As shown in FIG. 3 , the resetting sub-circuit 101 comprises a first transistor M 1 and a second transistor M 2 . The first transistor M 1 has a gate connected to the first signal terminal Reset, a first electrode connected to the first voltage terminal Vdd and a second electrode connected to the second node N 2 . The second transistor M 2 has a gate connected to the second signal terminal Reset 1 , a first electrode connected to the ground and a second electrode connected to the first node N 1 .

Referring to FIG. 3 , the charging sub-circuit 102 comprises a third transistor M 3 and a first capacitor C 1 . The third transistor M 3 has a gate connected to the third signal terminal, a first electrode connected to a second electrode of a photosensitive device PD and a second electrode connected to the second node N 2 . The first capacitor C 1 has a first terminal connected to the ground and a second terminal connected to the second node N 2 .

Referring to FIG. 3 , the compensating sub-circuit 103 comprises a fourth transistor M 4 , a fifth transistor M 5 , a sixth transistor M 6 and a second capacitor C 2 . The fourth transistor M 4 has a gate connected to the fifth signal terminal Scan 3 , a first electrode connected to the second node N 2 and a second electrode connected to the second voltage terminal Vdata. The fifth transistor M 5 has a gate connected to the first node N 1 , a first electrode connected to the second node N 2 and a second electrode connected to the third node N 3 . The sixth transistor M 6 has a gate connected to the fourth signal terminal Scan 2 , a first electrode connected to the first node N 1 and a second electrode connected to the third node N 3 . The second capacitor C 2 has a first terminal connected to the first node N 1 and a second terminal connected to the first voltage terminal Vdd.

Referring to FIG. 3 , the reading circuit comprises a seventh transistor M 7 . The seventh transistor M 7 has a gate connected to the sixth signal terminal EM 1 , a first electrode connected to the third node N 3 and a second electrode connected to the reading terminal ReadLine. The light emitting circuit comprises an eighth transistor M 8 . The eighth transistor M 8 has a gate connected to the seventh signal terminal EM 2 , a first electrode connected to the third node N 3 and a second electrode connected to the first terminal of the light emitting device OLED.

According to the embodiment of the present disclosure, the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the sixth transistor M 6 , the seventh transistor M 7 and the eighth transistor M 8 are switching transistors (switching TFT). The fifth transistor M 5 is a source follower driving transistor (driving TFT). The switching transistor, the driving transistor and the source follower driving transistor used in the embodiments of the present disclosure may be thin film transistors, such as oxide semiconductor transistors. Since the source and the drain of the thin film transistor used herein are symmetrical, the source and the drain of the thin film transistor can be exchanged. In an embodiment of the present disclosure, one of the source and the drain is referred to as the first electrode, and the other is referred to as the second electrode. For the convenience of description, all of the thin film transistors in the following examples are P-type thin film transistors whose gate-on voltage is at a low level. It should be understood for those skilled in the art that the thin film transistor may also be an N-type thin film transistor, and in this case, the polarity of the gate controlling signal should be changed accordingly.

By sharing the driving signal and the scanning signal, the pixel circuit according to the embodiments of the present disclosure can not only realize the high-resolution silicon-based display function but also have the environment image monitoring function. In addition, the solution according to the embodiment compensates for the source follower transistor of the pixel circuit to avoid a non-uniform outputting current caused by the difference of the source follower transistors itself, so that the outputting current is independent from the threshold voltage of the source follower transistor.

According to another aspect of embodiments of the present disclosure, there is provided a display apparatus including the pixel circuit according to the embodiment of the present disclosure.

In the display apparatus according to the embodiment of the present disclosure, the pixel circuit may include a resetting sub-circuit, a charging sub-circuit, a compensating sub-circuit, an outputting sub-circuit and a light emitting device. The resetting sub-circuit is configured to control potentials of the first node and the second node according to inputting signals of the first signal terminal and the second signal terminal. The charging sub-circuit is configured to control a potential of the second node according to an inputting signal of the third signal terminal. The compensating sub-circuit is configured to control the potentials of the first node and the third node according to inputting signals of the fourth signal terminal and the fifth signal terminal and the potential of the second node. The outputting sub-circuit is configured to control a signal outputted to the first terminal of the light emitting device and an outputting signal of the reading terminal according to the inputting signal of the sixth signal terminal and the seventh signal terminal and the potential of the third node.

FIG. 4 shows a flowchart illustrating a driving method for a pixel circuit according to an embodiment of the present disclosure. FIG. 5 shows an operation timing diagram of the pixel circuit according to an embodiment of the present disclosure. In an example of FIGS. 4 and 5 , the first voltage terminal Vdd is applied to a high level, and the second voltage terminal Vdata is applied to a data signal voltage.

In the following example, all of the transistors M 1 to M 8 are P-type transistors with a gate-on voltage of a low level. It should be understood by those skilled in the art that the transistors may also be an N-type transistors, in which case the gate-on voltage is at a high level.

The driving method of the pixel circuit may include following steps.

At step 1001 , during the first period t 1 , the input signal of the first signal terminal is at a low level, the input signal of the second signal terminal is at a low level, the input signal of the third signal terminal is at a low level, the input signal of the fourth signal terminal is at a high level, the input signal of the fifth signal terminal is at a high level, the input signal of the sixth signal terminal is at a high level and the input signal of the seventh signal terminal is at a high level.

FIG. 6 shows a schematic diagram of the current flow of the pixel circuit during the first period t 1 according to the embodiment of FIG. 4 . As shown in FIG. 6 , the direction of the arrow in the figure represents the current flow. During the first period t 1 , the inputting signal of the first signal terminal Reset is at a low level, the inputting signal of the second signal terminal Reset 1 is at a low level, the inputting signal of the third signal terminal Scan 1 is at a low level, the inputting signal of the fourth signal terminal Scan 2 is at a high level, the inputting signal of the fifth signal terminal Scan 3 is at a high level, the inputting signal of the sixth signal terminal EM 1 is at a high level and the inputting signal of the seventh signal terminal EM 2 is at a high level. At this time, the first transistor M 1 , the second transistor M 2 and the third transistor M 3 are turned on, and the other transistors are turned off. In this case, the potential of the first node N 1 is reset to Vint, for example, 0V. Certainly, the potential of the first node N 1 could also be reset to a negative voltage, so that the fifth transistor M 5 is turned on and the potential of the second node N 2 is Vdd. Meanwhile, the voltage signals will be reset.

At step 1002 , during the second period t 2 , the inputting signal of the first signal terminal is at a high level, the inputting signal of the second signal terminal is at a high level, the inputting signal of the third signal terminal is at a low level, the inputting signal of the fourth signal terminal is at a high level, the inputting signal of the fifth signal terminal is at a high level, the inputting signal of the sixth signal terminal is at a high level, and the inputting signal of the seventh signal terminal is at a high level.

FIG. 7 shows a schematic diagram of the current flow of the pixel circuit during the second period t 2 according to the embodiment of FIG. 4 . As shown in FIG. 6 , an arrow on the photosensitive device PD indicates for a photoelectrical reaction. During the second period t 2 , the inputting signal of the first signal terminal Reset is at a high level, the inputting signal of the second signal terminal Reset 1 is at a high level, the inputting signal of the third signal terminal Scan 1 is at a low level, the inputting signal of the fourth signal terminal Scan 2 is at a high level, the inputting signal of the fifth signal terminal Scan 3 is at a high level, the inputting signal of the sixth signal terminal EM 1 is at a high level, and the inputting signal of the seventh signal terminal EM 2 is at a high level. At this time, only the third transistor M 3 is turned on and the other transistors are turned off. When a light is incident on a PN junction of the photosensitive device PD, the photon quantum excitation generates an electron-hole pair on the PN junction, so that the charge on a capacitor of the PN junction is recombined, thereby reducing the potential of the second node N 2 to Vdata 1 which is then stored at both ends of the first capacitor C 1 , so as to be ready for a compensating period.

At step 1003 , during the third period t 3 , the inputting signal of the first signal terminal is at a high level, the inputting signal of the second signal terminal is at a high level, the inputting signal of the third signal terminal is at a high level, the inputting signal of the fourth signal terminal is at a low level, the inputting signal of the fifth signal terminal is at a high level, the inputting signal of the sixth signal terminal is at a high level, and the inputting signal of the seventh signal terminal is at a high level.

FIG. 8 shows a schematic diagram of the current flow of the pixel circuit during the third period t 3 according to the embodiment of FIG. 4 . As shown in FIG. 8 , the direction of the arrow in the figure represents the current flow. During the third period t 3 , the inputting signal of the first signal terminal Reset is at a high level, the inputting signal of the second signal terminal Reset 1 is at a high level, the inputting signal of the third signal terminal Scan 1 is at a high level, the inputting signal of the fourth signal terminal Scan 2 is at a low level, the inputting signal of the fifth signal terminal Scan 3 is at a high level, the inputting signal of the sixth signal terminal EM 1 is at a high level, and the inputting signal of the seventh signal terminal EM 2 is at a high level. At this time, the sixth transistor M 6 and the fifth transistor M 5 are turned on, while the other transistors are turned off. Since the potential of the first node N 1 is 0V previously, the fifth transistor M 5 is turned on, and the signal of Vdata 1 starts charging the first node N 1 via the fifth transistor M 5 and the sixth transistor M 6 , until the first node N 1 is charged to Vdata 1 −Vth. At this time, the voltage difference between the gate and the source of the fifth transistor M 5 is Vth. After the charging is completed, the potential of the first node N 1 will always be maintained at Vdata 1 −Vth.

At step 1004 , during the fourth period t 4 , the inputting signal of the first signal terminal is at a low level, the inputting signal of the second signal terminal is at a high level, the inputting signal of the third signal terminal is at a high level, the inputting signal of the fourth signal terminal is at a high level, the inputting signal of the fifth signal terminal is at a high level, the inputting signal of the sixth signal terminal is at a low level, and the inputting signal of the seventh signal terminal is at a high level.

FIG. 9 shows a schematic diagram of the current flow of the pixel circuit during the fourth period t 4 according to the embodiment of FIG. 4 . As shown in FIG. 9 , the direction of the arrow in the figure represents the current flow. During the fourth period t 4 , the inputting signal of the first signal terminal Reset is at low level, the inputting signal of the second signal terminal Reset 1 is at high level, the inputting signal of the third signal terminal Scan 1 is at a high level, the inputting signal of the fourth signal terminal Scan 2 is at a high level, the inputting signal of the fifth signal terminal Scan 3 is at a high level, the inputting signal of the sixth signal terminal EM 1 is at a low level, and the inputting signal of the seventh signal terminal EM 2 is at a high level. At this time, the first transistor M 1 and the seventh transistor M 7 are turned on, so that the source of the fifth transistor M 5 is connected to the voltage terminal Vdd. The potential of the second node N 2 is Vdd. The current flows through the first transistor M 1 and the fifth transistor M 5 to the seventh transistor M 7 , and then is output by the read terminal Readline. It can be derived by an equation for the transistor saturation current for the fifth transistor M 5 as follows:

I=K ( Vgs−Vth ) 2 =K [ Vdd −( V data1− Vth )− Vth ] 2 =K ( Vdd−V data1) 2

wherein K is the current coefficient of M 3 , and

K = C ox · μ · W L ,

μ is the field effect mobility of M 3 , C ox is the capacitance per sub-circuit area for the gate insulating layer, W is the channel width and L is the channel length.

It can be seen from the above equation that the operation current I of the source follower transistor M 5 is independent from its threshold voltage Vth of the source follower transistor M 5 at this time, but only related with Vdd and Vdata 1 . Vdata 1 is directly generated by the irradiation on the diode PN junction, avoiding a drift of the threshold voltage Vth of the source follower transistor, and ensuring an accuracy of the signal data.

At step 1005 , during the fifth period t 5 , the inputting signal of the first signal terminal is at a high level, the inputting signal of the second signal terminal is at a low level, the inputting signal of the third signal terminal is at a high level, the inputting signal of the fourth signal terminal is at a high level, the inputting signal of the fifth signal terminal is at a high level, the inputting signal of the sixth signal terminal is at a high level, and the inputting signal of the seventh signal terminal is at a high level.

FIG. 10 shows a schematic diagram of the current flow of the pixel circuit during the fifth period t 5 according to the embodiment of FIG. 4 . As shown in FIG. 10 , the direction of the arrow in the figure represents the current flow. During the fifth period t 5 , the inputting signal of the first signal terminal Reset is at a high level, the inputting signal of the second signal terminal Reset 1 is at a low level, the inputting signal of the third signal terminal Scan 1 is at a high level, the inputting signal of the fourth signal terminal Scan 2 is at a high level, the inputting signal of the fifth signal terminal Scan 3 is at a high level, the inputting signal of the sixth signal terminal EM 1 is at a high level and the inputting signal of the seventh signal terminal EM 2 is at a high level. At this time, the second transistor M 2 is turned on, and the other transistors are turned off. In this case, the first node N 1 is reset to the ground. Thus, the first node N 1 has the potential of 0V. Certainly, the potential of the first node N 1 could also be reset to a negative voltage.

At step 1006 , during the second period t 6 , the inputting signal of the first signal terminal is at a high level, the inputting signal of the second signal terminal is at a high level, the inputting signal of the third signal terminal is at a high level, the inputting signal of the fourth signal terminal is at a low level, the inputting signal of the fifth signal terminal is at a low level, the inputting signal of the sixth signal terminal is at a high level, and the inputting signal of the seventh signal terminal is at a high level.

FIG. 11 shows a schematic diagram of the current flow of the pixel circuit during the sixth period t 6 according to the embodiment of FIG. 4 . As shown in FIG. 11 , the direction of the arrow in the figure represents the current flow. During the sixth period t 6 , the inputting signal of the first signal terminal Reset is at a high level, the inputting signal of the second signal terminal Reset 1 is at a high level, the inputting signal of the third signal terminal Scan 1 is at a high level, the inputting signal of the fourth signal terminal Scan 2 is at a low level, the inputting signal of the fifth signal terminal Scan 3 is at a low level, the inputting signal of the sixth signal terminal EM 1 is at a high level, and the inputting signal of the seventh signal terminal EM 2 is at a high level. At this time, the sixth transistor M 6 , the fifth transistor M 5 and the fourth transistor M 4 are turned on. Since the potential of the first node N 1 is 0V previously, the fifth transistor M 5 will be charged again for compensating. The signal of Vdata 1 may start charging the first node N 1 via the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 , until the first node N 1 is charged to Vdata 2 −Vth. At this time, the voltage difference between the gate and the source of the fifth transistor M 5 is Vth. After the charging is completed, the potential of the first node N 1 will always be maintained at Vdata 2 −Vth.

At step 1007 , during the seventh period t 7 , the inputting signal of the first signal terminal is at a low level, the inputting signal of the second signal terminal is at a high level, the inputting signal of the third signal terminal is at a high level, the inputting signal of the fourth signal terminal is at a high level, the inputting signal of the fifth signal terminal is at a high level, the inputting signal of the sixth signal terminal is at a high level, and the inputting signal of the seventh signal terminal is at a low level.

FIG. 12 shows a schematic diagram of the current flow of the pixel circuit during the seventh period t 7 according to the embodiment of FIG. 4 . As shown in FIG. 12 , the direction of the arrow in the figure represents the current flow. During the seventh period t 7 , the inputting signal of the first signal terminal Reset is at a low level, the inputting signal of the second signal terminal Reset 1 is at a high level, the inputting signal of the third signal terminal Scan 1 is at a high level, the inputting signal of the fourth signal terminal Scan 2 is at a high level, the inputting signal of the fifth signal terminal Scan 3 is at a high level, the inputting signal of the sixth signal terminal EM 1 is at a high level, and the inputting signal of the seventh signal terminal EM 2 is at a low level.

At this time, the first transistor M 1 is turned on, so that the source of the fifth transistor M 5 is connected to the voltage terminal Vdd. The potential of the second node N 2 is Vdd. The current flows through the first transistor M 1 and the fifth transistor M 5 to the eighth transistor M 8 , so that the light emitting device OLED emits light. It can be derived by an equation for the transistor saturation current for the fifth transistor M 5 as follows:

I OLED =K ( Vgs−Vth ) 2 =K [ Vdd −( V data2− Vth )− Vth ] 2 =K ( Vdd−V data2) 2

It can be seen from the above equation that the current I oled is independent from the threshold voltage Vth at this time, but only related to the voltage value which is used to charge the fifth transistor M 5 by the second voltage terminal Vdata during the second charging period, Vdata 2 . Thus, the drift of the threshold voltage Vth of source follower transistor M 3 which is caused by processes and operations can be avoided, thereby ensuring an normal operation of the light emitting device OLED.

It can be understood that the above embodiments are merely exemplary embodiments used for illustrating the principle of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those skilled in the art, various variations and improvements may be made without departing from the spirit and essence of the embodiments of the present disclosure, and these variations and improvements are also considered as the scope of the embodiments of the present disclosure.