Voltage source converter (VSC) control system with active damping

The present disclosure relates to a Voltage Source Converter (VSC) control system for active damping (AD) of a resonance oscillation in the VSC.

A voltage-source converter (VSC) of high enough power rating may cause destabilization of grid resonances in the vicinity of the synchronous (fundamental) frequency f 1 . Of particular concern are subsynchronous torsional resonances. A torsional resonant frequency f r in the range of tens of hertz (Hz) is mirrored to the frequency f 1 -f r in the three-phase domain (as well as in the equivalent two-phase domain domain). It thus remains subsynchronous, i.e., it appears below the synchronous frequency. Often, the inherent damping of the system is sufficient to avoid resonance destabilization, but in some cases subsynchronous damping controllers are needed. In weak grids, the lowest electrical grid resonance may be close to, but above, the synchronous frequency, i.e., it is supersynchronous. Also in this case, destabilization may occur.

By “near-synchronous” we here imply a resonant frequency that may be subsynchronous or supersynchronous, but in the latter case typically not larger than 2f 1 .

A subsynchronous damping scheme, shown in FIG. 3 , has been proposed by K. M. Alawasa, Y. A.-R. I. Mohamed, and W. Xu, in “Active mitigation of subsynchronous interactions between PWM voltage-source converters and power networks”, IEEE Trans. Power Electron., vol. 29, no. 1, pp. 121-134, January 2014. The damping scheme comprises a phase-locked loop (PLL) and is effective for damping of torsional resonances.

The damping scheme proposed by Alawasa et al., mentioned above, is shown to have a drawback in that negative impact of the phase-locked loop (PLL) results. An objective of the present invention is to present an improved VSC control system which reduces or eliminates this negative impact. Stable operation is shown by simulation. The invention may be used for High-Voltage Direct Current (HVDC) applications, but also other power applications are contemplated such as Flexible Alternating Current Transmission System (FACTS) and medium-voltage drive applications.

According to an aspect of the present invention, there is provided a Voltage Source Converter (VSC) control system for active damping (AD) of a resonance oscillation in the VSC. The control system comprises a regular Phase-Locked Loop (PLL), as well as a slow PLL. The control system is arranged such that an imaginary part in the synchronous dq frame of the AD is obtainable from the slow PLL. The slow PLL is configured for having a closed-loop bandwidth which is less than a frequency, in a synchronous dq frame (i.e. a coordinate system with real and imaginary axii), of the resonance oscillation to be dampened.

It is to be noted that any feature of any of the aspects may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any of the other aspects. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following detailed disclosure, from the attached dependent claims as well as from the drawings.

Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to “a/an/the element, apparatus, component, means, step, etc.” are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated. The use of “first”, “second” etc. for different features/components of the present disclosure are only intended to distinguish the features/components from other similar features/components and not to impart any order or hierarchy to the features/components.

Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 is a schematic circuit diagram of a standard VSC control system.

FIG. 2 is a schematic illustration of a main-circuit model.

FIG. 3 is a schematic circuit diagram of a VSC control system with AD according to prior art.

FIG. 4 is a schematic circuit diagram of an embodiment of a VSC control system with AD according to the present invention.

FIG. 5 is a schematic circuit diagram of another embodiment of a VSC control system with AD according to the present invention.

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown. However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.

The cause of resonance destabilization is negative-resistance behaviour resulting from the various cascaded and parallel controllers that make up the VSC control system. A typical control system is depicted in FIG. 1 , where the PLL is illustrated within the dashed line, boldface letters denote complex space vectors and the superscript “s” denotes the stationary αβ reference frame. The controllers work as follows:

The Direct Current (DC or dc) voltage controller (DCVC) operates on the error between the dc-voltage reference u dc ref and the actual dc voltage u dc . Its output is the active-power-producing current reference i d ref . Reference u dc ref may be adjusted by an outer active-power controller in a cascaded fashion.

The ac-voltage controller (ACVC) operates on the error between the point-of-common-coupling (PCC)-voltage reference u pcc ref and the actual PCC-voltage modulus u pcc =|u pcc s |. Its output is the reactive-power-producing current reference i q . Reference up, may be adjusted by an outer reactive-power controller in a cascaded fashion.

Both current references are fed to the ac-current controller (ACCC), whose outputs are the VSC phase-voltage references u a,b,c ref , which form the input to the pulse width modulator. The ACCC may be implemented in the αβ frame or in the synchronous dq frame. The ACCC has as input signals also the converter input current i s and the transformation angle θ (or the exponential factors e ±jθ thereof).

The transformation angle θ is computed by the phase-locked loop (PLL), whose input u pccq is the imaginary part of the dq-transformed PCC voltage u pcc =e −jθ u pcc s . Input u pccq is fed to the PLL controller (PLLC), to whose output the nominal angular synchronous frequency ω nom is added, forming the instantaneous angular frequency co. This is then integrated into the transformation angle θ (modulo 271).

All the mentioned controllers are normally of proportionalintegral (PI) type.

To test the damping scheme proposed by Alawasa et al., a test system is implemented in Matlab, using a per-unit (pu) system. The base frequency is set to the synchronous frequency 50 Hz, but all other base values are unspecified. The main circuit is as shown in FIG. 2 . An LC series resonance (comprising an inductor L and a capacitor C), with resonant frequency f res =1/(2π√{square root over (L b C b )}), is inserted as a branch at the PCC. L is the phase-reactor-plus-transformer inductance and Lg is the grid inductance in front of the stiff grid voltage ν g . The inductances are selected as L=Lg=0.1 pu and Lb=1 pu. The closed-loop bandwidths of the respective control loops are chosen as ACCC: 4 pu, PLL: 1 pu, and DCVC: 0.5 pu. The ACVC proportional gain it set to 1 pu. Integral action is added to all controllers. The ACCC is implemented in the αβ frame, implying that a generalized integrator (i.e., a resonator at the synchronous frequency) is used.

Three cases are evaluated, all for inverter operation at 0.9 pu active power, but with different LC resonant frequencies. Relatively well-damped operation is obtained for f res =2f 1 , poorly damped operation for f res =1.5 f 1 , and unstable operation for f res =1.3f 1 .

As mentioned above, to mitigate subsynchronous torsional interaction, damping controllers can be added to the VSC control system. Two interesting damping schemes (and their combination) are proposed by Alawasa et al.

The rationale behind the first scheme is to inject a contribution to the current reference vector i ref =i d ref ji g ref , where j is the square root of −1, as

i ref modified =i ref +B ( s ) u pcc   (1)

where B(s) (s=d/dt) is a bandpass filter. The scheme can be generalized (enhanced) as shown in FIG. 3 , where the active damper (AD) operates on the difference between u pcc and its reference as

i ref modified =i ref +AD( u pcc −u pcc ref ).  (2)

The AD can now, theoretically, be a proportional gain G a , which acts as an active conductance

i ref modified =i ref +G a ( u pcc −u pcc ref ).  (3)

In practice, however, a low-pass filter may be added to suppress disturbances of higher frequencies. A hard limiter may also be added to avoid large transient injections.

The scheme proposed by Alawasa et al. in accordance with FIG. 3 is shown to give improved damping at subsynchronous frequencies. However, it often fails to stabilize a resonance close to, but above, the synchronous frequency, as will now be shown. We set G a =4 pu and obtain results in which the amplitudes of the oscillations in response to a step change no longer appear to grow over time for f res =1.3 f 1 , but the system is only marginally stable. Increasing G a does not give improved stability.

The proposed scheme of Alawasa et al. manages to add damping that compensates negative impact of the ACVC and the DCVC, but negative impact of the PLL actually increases. This can be understood as follows. Let us consider a scenario when the system is in the steady state, but oscillations of small amplitudes start to occur. These are modelled as incremental variables, denoted with the prefix A. For the PCC voltage, we thus have

u pcc s =e jω 1 t ( u pcc ref +Δu pccd +jΔu pccq ).  (4)

and for the transformation angle

θ=ω 1 t+Δθ.   (5)

Now, the dq transformation of the PCC voltage is given by

u pcc =e −j u pcc s =e −j(ω 1 t+Δθ) e jω 1 t ( u pcc ref +Δu pccd +jΔu pccq ).  (6)

Since Δθ is small, e −jθ ≈1−jΔθ, giving

u pcc ≈(1− j Δθ)( u pcc ref +Δu pccd +jΔu pccq ).  (7)

Neglecting cross products of Δ quantities yields

u pcc ≈u pcc ref +Δu pccd +j (Δ u pccq −u pcc ref Δθ)  (8)

and

u pcc −u pcc ref =Δu pccd +j (Δ u pccq −u pcc ref Δθ).  (9)

This shows that the correct d component, Δu pccd , of the error u pcc −u pcc ref is obtained, whereas in the q component a parasitic contribution is added: the term proportional to Δθ. This term is the reason for negative impact of the PLL in the scheme shown in FIG. 3 .

The negative PLL impact found in (9) can be reduced to a minimum by modifying the control scheme to the schemes 1 shown in FIGS. 4 and 5 . According to FIG. 5 , the d part of the active damping (ADO) is obtained by tapping the input signal to the ACVC. This gives the correct signal (after a sign change), because the modulus of (4) with u pcc ref subtracted is given by

The q part of the active damping (AD q ) is obtained by tapping the input signal u pccq s to an added slow PLL 3 (denoted with the sub- or superscript “s”). The gain of the slow PLL controller (PLLC s ) shall be significantly lower than that of the regular PLL 2 (PLLC).

The slow PLL 3 should have a bandwidth which is less than the frequency, as referred to the synchronous dq frame, of the oscillations to be dampened. Thus, the slow PLL 3 is slower, is running at a lower frequency, than the oscillations to be dampened such that Os (the angle tracking u pcc s ) does not include said oscillations.

For example, in some embodiments, the slow PLL 3 may be configured for having a closed-loop bandwidth which is a fraction of the closed-loop bandwidth of the regular PLL 2 , e.g. in the range of ⅕ to 1/20 of the closed-loop bandwidth of the regular PLL.

In some embodiments, the slow PLL 3 may be configured for having a closed-loop bandwidth which is less than 100, such as less than 50, radians per second, e.g. in the range of 5 to 40 or 5 to 20 radians per second.

PLLC s shall preferably not have an integral part. AD d and AD q may be low-pass filters with equal or different gains, possibly with hard limiters added.

It is not a necessity to include ac- and dc-voltage controllers, DCVC and ACVC in FIG. 5 . As long as the regular (fast) PLL 2 is used, the active damping contribution in the q direction may be added without modification. For the d direction contribution, a substitute for the reference u pcc ref , may be found, e.g. by means of a high-pass filter (HPF) | pcc s |, as shown in FIG. 4 . Consider (4) with u pcc ref =U pcc , we get

If the cut-off frequency of the high-pass filter is set lower than the frequency (as referred to the dq frame) of the oscillation that is to be damped, then the oscillating component Δu pccd passes through, whereas the mean value U pcc is rejected:

HPF(| u pcc s |)≈HPF( U pcc +Δu pccd )= u pccd .  (12)

The regular PLL 2 is still used to translate θ to the dq coordinate system. It may form its input signal as follows. Suppose that u pcc s =U pcc e jω1 . Then

u pccq =Im{e −jω u pcc s }=U pcc Im{e j(θ 1 −θ) }=U pcc sin(θ 1 −θ).  (13)

The closed loop formed around the PLL controller forces θ to converge to θ 1 , such that u pccq =0 in the steady state. This is why active damping with u pccq tapped from the regular PLL 2 may fail. The oscillations that are to be damped are suppressed in u pccq , since the regular PLL 2 may have too fast tracking in relation to the oscillation frequency. Slowing down the regular PLL would degrade the dynamic properties of the control system (such as the response in the ac- and dc-voltage control) and is not an option. This is why the slow PLL 3 has been added. The closed-loop bandwidth of the slow PLL 3 should be lower than the frequency (as referred to the dq frame) of the oscillation that is to be damped.

If the bandwidth of the slow PLL 3 is set to 0.02 pu and the same “active conductance” G a = 4 pu is used in both AD d and AD q . The new active damping scheme is evaluated for f res =1.3 f 1 , giving a significantly improved damping compared with the scheme of Alawasa et al.

The damping method of the present invention may be straight-forward to implement in existing e.g. HVDC control systems. It offers the potential of resistance to detrimental subsynchronous torsional interaction, regardless of the torsional frequencies. It may also be conjectured that stable operation using current control mode may be possible even for very weak grids.

The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.