OLED pixel driving circuit and pixel driving method

1. Field of the Invention

The present invention relates to the field of display techniques, and in particular to an OLED pixel driving circuit and pixel driving method.

2. The Related Arts

The organic light emitting diode (OLED) panel provides the advantages of active-luminescent, low driving voltage, high emission efficiency, quick response time, high resolution and contrast, near 180° viewing angle, wide operation temperature range, and capability to realize flexible display and large-area full-color display, and is heralded as the most promising display technology.

The OLED panel comprises a plurality of pixels arranged in an array, with each pixel driven by an OLED pixel driving circuit. The OLED is an electroluminescent device driven by electric current; that is, when a current flows through OLED, the OLED illuminates, and the brightness is determined by the current flowing through the OLED. The majority of known integrated circuit (IC) only transmits the voltage signal, and the pixel driving circuit of the OLED display must accomplish the task of translating the voltage signal into a current signal. The conventional pixel driving circuit usually uses a 2T1C structure, i.e., two thin film transistors (TFT) and a capacitor, to translate the voltage into current.

As shown in FIG. 1 , a conventional 2T1C pixel driving circuit for driving OLED device comprises: a first TFT T 10 , second TFT T 20 , and a capacitor C 10 . The first TFT T 10 is a switching TFT, the second TFT T 20 is a driving TFT, and the capacitor T 10 is a storage capacitor. Specifically, the first TFT T 10 has a gate connected to receive a scan signal Scan(n) corresponding to the row to which the pixel driving circuit belonging, a drain connected to receive a data signal Data, and a source electrically connected to a gate of the second TFT T 20 and to one end of the capacitor C 10 . The second TFT T 20 has a drain connected to receive a voltage VDD of a power source, and a source connected to receive an anode of the OLED D 10 ; the OLED D 10 has a cathode connected to receive a common ground voltage VSS; the capacitor C 10 has one end electrically connected to the drain of the second TFT T 20 , and the other end electrically connected to the source of the second TFT T 20 . When the OLED displays, the scan signal Scan(n) controls the first TFT T 10 to be turned on, the data signal Data passes through the first TFT T 10 and enters the gate of the second TFT T 20 and the capacitor C 10 . Then, the first TFT T 10 is cut off. Because of the storage of the capacitor C 10 , the gate voltage of the second TFT T 20 stays at the data signal voltage level so that the second TFT T 20 stays turned on. The driving current flows through the second TFT T 20 to enter the OLED D 10 and drives the OLED D 10 to emit light.

According to the equation calculating the current flowing through the driving TFT and the OLED:

I OLED =K ×( Vgs−Vth ) 2 ;

Wherein K is the intrinsic conductive factor, of the driving TFT, Vgs is the voltage difference across the gate and the source of the driving TFT, and Vth is the threshold voltage of the driving TFT.

As seen, the size of I OLED is related to the threshold voltage Vth of the driving TFT.

Because the non-uniformity of the TFT fabrication process, the threshold voltages of the driving TFTs of all pixels in the OLED display device will be inconsistent. Moreover, due to long operation time, the ageing of the driving TFT will cause voltage drift of the threshold voltage of the driving TFTs, leading to display unevenness and resulting in affecting the brightness of the OLED. The above conventional 2T1C pixel driving circuit does not compensate the threshold voltage Vth of the driving TFT, and therefore, the OLED panel will suffer the problem of uneven brightness.

The object of the present invention is to provide an OLED pixel driving circuit, able to compensate the threshold voltage of driving TFT, eliminate the impact of the threshold voltage of the driving TFT on the OLED, and achieve uniform display and improve image quality.

Another object of the present invention is to provide an OLED pixel driving method, able to compensate the threshold voltage of driving TFT, eliminate the impact of the threshold voltage of the driving TFT on the OLED, and achieve uniform display and improve image quality.

To achieve the above object, the present invention provides an OLED pixel driving circuit, comprising: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a first capacitor, a second capacitor, and an OLED;

the first TFT having a gate connected to a first node, a drain connected to a positive voltage power source, and a source connected to a drain of the third TFT; the first TFT being a driving TFT;

for a positive integer n>1, the second TFT having a gate connected to an n-th third scan signal corresponding to a row to which the pixel driving circuit belonging, a source connected to a data signal, and a drain connected to the first node;

the third TFT having a gate connected to an n-th second scan signal corresponding to a row to which the pixel driving circuit belonging, a drain connected to the source of the first TFT, and a source connected to a third node;

the fourth TFT having a gate connected to an (n−1)-th first scan signal corresponding to a row above the row to which the pixel driving circuit belonging, a source connected to a second node and one end of the second capacitor, and a drain connected to the third node and the other end of the second capacitor;

the fifth TFT having a gate connected to an n-th first scan signal corresponding to a row to which the pixel driving circuit belonging, a source connected to the second node, and a drain connected to a negative voltage power source;

the sixth TFT having a gate connected to an n-th fourth scan signal corresponding to a row to which the pixel driving circuit belonging, a source connected to the third node, and a drain connected to the negative voltage power source;

the first capacitor having one end connected to the first node and the other end connected to the second node;

the second capacitor having one end connected to the second node and the other end connected to the third node;

the OLED having an anode connected to the third node, and a cathode connected to the negative voltage power source.

According to a preferred embodiment of the present invention, the first TFT, the second TFT, the third TFT, the fourth TFT, the fifth TFT, and the sixth TFT are all low temperature polysilicon (LTPS) TFTs, oxide semiconductor TFTs, or amorphous silicon (a-Si) TFTs.

According to a preferred embodiment of the present invention, the (n−1)-th first scan signal, the n-th first scan signal, the n-th second scan signal, the n-th third scan signal, the n-th fourth scan signal, and the data signal are all provided by an external timing controller.

According to a preferred embodiment of the present invention, the (n−1)-th first scan signal, the n-th first scan signal, the n-th second scan signal, the n-th third scan signal, the n-th fourth scan signal, and the data signal are combined to correspond to a reset stage, a threshold voltage storage stage, a data writing stage, a capacitor cascading stage, and a display lighting stage, respectively.

According to a preferred embodiment of the present invention, in the reset stage, the (n−1)-th first scan signal is at high voltage, the n-th first scan signal is at low voltage, the n-th second scan signal is at low voltage, the n-th third scan signal is at low voltage, the n-th fourth scan signal is at high voltage, and the data signal is at low voltage;

in the threshold voltage storage stage, the (n−1)-th first scan signal is at low voltage, the n-th first scan signal is at high voltage, the n-th second scan signal is at high voltage, the n-th third scan signal is at high voltage, the n-th fourth scan signal is at low voltage, and the data signal is at a first high voltage; in the data writing stage, the (n−1)-th first scan signal is at low voltage, the n-th first scan signal is at high voltage, the n-th second scan signal is at low voltage, the n-th third scan signal is at high voltage, the n-th fourth scan signal is at low voltage, and the data signal is at a second high voltage higher than the first high voltage; in the capacitor cascading stage, the (n−1)-th first scan signal is at low voltage, the n-th first scan signal is at low voltage, the n-th second scan signal is at low voltage, the n-th third scan signal is at low voltage, the n-th fourth scan signal is at high voltage, and the data signal is at low voltage; in the display lighting stage, the (n−1)-th first scan signal is at low voltage, the n-th first scan signal is at low voltage, the n-th second scan signal is at high voltage, the n-th third scan signal is at low voltage, the n-th fourth scan signal is at low voltage, and the data signal is at low voltage.

The present invention also provides an OLED pixel driving method, which comprises the following steps:

the OLED pixel driving circuit, comprising: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a first capacitor, a second capacitor, and an OLED;

the first TFT having a gate connected to a first node, a drain connected to a positive voltage power source, and a source connected to a drain of the third TFT; the first TFT being a driving TFT;

for a positive integer n>1, the second TFT having a gate connected to an n-th third scan signal corresponding to a row to which the pixel driving circuit belonging, a source connected to a data signal, and a drain connected to the first node;

the third TFT having a gate connected to an n-th second scan signal corresponding to a row to which the pixel driving circuit belonging, a drain connected to the source of the first TFT, and a source connected to a third node;

the fourth TFT having a gate connected to an (n−1)-th first scan signal corresponding to a row above the row to which the pixel driving circuit belonging, a source connected to a second node and one end of the second capacitor, and a drain connected to the third node and the other end of the second capacitor;

the fifth TFT having a gate connected to an n-th first scan signal corresponding to a row to which the pixel driving circuit belonging, a source connected to the second node, and a drain connected to a negative voltage power source;

the sixth TFT having a gate connected to an n-th fourth scan signal corresponding to a row to which the pixel driving circuit belonging, a source connected to the third node, and a drain connected to the negative voltage power source;

the first capacitor having one end connected to the first node and the other end connected to the second node;

the second capacitor having one end connected to the second node and the other end connected to the third node;

the OLED having an anode connected to the third node, and a cathode connected to the negative voltage power source;

the (n−1)-th first scan signal providing high voltage, the n-th first scan signal providing low voltage, the n-th second scan signal providing low voltage, the n-th third scan signal providing low voltage, the n-th fourth scan signal providing high voltage, and the data signal providing low voltage; the second TFT, the third TFT, and the fifth TFT all being cut-off; the fourth TFT turned on to perform reset on the second capacitor; the sixth TFT turned on to perform reset on the OLED;

the (n−1)-th first scan signal becoming low voltage, the n-th first scan signal becoming high voltage, the n-th second scan signal becoming high voltage, the n-th third scan signal becoming high voltage, the n-th fourth scan signal becoming low voltage, and the data signal becoming a first high voltage; the fourth TFT and the sixth TFT being cut-off; the second TFT, the first TFT, the third TFT, and the fifth TFT all being turned on, and the data signal providing the first high voltage to the first node and charging the second capacitor until voltage difference V BA between the third node and the second node reaching V BA =V 1 D −V th , wherein V 1 D being the first high voltage provided by the data signal, V th being threshold voltage of the first TFT;

the (n−1)-th first scan signal maintaining at low voltage, the n-th first scan signal maintaining at high voltage, the n-th second scan signal becoming low voltage, the n-th third scan signal maintaining at high voltage, the n-th fourth scan signal maintaining at low voltage; the third TFT, the fourth TFT, and the sixth TFT being cut-off; the second TFT, the first TFT, and the fifth TFT being turned on, and the data signal providing to the first node a second high voltage higher than the first high voltage and charging the first capacitor so that voltage difference V GA between the first node and the second node equal to V GA =V 2 D , wherein V 2 D being the second high voltage provided by the data signal;

the (n−1)-th first scan signal maintaining at low voltage, the n-th first scan signal becoming low voltage, the n-th second scan signal maintaining at low voltage, the n-th third scan signal becoming low voltage, the n-th fourth scan signal becoming high voltage, and the data signal becoming low voltage; the second TFT, the third TFT, the fourth TFT, and the fifth TFT being cut-off; the sixth TFT being turned on, the first capacitor and the second capacitor being cascaded so that voltage difference V GB between the first node and the third node becoming V GB =V 2 D −V 1 D +V th ;

the (n−1)-th first scan signal maintaining at low voltage, the n-th first scan signal maintaining at low voltage, the n-th second scan signal becoming high voltage, the n-th third scan signal maintaining at low voltage, the n-th fourth scan signal becoming low voltage, and the data signal providing low voltage; the second TFT, the fourth TFT, the fifth TFT, and the sixth TFT being cut-off, the first TFT and the third TFT being turned on, the OLED emitting light, and current flowing through the OLED being independent of the threshold voltage of the driving TFT.

According to a preferred embodiment of the present invention, the first TFT, the second TFT, the third TFT, the fourth TFT, the fifth TFT, and the sixth TFT are all low temperature polysilicon (LTPS) TFTs, oxide semiconductor TFTs, or amorphous silicon (a-Si) TFTs.

According to a preferred embodiment of the present invention, the (n−1)-th first scan signal, the n-th first scan signal, the n-th second scan signal, the n-th third scan signal, the n-th fourth scan signal, and the data signal are all provided by an external timing controller.

The present invention further provides an OLED pixel driving circuit, comprising: a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a first capacitor, a second capacitor, and an OLED;

the first TFT having a gate connected to a first node, a drain connected to a positive voltage power source, and a source connected to a drain of the third TFT; the first TFT being a driving TFT;

for a positive integer n>1, the second TFT having a gate connected to an n-th third scan signal corresponding to a row to which the pixel driving circuit belonging, a source connected to a data signal, and a drain connected to the first node;

the third TFT having a gate connected to an n-th second scan signal corresponding to a row to which the pixel driving circuit belonging, a drain connected to the source of the first TFT, and a source connected to a third node;

the fourth TFT having a gate connected to an (n−1)-th first scan signal corresponding to a row above the row to which the pixel driving circuit belonging, a source connected to a second node and one end of the second capacitor, and a drain connected to the third node and the other end of the second capacitor;

the fifth TFT having a gate connected to an n-th first scan signal corresponding to a row to which the pixel driving circuit belonging, a source connected to the second node, and a drain connected to a negative voltage power source;

the sixth TFT having a gate connected to an n-th fourth scan signal corresponding to a row to which the pixel driving circuit belonging, a source connected to the third node, and a drain connected to the negative voltage power source;

the first capacitor having one end connected to the first node and the other end connected to the second node;

the second capacitor having one end connected to the second node and the other end connected to the third node;

the OLED having an anode connected to the third node, and a cathode connected to the negative voltage power source;

wherein the first TFT, the second TFT, the third TFT, the fourth TFT, the fifth TFT, and the sixth TFT being all low temperature polysilicon (LTPS) TFTs, oxide semiconductor TFTs, or amorphous silicon (a-Si) TFTs;

wherein the (n−1)-th first scan signal, the n-th first scan signal, the n-th second scan signal, the n-th third scan signal, the n-th fourth scan signal, and the data signal being all provided by an external timing controller;

wherein the (n−1)-th first scan signal, the n-th first scan signal, the n-th second scan signal, the n-th third scan signal, the n-th fourth scan signal, and the data signal being combined to correspond to a reset stage, a threshold voltage storage stage, a data writing stage, a capacitor cascading stage, and a display lighting stage, respectively;

wherein in the reset stage, the (n−1)-th first scan signal being at high voltage, the n-th first scan signal being at low voltage, the n-th second scan signal being at low voltage, the n-th third scan signal being at low voltage, the n-th fourth scan signal being at high voltage, and the data signal being at low voltage;

in the threshold voltage storage stage, the (n−1)-th first scan signal being at low voltage, the n-th first scan signal being at high voltage, the n-th second scan signal being at high voltage, the n-th third scan signal being s at high voltage, the n-th fourth scan signal being at low voltage, and the data signal being at a first high voltage;

in the data writing stage, the (n−1)-th first scan signal being at low voltage, the n-th first scan signal being at high voltage, the n-th second scan signal being at low voltage, the n-th third scan signal being at high voltage, the n-th fourth scan signal being at low voltage, and the data signal being at a second high voltage higher than the first high voltage;

in the capacitor cascading stage, the (n−1)-th first scan signal being at low voltage, the n-th first scan signal being at low voltage, the n-th second scan signal being at low voltage, the n-th third scan signal being at low voltage, the n-th fourth scan signal being at high voltage, and the data signal being at low voltage;

in the display lighting stage, the (n−1)-th first scan signal being at low voltage, the n-th first scan signal being at low voltage, the n-th second scan signal being at high voltage, the n-th third scan signal being at low voltage, the n-th fourth scan signal being at low voltage, and the data signal being at low voltage.

The present invention provides the following advantages. The present invention provides an OLED pixel driving circuit and pixel driving method, adopting a 6T2C structure driving circuit, an (n−1)th first scan signal, an n-th first scan signal, an n-th second scan signal, an n-th third scan signal and an n-th fourth scan signal are combined with the data signal to correspond to a reset stage, a threshold voltage storage stage, a data writing stage, a capacitor cascading stage, and a display lighting stage respectively so that the current flowing through the OLED is independent of the threshold voltage of driving TFT, i.e., the threshold voltage of the driving TFT is compensated and the impact of the threshold voltage of driving TFT on the OLED is eliminated so as to make the display brightness of the OLED panel more uniform and improve the display quality of the OLED panel.

To make the technical solution of the embodiments according to the present invention, a brief description of the drawings that are necessary for the illustration of the embodiments will be given as follows. Apparently, the drawings described below show only example embodiments of the present invention and for those having ordinary skills in the art, other drawings may be easily obtained from these drawings without paying any creative effort. In the drawings:

FIG. 1 is a schematic view showing a conventional OLED pixel driving circuit with 2T1C structure;

FIG. 2 is a schematic view showing an OLED pixel driving circuit provided by an embodiment of the present invention;

FIG. 3 is a schematic view showing the signal timing sequence for the OLED pixel driving circuit provided by an embodiment of the present invention;

FIG. 4 is a schematic view showing Step S 2 of the OLED pixel driving method provided by an embodiment of the present invention;

FIG. 5 is a schematic view showing Step S 3 of the OLED pixel driving method provided by an embodiment of the present invention;

FIG. 6 is a schematic view showing Step S 4 of the OLED pixel driving method provided by an embodiment of the present invention;

FIG. 7 is a schematic view showing Step S 5 of the OLED pixel driving method provided by an embodiment of the present invention;

FIG. 8 is a schematic view showing Step S 6 of the OLED pixel driving method provided by an embodiment of the present invention.

To further explain the technique means and effect of the present invention, the following uses preferred embodiments and drawings for detailed description.

The present invention provides an OLED pixel driving circuit, applicable to an OLED panel, the OLED panel comprising a plurality of pixels, with each pixel driven by an OLED pixel driving circuit. Refer to FIG. 2 and FIG. 3 . The OLED pixel driving circuit of the present invention is of a 6T2C structure, comprising: a first thin film transistor (TFT) T 1 , a second TFT T 2 , a third TFT T 3 , a fourth TFT T 4 , a fifth TFT T 5 , a sixth TFT T 6 , a first capacitor C 1 , a second capacitor C 2 , and an OLED D; wherein the first TFT T 1 being used as a driving TFT.

The first TFT T 1 has a gate connected to a first node G, a drain connected to a positive voltage power source VDD, and a source connected to a drain of the third TFT T 3 ; the first TFT T 1 is a driving TFT.

For a positive integer n>1, the second TFT T 2 has a gate connected to an n-th third scan signal Scan 3 ( 3 ) corresponding to a row to which the OLED pixel driving circuit belonging, a source connected to a data signal Data, and a drain connected to the first node G.

The third TFT T 3 has a gate connected to an n-th second scan signal Scan 2 ( n ) corresponding to a row to which the OLED pixel driving circuit belonging, a drain connected to the source of the first TFT T 1 , and a source connected to a third node B.

The fourth TFT T 2 has a gate connected to an (n−1)-th first scan signal Scan 1 ( n− 1) corresponding to a row above the row to which the OLED pixel driving circuit belonging, a source connected to a second node A and one end of the second capacitor C 2 , and a drain connected to the third node B and the other end of the second capacitor C 2 .

The fifth TFT T 5 has a gate connected to an n-th first scan signal Scan 1 ( n ) corresponding to a row to which the OLED pixel driving circuit belonging, a source connected to the second node A, and a drain connected to a negative voltage power source VSS.

The sixth TFT T 6 has a gate connected to an n-th fourth scan signal Scan 4 ( n ) corresponding to a row to which the OLED pixel driving circuit belonging, a source connected to the third node B, and a drain connected to the negative voltage power source VSS.

The first capacitor C 1 has one end connected to the first node G and the other end connected to the second node A.

The second capacitor C 2 ahs one end connected to the second node A and the other end connected to the third node B.

The OLED D has an anode connected to the third node B, and a cathode connected to the negative voltage power source VSS.

Specifically, the first TFT T 1 , the second TFT T 2 , the third TFT T 3 , the fourth TFT T 4 , the fifth TFT T 5 , and the sixth TFT T 6 are all low temperature polysilicon (LTPS) TFTs, oxide semiconductor TFTs, or amorphous silicon (a-Si) TFTs.

The (n−1)-th first scan signal Scan 1 ( n −1), the n-th first scan signal Scan 1 ( n ), the n-th second scan signal Scan 2 ( n ), the n-th third scan signal Scan 3 ( n ), the n-th fourth scan signal Scan 4 ( n ), and the data signal Data are all provided by an external timing controller. As shown in FIG. 3 , the (n−1)-th first scan signal Scan 1 ( n −1), the n-th first scan signal Scan 1 ( n ), the n-th second scan signal Scan 2 ( n ), the n-th third scan signal Scan 3 ( n ), the n-th fourth scan signal Scan 4 ( n ), and the data signal Data are combined to correspond to a reset stage t 1 , a threshold voltage storage stage t 2 , a data writing stage t 3 , a capacitor cascading stage t 4 , and a display lighting stage t 5 , respectively.

Refer to FIG. 2 , FIG. 3 and FIG. 4 . In the reset stage t 1 , the (n−1)-th first scan signal Scan 1 ( n −1) is at high voltage, the n-th first scan signal Scan 1 ( n ) is at low voltage, the n-th second scan signal Scan 2 ( n ) is at low voltage, the n-th third scan signal Scan 3 ( n ) is at low voltage, the n-th fourth scan signal Scan 4 ( n ) is at high voltage, and the data signal Data is at low voltage; the second TFT T 2 , the third TFT T 3 , and the fifth TFT T 5 are all cut-off; the fourth TFT T 4 is turned on so that the two ends of the second capacitor C 2 are shorted and the voltage difference of the two ends of the second capacitor C 2 is 0 to achieve the reset of the second capacitor C 2 ; the sixth TFT T 6 is turned on so that the anode and the cathode of the OLED D are shorted and the voltage difference of the anode and the cathode of the OLED D is 0 to achieve the reset of the OLED D. Because the (n−1)-th first scan signal Scan 1 ( n −1) is generated before the n-th first scan signal Scan 1 ( n ), the n-th fourth scan signal Scan 4 ( n ) and the (n−1)-th first scan signal Scan 1 ( n −1) are synchronized within the reset stage t 1 . Hence, before the n-th first scan signal Scan 1 ( n ) arrives, the reset of the second capacitor C 2 and the reset of OLED D are both completed.

Refer to FIG. 2 , FIG. 3 and FIG. 5 . In the threshold voltage storage stage t 2 , the (n−1)-th first scan signal Scan 1 ( n −1) is at low voltage, the n-th first scan signal Scan 1 ( n ) is at high voltage, the n-th second scan signal Scan 2 ( n ) is at high voltage, the n-th third scan signal Scan 3 ( n ) is at high voltage, the n-th fourth scan signal Scan 4 ( n ) is at low voltage, and the data signal Data is at a first high voltage V 1 D ; the fourth TFT T 4 and the sixth TFT T 6 are cut-off; the second TFT T 2 , the first TFT t 1 , the third TFT T 3 , and the fifth TFT T 5 are all turned on, and the first high voltage V 1 D provided by the data signal Data reaches the first node G and charges the second capacitor C 2 through the first TFT T 1 and the third TFT T 3 until voltage difference V BA between the two ends of the second capacitor C 2 , i.e., the third node B and the second node A, reaches V BA =V 1 D −V th , wherein V 1 D is the first high voltage provided by the data signal data, V th is threshold voltage of the first TFT T 1 .

Refer to FIG. 2 , FIG. 3 and FIG. 6 . In the data writing stage t 3 , the (n−1)-th first scan signal Scan 1 ( n− 1) is at low voltage, the n-th first scan signal Scan 1 ( n ) is at high voltage, the n-th second scan signal Scan 2 ( n ) is at low voltage, the n-th third scan signal Scan 3 ( n ) is at high voltage, the n-th fourth scan signal Scan 4 ( n ) is at low voltage, and the data signal Data is at a second high voltage V 2 D higher than the first high voltage V 1 D ; the third TFT T 3 , the fourth TFT T 4 , and the sixth TFT T 6 are cut-off; the second TFT T 2 , the first TFT T 1 , and the fifth TFT T 5 are turned on, and second high voltage V 2 D of the data signal Data reaches the first node G and charges the first capacitor C 1 so that voltage difference V GA between the first node G and the second node A is equal to V GA =V 2 D .

Refer to FIG. 2 , FIG. 3 and FIG. 7 . In the capacitor cascading stage t 4 , the (n−1)-th first scan signal Scan 1 ( n− 1) is at low voltage, the n-th first scan signal Scan 1 ( n ) is at low voltage, the n-th second scan signal Scan 2 ( n ) is at low voltage, the n-th third scan signal Scan 3 ( n ) is at low voltage, the n-th fourth scan signal Scan 4 ( n ) is at high voltage, and the data signal Data is at low voltage; the second TFT T 2 , the third TFT T 3 , the fourth TFT T 4 , and the fifth TFT T 5 are cut-off; the sixth TFT T 6 is turned on, the first capacitor C 1 and the second capacitor C 2 are cascaded so that voltage difference V SB between the first node G and the third node B becomes:

V GB =V 2 D −( V 1 D −V th )= V 2 D −V 1 D +V th ,

In the capacitor cascading stage t 4 , because the sixth TFT T 6 shorts the anode and the cathode of the OLED D, the OLED D does not emit light.

Refer to FIG. 2 , FIG. 3 and FIG. 8 . In the display lighting stage t 5 , the (n−1)-th first scan signal Scan 1 ( n −1) is at low voltage, the n-th first scan signal Scan 1 ( n ) is at low voltage, the n-th second scan signal Scan 2 ( n ) is at high voltage, the n-th third scan signal Scan 3 ( n ) is at low voltage, the n-th fourth scan signal Scan 4 ( n ) is at low voltage, and the data signal Data is at low voltage; the second TFT T 2 , the fourth TFT T 4 , the fifth TFT T 5 , and the sixth TFT T 6 are cut-off, the first TFT T 1 and the third TFT T 3 are turned on; under the storage effect of the first capacitor C 1 and the second capacitor C 2 , the voltage difference V GB between the first node G and the third node B, i.e., the voltage difference Vgs between the gate and the source of the first TFT T 1 stays at:

V GB =Vgs=V 2 D −V 1 D +V th ;

And the OLED D emits light.

Based on the equation to compute the current I OLED flowing through the OLED D:

I OLED =K ×( Vgs−V th ) 2 =K ×( V 2 D −V 1 D +V th −V th ) 2 =K ×( V 2 D −V 1 D ) 2

Wherein K is the intrinsic conductive factor of the driving TFT, i.e., the first TFT T 1 . As shown, the current flowing through the OLED D is independent of the threshold voltage V th of the driving TFT T 1 , i.e., the first TFT T 1 . As such, the present invention eliminates the impact of the threshold voltage V th of the driving TFT on the OLED D, achieves uniform display and improves the OLED image quality.

Refer to FIGS. 4-8 . The present invention also provides an OLED pixel driving method, which comprises the following steps:

Step S 1 : providing an OLED pixel driving circuit of a 6T2C structure as shown in FIG. 2 ; the details of the OLED pixel driving circuit will not be repeated.

Specifically, the first TFT T 1 , the second TFT T 2 , the third TFT T 3 , the fourth TFT T 4 , the fifth TFT T 5 , and the sixth TFT T 6 are all low temperature polysilicon (LTPS) TFTs, oxide semiconductor TFTs, or amorphous silicon (a-Si) TFTs. The (n−1)-th first scan signal Scan 1 ( n −1), the n-th first scan signal Scan 1 ( n ), the n-th second scan signal Scan 2 ( n ), the n-th third scan signal Scan 3 ( n ), the n-th fourth scan signal Scan 4 ( n ), and the data signal Data are all provided by an external timing controller.

Step S 2 : referring to FIG. 3 and FIG. 4 , entering reset stage t 1 .

The (n−1)-th first scan signal Scan 1 ( n− 1) provides high voltage, the n-th first scan signal Scan 1 ( n ) provides low voltage, the n-th second scan signal Scan 2 ( n ) provides low voltage, the n-th third scan signal Scan 3 ( n ) provides low voltage, the n-th fourth scan signal Scan 4 ( n ) provides high voltage, and the data signal Data provides low voltage.

The second TFT T 2 , the third TFT T 3 , and the fifth TFT T 5 are all cut-off; the fourth TFT T 4 is turned on so that the two ends of the second capacitor C 2 are shorted and the voltage difference of the two ends of the second capacitor C 2 is 0 to achieve the reset of the second capacitor C 2 ; the sixth TFT T 6 is turned on so that the anode and the cathode of the OLED D are shorted and the voltage difference of the anode and the cathode of the OLED D is 0 to achieve the reset of the OLED D.

Step S 3 : referring to FIG. 3 and FIG. 5 , entering threshold voltage storage stage t 2 .

The (n−1)-th first scan signal Scan 1 ( n− 1) becomes low voltage, the n-th first scan signal Scan 1 ( n ) becomes high voltage, the n-th second scan signal Scan 2 ( n ) becomes high voltage, the n-th third scan signal Scan 3 ( n ) becomes high voltage, the n-th fourth scan signal Scan 4 ( n ) becomes low voltage, and the data signal Data becomes a first high voltage.

The fourth TFT T 4 and the sixth TFT T 6 are cut-off; the second TFT T 2 , the first TFT t 1 , the third TFT T 3 , and the fifth TFT T 5 are all turned on, and the first high voltage V 1 D provided by the data signal Data reaches the first node G and charges the second capacitor C 2 through the first TFT T 1 and the third TFT T 3 until voltage difference V BA between the third node B and the second node A reaches V BA =V 1 D −V th , wherein V 1 D is the first high voltage provided by the data signal data, V th is threshold voltage of the first TFT T 1 .

Step S 4 : referring to FIG. 3 and FIG. 6 , entering data writing stage t 3 .

The (n−1)-th first scan signal Scan 1 ( n− 1) maintains at low voltage, the n-th first scan signal Scan 1 ( n ) maintains at high voltage, the n-th second scan signal Scan 2 ( n ) becomes low voltage, the n-th third scan signal Scan 3 ( n ) maintains at high voltage, the n-th fourth scan signal Scan 4 ( n ) maintains at low voltage.

The third TFT T 3 , the fourth TFT T 4 , and the sixth TFT T 6 are cut-off; the second TFT T 2 , the first TFT T 1 , and the fifth TFT T 5 are turned on, and second high voltage V 2 D of the data signal Data reaches the first node G and charges the first capacitor C 1 so that voltage difference V GA between the first node G and the second node A is equal to V GA =V 2 D .

Step S 5 : referring to FIG. 3 and FIG. 7 , entering capacitor cascading stage t 4 .

The (n−1)-th first scan signal Scan 1 ( n− 1) maintains at low voltage, the n-th first scan signal Scan 1 ( n ) becomes low voltage, the n-th second scan signal Scan 2 ( n ) maintains at low voltage, the n-th third scan signal Scan 3 ( n ) becomes low voltage, the n-th fourth scan signal Scan 4 ( n ) becomes high voltage, and the data signal Data becomes low voltage.

The second TFT T 2 , the third TFT T 3 , the fourth TFT T 4 , and the fifth TFT T 5 are cut-off; the sixth TFT T 6 is turned on, the first capacitor C 1 and the second capacitor C 2 are cascaded so that voltage difference V GB between the first node G and the third node B becomes:

V GB =V 2 D −( V 1 D −V th )= V 2 D −V 1 D +V th ;

In the capacitor cascading stage t 4 , because the sixth TFT T 6 shorts the anode and the cathode of the OLED D, the OLED D does not emit light.

Step S 6 : referring to FIG. 3 and FIG. 8 , entering display lighting stage t 5 .

The (n−1)-th first scan signal Scan 1 ( n− 1) maintains at low voltage, the n-th first scan signal Scan 1 ( n ) maintains at low voltage, the n-th second scan signal Scan 2 ( n ) becomes high voltage, the n-th third scan signal Scan 3 ( n ) maintains at low voltage, the n-th fourth scan signal Scan 4 ( n ) becomes low voltage, and the data signal Data provides low voltage.

the second TFT T 2 , the fourth TFT T 4 , the fifth TFT T 5 , and the sixth TFT T 6 are cut-off, the first TFT T 1 and the third TFT T 3 are turned on; under the storage effect of the first capacitor C 1 and the second capacitor C 2 , the voltage difference V GB between the first node G and the third node B, i.e., the voltage difference Vgs between the gate and the source of the first TFT T 1 stays at:

V GB =Vgs=V 2 D −V 1 D +V th ;

And the OLED D emits light.

Based on the equation to compute the current I OLED flowing through the OLED D:

I OLED =K ×( Vgs−V th ) 2 =K ×( V 2 D −V 1 D +V th −V th ) 2 =K ×( V 2 D −V 1 D ) 2

Wherein K is the intrinsic conductive factor of the driving TFT, i.e., the first TFT T 1 . As shown, the current flowing through the OLED D is independent of the threshold voltage V th of the driving TFT T 1 , i.e., the first TFT T 1 . As such, the present invention eliminates the impact of the threshold voltage V th of the driving TFT on the OLED D, achieves uniform display and improves the OLED image quality.

In summary, the present invention provides an OLED pixel driving circuit and pixel driving method, adopting a 6T2C structure driving circuit, an (n−1)th first scan signal, an n-th first scan signal, an n-th second scan signal, an n-th third scan signal and an n-th fourth scan signal are combined with the data signal to correspond to a reset stage, a threshold voltage storage stage, a data writing stage, a capacitor cascading stage, and a display lighting stage respectively so that the current flowing through the OLED is independent of the threshold voltage of driving TFT, i.e., the threshold voltage of the driving TFT is compensated and the impact of the threshold voltage of driving TFT on the OLED is eliminated so as to make the display brightness of the OLED panel more uniform and improve the display quality of the OLED panel.

It should be noted that in the present disclosure the terms, such as, first, second are only for distinguishing an entity or operation from another entity or operation, and does not imply any specific relation or order between the entities or operations. Also, the terms “comprises”, “include”, and other similar variations, do not exclude the inclusion of other non-listed elements. Without further restrictions, the expression “comprises a . . . ” does not exclude other identical elements from presence besides the listed elements.

Embodiments of the present invention have been described, but not intending to impose any unduly constraint to the appended claims. Any modification of equivalent structure or equivalent process made according to the disclosure and drawings of the present invention, or any application thereof, directly or indirectly, to other related fields of technique, is considered encompassed in the scope of protection defined by the claims of the present invention.