Synapse and a synapse array

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2017-0049192, filed on Apr. 17, 2017, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.

1. Field

The present disclosure relates to a neuromorphic device, and more particularly, to a synapse including dual memristors, a synapse array including the synapse, and a neuromorphic device including the synapse array.

2. Description of the Related Art

Recently, much attention has been paid to neuromorphic devices, which include chips that mimic the human brain. A neuromorphic device includes a plurality of pre-synaptic neurons, a plurality of post-synaptic neurons, and a plurality of synapses. The neuromorphic device outputs pulses or spikes having various levels, amplitudes, and/or times, according to a learning state of the neuromorphic device.

Embodiments of the present disclosure include synapses having dual memristors.

Embodiments of the present disclosure include an array including the synapses having dual memristors.

Embodiments of the present disclosure include neuromorphic devices including the synapses having dual memristors.

The present disclosure is not limited to the above-mentioned embodiments, and it would be obvious to those skilled in the art that there may be other embodiments of the present disclosure that are not mentioned above.

A neuromorphic device in accordance with an embodiment of the present disclosure may include a pre-synaptic neuron, a row line extending from the pre-synaptic neuron in a row direction, a post-synaptic neuron, a column line extending from the post-synaptic neuron in a column direction, and a synapse coupled between the row line and the column line. The synapse may be disposed in an intersection region between the row line and the column line. The synapse may include a first unit synapse and a second unit synapse. The first unit synapse may include a resistive memory device. The second unit synapse may include a phase-changeable memory device.

The first unit synapse may include a first memristor including the resistive memory device and a selecting element, and the second unit synapse may include a second memristor including the phase-changeable memory device and a second selecting element.

The row line may include a first row line and a second row line. The first row line may be electrically connected with the first unit synapse. The second row line may be electrically connected with the second unit synapse.

The column line may include a first column line and a second column line. The first column line may be electrically connected with the first unit synapse. The second column line may be electrically connected with the second unit synapse.

The neuromorphic device may further include a first selecting line being electrically connected with the first selecting element and extending in the column direction and a second selecting line being electrically connected with the second selecting element and extending in the column direction.

The neuromorphic device may further include a selecting signal delay circuit electrically connected with the second selecting line.

The post-synaptic neuron may include a first totalizer electrically connected with the first column line, a second totalizer electrically connected with the second column line, and a normalizer electrically connected with the first totalizer and the second totalizer.

The post-synaptic neuron may further include a pulse generator and a pulse delay circuit.

The post-synaptic neuron may further include an integrator and a comparator between the normalizer and the pulse generator.

The pre-synaptic neuron comprises a row signal delay circuit electrically connected with the second row line.

A neuromorphic device in accordance with an embodiment of the present disclosure may include a pre-synaptic neuron, a first row line and a second row line each extending from the pre-synaptic neuron in a row direction, a post-synaptic neuron, a first column line, a second column line, a first selecting line, and a second selecting line each extending from the post-synaptic neuron in a column direction, a first unit synapse electrically connected with the first row line, the first column line, and the first selecting line, and a second unit synapse electrically connected with the second row line, the second column line, and the second selecting line.

The first unit synapse may include a resistive memory device and a first selecting element. The second unit synapse may include a phase-changeable memory device and a second selecting element.

The neuromorphic device may further include a row signal delay circuit on the second row line.

The neuromorphic device may further include a selecting signal delay circuit on the second selecting line.

The post-synaptic neuron may include a first totalizer electrically connected with the first column line, a second totalizer electrically connected with the second column line, a normalizer electrically connected with the first totalizer and the second totalizer, an integrator electrically connected with the normalizer, and a pulse generator electrically connected with the integrator. The pulse generator may be electrically connected with the first selecting line and the second selecting line.

A neuromorphic device in accordance with an embodiment of the present disclosure may include a pre-synaptic neuron, a row line extending from the pre-synaptic neuron in a row direction, a post-synaptic neuron, a column line extending from the post-synaptic neuron in a column direction, and a synapse coupled between the row line and the column line. The synapse may be disposed in an intersection region between the row line and the column line. The synapse may include a first unit synapse and the second unit synapse. A resistance of the first unit synapse may change more abruptly than a resistance of the second unit synapse in a potentiation mode. The resistance of the second unit synapse may change more abruptly than the resistance of the first unit synapse in a depression mode.

The resistance of the first unit synapse may change more gradually than the resistance of the second unit synapse in the depression mode. The resistance of the second unit synapse may change more gradually than the resistance of the first unit synapse in the potentiation mode.

The first unit synapse may include a resistive memory device. The second unit synapse may include a phase-changeable memory device.

The row line may include a first row line and a second row line. The first row line may be electrically connected with the first unit synapse. The second row line may be electrically connected with the second unit synapse. The column line may include a first column line and a second column line. The first column line may be electrically connected with the first unit synapse. The second column line may be electrically connected with the second unit synapse.

The neuromorphic device may further include a first selecting line electrically connecting the post-synaptic neuron to the first unit synapse, and a second selecting line electrically connecting the post-synaptic neuron to the second unit synapse.

Details of other embodiments are included in the detailed description and drawings.

FIGS. 1A and 1B are diagrams schematically illustrating synapse arrays of neuromorphic devices in accordance with embodiments of the present disclosure.

FIGS. 2A to 2D are diagrams schematically illustrating pre-synaptic neurons of synapse arrays of neuromorphic devices in accordance with embodiments of the present disclosure.

FIGS. 3A and 3B are diagrams schematically illustrating synapses and synapse arrays of neuromorphic devices in accordance with embodiments of the present disclosure.

FIG. 4A is a graph schematically illustrating a change in conductivity of a resistive memory device with respect to a number of pulses applied to the resistive memory device in accordance with an embodiment of the present disclosure.

FIG. 4B is a graph schematically illustrating a change in conductivity of a phase-changeable memory device with respect to a number of pulses applied to the phase-changeable memory device in accordance with an embodiment of the present disclosure.

FIGS. 5A and 5B are diagrams schematically illustrating post-synaptic neurons and synapse arrays of neuromorphic devices in accordance with embodiments of the present disclosure.

FIG. 6 is a diagram schematically illustrating a synapse array of a neuromorphic device in accordance with an embodiment of the present disclosure.

FIG. 7A is a timing diagram schematically illustrating a method for depressing a synapse in accordance with an embodiment of the present disclosure.

FIG. 7B is a timing diagram schematically illustrating a method for potentiating a synapse in accordance with an embodiment of the present disclosure.

FIG. 8 is a diagram schematically illustrating a pattern recognition system in accordance with an embodiment of the present disclosure.

Various embodiments will be described below in more detail with reference to the accompanying drawings. Embodiments of the present disclosure may, however, have different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the claims to those skilled in the art.

Throughout the specification, like reference numerals refer to the same elements. Therefore, although the same or similar reference numerals are not mentioned or described in the corresponding drawing, the reference numerals may be described with reference to other drawings. Furthermore, although elements are not represented by reference numerals, the elements may be described with reference to other drawings.

FIGS. 1A and 1B are diagrams schematically illustrating synapse arrays of neuromorphic devices in accordance with embodiments of the present disclosure.

Referring to FIG. 1A , a synapse array in accordance with an embodiment of the present disclosure may include a plurality of pre-synaptic neurons 10 , a plurality of post-synaptic neurons 20 , and a plurality of synapses 30 . The synapse array may include a plurality of row line pairs RL 1 and RL 2 , a plurality of column line pairs CL 1 and CL 2 , and a plurality of selecting line pairs SL 1 and SL 2 . The plurality of row line pairs RL 1 and RL 2 may extend from the plurality of pre-synaptic neurons 10 in a row direction, respectively. The plurality of column line pairs CL 1 and CL 2 , and the plurality of selecting line pairs SL 1 and SL 2 , may respectively extend from the plurality of post-synaptic neurons 20 in a column direction.

The row line pairs RL 1 and RL 2 may include first row lines RL 1 and second row lines RL 2 , the column line pairs CL 1 and CL 2 may include first column lines CL 1 and second column lines CL 2 , and the selecting line pairs SL 1 and SL 2 may include first selecting lines SL 1 and second selecting lines SL 2 .

The synapses 30 may be disposed and arrayed between the row line pairs RL 1 and RL 2 , the column line pairs CL 1 and CL 2 , and the selecting lines SL 1 and SL 2 . That is, one of the synapses 30 may be electrically connected with one of the first row lines RL 1 , one of the second row lines RL 2 , one of the first column lines CL 1 , one of the second column lines CL 2 , one of the first selecting lines SL 1 , and one of the second selecting lines SL 2 . The synapses 30 may be disposed in intersection regions among the row line pairs RL 1 and RL 2 , the column line pairs CL 1 and CL 2 , and the selecting line pairs SL 1 and SL 2 . For example, the synapses 30 may be disposed in a region where the row line pairs RL 1 and RL 2 , the column line pairs CL 1 and CL 2 , and the selecting line pairs SL 1 and SL 2 intersect in a direction perpendicular to the row direction and the column direction. As an illustrative example, four of the pre-synaptic neurons 10 four of the post-synaptic neurons 20 , and sixteen of the synapses 30 are illustrated in FIGS. 1A and 1B .

The pre-synaptic neurons 10 may transmit row signals to the synapses 30 through the row line pairs RL 1 and RL 2 . Each of the row signals may have a pulse shape.

The post-synaptic neurons 20 may receive column signals from the synapses 30 through the column line pairs CL 1 and CL 2 , and may transmit selecting signals to the synapses 30 through the selecting line pairs SL 1 and SL 2 . Each of the selecting signals may have a pulse shape.

The synapses 30 may include variable resistors having multiple resistance levels. The synapses 30 may be gradually changed from/to a high resistance state (HRS) to/from a low resistance state (LRS) according to numbers of pulses input to the synapses 30 from the pre-synaptic neurons 10 and/or the post-synaptic neurons 20 , time differences between the input pulses, and/or voltage differences between the input pulses. Embodiments of the synapses 30 will also be described with reference to other drawings.

Referring to FIG. 1B , a synapse array of a neuromorphic device in accordance with the present disclosure may include the plurality of pre-synaptic neurons 10 , the plurality of post-synaptic neurons 20 , the plurality of synapses 30 , and a plurality of selecting controllers 40 . The synapse array may further include the plurality of row line pairs RL 1 and RL 2 , the plurality of column line pairs CL 1 and CL 2 , and the plurality of selecting line pairs SL 1 and SL 2 . The plurality of row line pairs RL 1 and RL 2 may extend from the plurality of pre-synaptic neurons 10 in the row direction, respectively. The plurality of column line pairs CL 1 and CL 2 , and the plurality of selecting line pairs SL 1 and SL 2 , may respectively extend from the plurality of post-neurons 20 in the column direction.

The post-synaptic neurons 20 may receive the column signals from the synapses 30 through the column line pairs CL 1 and CL 2 , and the selecting controllers 40 may transmit the selecting signals to the synapse 30 through the selecting line pairs SL 1 and SL 2 . Each of the selecting signals may have a pulse shape.

FIGS. 2A to 2D are diagrams schematically illustrating pre-synaptic neurons 10 a to 10 d of synapse arrays of a neuromorphic devices in accordance with embodiments of the present disclosure.

Referring to FIG. 2A , a pre-synaptic neuron 10 a of a synapse array may include a row signal generator 11 and a row signal delay circuit 19 .

The row signal generator 11 may output a basic row signal RS 0 onto a basic row line RL 0 . The basic row signal RS 0 may have a pulse shape, and include at least one of a potentiation signal to potentiate the synapse 30 , a depression signal to depress the synapse 30 , and a data signal to output data stored by the synapse 30 . The basic row line RL 0 may be divaricated into the first row line RL 1 and the second row line RL 2 .

The row signal delay circuit 19 may be disposed on the second row line RL 2 . The row signal delay circuit 19 may include an odd number of inverters. Accordingly, the row signal delay circuit 19 may output a second row signal RS 2 , which has an inverted phase and a delayed timing with respect to the basic row signal RS 0 , to the synapse 30 for a predetermined time. In addition, the first row line RL 1 may provide a first row signal RS 1 , which has the same phase and the same pulse timing as the basic row signal RS 0 , to the synapse 30 . Because the basic row signal RS 0 and the first row signal RS 1 have the same phase and the same pulse timing, the second row signal RS 2 may also have an inverted phase and a delayed pulse timing with respect to the first row signal RS 1 .

Referring to FIG. 2B , a pre-synaptic neuron 10 b of a synapse array of a neuromorphic device in accordance with an embodiment of the present disclosure may include a row signal generator 11 , a row line selector 13 , and a row signal delay circuit 19 . A basic row line RL 0 may be divaricated into a first row line RL 1 and a second row line RL 2 , and the second row line RL 2 may be divaricated into a non-inverted second row line RL 2 n and an inverted second row line RL 2 i . The divaricated non-inverted second row line RL 2 n and the inverted second row line RL 2 i may be merged into the second row line RL 2 .

The row line selector 13 may be disposed at a junction point in which the second row line RL 2 is divaricated into the non-inverted second row line RL 2 n and the inverted second row line RL 2 i . The row line selector 13 may selectively electrically connect a front portion of the second row line RL 2 , which has been divaricated from the basic row line RL 0 , to one of the non-inverted second row line RL 2 n and the inverted second row line RL 2 i . For example, when it is desirable that the second row signal RS 2 has the same phase and the same pulse timing as the basic row signal RS 0 , the row line selector 13 may electrically connect the basic row line RL 0 to the non-inverted second row line RL 2 n . Accordingly, the first row signal RS 1 and the second row signal RS 2 may have the same phase and the same pulse timing. In contrast, when it is desirable that the second row signal RS 2 has an inverted phase and a delayed pulse timing from the basic row signal RS 0 , the row line selector 13 may electrically connect the basic row line RL 0 to the inverted second row line RL 2 i . Accordingly, the second row signal RS 2 may have the inverted phase and the delayed pulse timing from the basic row signal RS 0 .

The non-inverted second row line RL 2 n and the inverted second row line RL 2 i may be merged into the second row line RL 2 . Accordingly, the second row signal RS 2 output on the second row line RL 2 may be one of the non-inverted row signal RS 2 n and the inverted second row signal RS 2 i . The non-inverted row signal RS 2 n may have the same phase and the same pulse timing as the first row signal RS 1 , and the inverted row signal RS 2 i may have the inverted phase and the delayed pulse timing, with respect to the basic row signal RS 0 or the first row signal RS 1 . Accordingly, the second row signal RS 2 may have the same phase and the same pulse timing, or may have the inverted phase and the delayed pulse timing, with respect to the basic row signal RS 0 and the first row signal RS 1 .

Referring to FIG. 2C , a pre-synaptic neuron 10 c of a synapse array of a neuromorphic device in accordance with an embodiment of the present disclosure may include a row signal generator 11 , a row signal delay circuit 19 , and a row line selector 13 .

The row line selector 13 may be disposed at a junction point which the non-inverted second row line RL 2 n and the inverted second row line RL 2 i are merged into the second row line RL 2 . The row signal selector 13 may selectively electrically connect one of the non-inverted second row line RL 2 n and the inverted second row line RL 2 i to the second row line RL 2 , according to an operation mode of the synapse array of the neuromorphic device. Accordingly, the second row signal RS 2 may be one of the non-inverted row signal RS 2 n and the inverted row signal RS 2 i.

Referring to FIG. 2D , a pre-synaptic neuron 10 d may include a row signal generator 11 , a row signal delay circuit 19 , and a row line selector 13 .

A basic row line RL 0 may be divaricated into a first row line RL 1 and a second row line RL 2 . The row signal delay circuit 19 may be disposed on the second row line RL 2 , and may invert and delay the basic row signal RS 0 to generate the inverted second row signal RS 2 i . The row line selector 13 may selectively electrically connect one of the first row line RL 1 and the inverted second row line RL 2 i to the second row line RL 2 , according to the operation mode of the synapse array of the neuromorphic device. Accordingly, the second row signal RS 2 may be one of the first row signal RS 1 and the inverted second row signal RS 2 i.

FIGS. 3A and 3B are diagrams schematically illustrating synapses 30 a and 30 b of synapse arrays of neuromorphic devices in accordance with embodiments of the present disclosure.

Referring to FIGS. 3A and 3B , synapses 30 a and 30 b may each include a first unit synapse 31 and a second unit synapse 32 . The first unit synapse 31 may include a first memristor 33 _ 1 and a first selecting element 35 _ 1 , and the second unit synapse 32 may include a second memristor 33 _ 2 and a second selecting element 35 _ 2 . The first selecting element 35 _ 1 and the second selecting element 35 _ 2 may each include a 3-terminal selecting element such as a MOS transistor or a 2-terminal selecting element such as a diode. In the embodiments of the present disclosure described with respect to FIGS. 3A and 3B , the first selecting element 35 _ 1 and the second selecting element 35 _ 2 may be referred to as a first transistor 35 _ 1 and a second transistor 35 _ 2 , respectively.

Referring to FIG. 3A , a first electrode of the first memristor 33 _ 1 may be electrically connected with the first row line RL 1 , and a second electrode of the first memristor 33 _ 1 may be electrically connected with a drain electrode of the first transistor 35 _ 1 . A source electrode of the first transistor 35 _ 1 may be electrically connected with the first column line CL 1 , and a gate electrode of the first transistor 35 _ 1 may be electrically connected with the first selecting line SL 1 . The first memristor 33 _ 1 may include a resistive memory device such as a resistive random access memory (ReRAM).

A first electrode of the second memristor 33 _ 2 may be electrically connected with the second row line RL 2 , and a second electrode of the second memristor 33 _ 2 may be electrically connected with a drain electrode of the second transistor 35 _ 2 . A source electrode of the second transistor 35 _ 2 may be electrically connected with the second column line CL 2 , and a gate electrode of the second transistor 35 _ 2 may be electrically connected with the second selecting line SL 2 . The second memristor 33 _ 2 may include a phase-changeable memory device such as a phase-changeable random access memory (PCRAM).

The first unit synapse 31 may receive a first row signal, e.g., the first row signal RS 1 illustrated in FIGS. 2A to 2D , from the first row line RL 1 ; and the second unit synapse 32 may receive a second row signal, e.g., the second row signal RS 2 illustrated in FIGS. 2A to 2D , from the second row line RL 2 .

Comparing the synapse 30 b shown in FIG. 3B with the synapse 30 a shown in FIG. 3A , positions of the first memristor 33 _ 1 and the first transistor 35 _ 1 in the first unit synapse 31 may be reversed, and positions of the second memristor 33 _ 2 and the second transistor 35 _ 2 in the second unit synapse 32 may be reversed. Specifically, the drain electrode of the first transistor 35 _ 1 of the first unit synapse 31 may be electrically connected with the first row line RL 1 , the source electrode of the first transistor 35 _ 1 may be electrically connected with the first electrode of the first memristor 33 _ 1 , and the second electrode of the first memristor 33 _ 1 may be electrically connected with the first column line CL 1 . Furthermore, the drain electrode of the second transistor 35 _ 2 of the second unit synapse 32 may be electrically connected with the second row line RL 2 , the source electrode of the second transistor 35 _ 2 may be electrically connected with the first electrode of the second memristor 33 _ 2 , and the second electrode of the second memristor 33 _ 2 may be electrically connected with the second column line CL 2 .

FIG. 4A is a graph schematically illustrating a change in conductivity G of a resistive memory device with respect to a number of pulses applied to the resistive memory device in accordance with an embodiment of the present disclosure.

Referring to FIG. 4A , the resistive memory device may exhibit an abrupt change in conductivity G, in a potentiation operation, that is, a set operation, and a gradual change in conductivity G in a depression operation, that is, a reset operation.

The resistive memory device may exhibit a non-linear change in conductivity G and a non-linear change in resistance in the potentiation operation, and may exhibit a linear change in conductivity G and a linear change in resistance in the depression operation. Accordingly, the resistive memory device can be used as a synapse that can undergo the depression operation, i.e., a depressive synapse.

FIG. 4B is a graph schematically illustrating a change in conductivity G of a phase-changeable memory device with respect to a number of pulses applied to the phase-changeable memory device.

Referring to FIG. 4B , the phase-changeable memory device may exhibit a gradual change in conductivity G in the potentiation operation, that is, the set operation, and an abrupt change in conductivity in the depression operation, that is, the reset operation.

The phase-changeable memory device may have a linear change in conductivity G and a linear change in resistance in the potentiation operation, and may have a non-linear change in conductivity G and a non-linear change in resistance in the depression operation. Accordingly, the phase-changeable memory device can be used as a synapse that can undergo the potentiation operation, i.e., a potentiating synapse.

In some embodiments of the present disclosure, referring to FIGS. 3A and 3B , the first memristor 33 _ 1 of the first unit synapse 31 may include the resistive memory device, and the second memristor 33 _ 2 of the second unit synapse 32 may include the phase-changeable memory device. Accordingly, the conductivity and the resistance of the first memristor 33 _ 1 may change more abruptly than the conductivity and resistance of second memristor 33 _ 2 in the potentiation operation, and conductivity and resistance of the second memristor 33 _ 2 may change more abruptly than the conductivity and resistance changes of the second memristor 33 _ 2 in the depression operation. Accordingly, in an embodiment, a resistance of the first unit synapse 31 changes more abruptly than a resistance of the second unit synapse 32 in the potentiation operation, and the resistance of the second unit synapse 32 changes more abruptly than the resistance of the first unit synapse 31 in the depression operation. In other words, the resistance of the first unit synapse 31 may change more gradually than the resistance of the second unit synapse 32 in the depression operation, and the resistance of the second unit synapse 32 may change more gradually than the resistance of the first unit synapse 31 in the potentiation operation. The synapses 30 a and 30 b in accordance with the embodiments of the present disclosure may include both of the first unit synapse 31 , which includes the resistive memory device, and the second unit synapse 32 , which includes the phase-changeable memory device. According to embodiments of the present disclosure, the first unit synapse 31 of each of the synapses 30 a and 30 b can be used as a depressive synapse by lowering the total resistance level of the synapse 30 a or 30 b in the depression operation. The second unit synapse 32 of each of the synapses 30 a and 30 b can be used as a potentiating synapse by raising the total resistance level of the synapse 30 a or 30 b in the potentiation operation.

FIGS. 5A and 5B are diagrams schematically illustrating post-synaptic neurons 20 a and 20 b of synapse arrays of neuromorphic devices in accordance with embodiments of the present disclosure.

Referring FIG. 5A , a post-synaptic neuron 20 a of a synapse array of a neuromorphic device in accordance with an embodiment of the present disclosure may include a first totalizer 21 , a second totalizer 22 , a normalizer 23 , an integrator 24 , a comparator 25 , a pulse generator 27 , a pulse delay circuit 29 , and a selecting signal delay circuit 49 .

The first totalizer 21 may be disposed on the first column line CL 1 , and the second totalizer 22 may be disposed on the second column line CL 2 . Accordingly, the first totalizer 21 may totalize first synapse weights of first unit synapses, which are electrically connected with the first column line CL 1 , and the second totalizer 22 may totalize second synapse weights of second unit synapses, which are electrically connected with the second column line CL 2 . In an embodiment, the first unit synapses and the second unit synapses may include the first unit synapse 31 and the second unit synapse 32 , respectively, of FIGS. 3A and 3B .

The normalizer 23 may normalize a sum of the first synapse weights and a sum of the second synapse weights and may transmit the normalized synapse weights to the integrator 24 . For example, the normalizer 23 may transmit a total sum of the totalized first synapse weights totalized by the first totalizer 21 and the totalized second synapse weights totalized by the second totalizer 22 , or may transmit an average value of the first synapse weights and the second synapse weights, to the integrator 24 .

The integrator 24 may integrate the normalized synapse weights and transmit the integrated synapse weights to the comparator 25 .

When the integrated synapse weights are greater than a reference voltage, the comparator 25 may output a firing signal.

The pulse generator 27 may output an output signal Pout and a basic selecting signal SS 0 when the pulse generator 27 receives the firing signal from the comparator 25 . Each of the output signal Pout and the basic selecting signal SS 0 may be pulse-shaped. The output signal Pout may be transmitted to a next synapse array or an output device. The basic selecting signal SS 0 may be provided to the pulse delay circuit 29 .

The pulse delay circuit 29 may delay the basic selecting signal SS 0 output from the pulse generator 27 , and may provide the delayed basic selecting signal SS 0 to the first selecting line SL 1 and the second selecting line SL 2 . The pulse delay circuit 29 may include an even number of inverters. In an embodiment, the pulse delay circuit 29 may delay the basic selecting signal SS 0 output from the pulse generator 27 according to a current operation mode of the corresponding synapse array of the neuromorphic device, such as an initializing mode, a potentiation mode, a depression mode, a read-out mode, etc.

The delayed basic selecting signal SS 0 may be divaricated and provided to the first selecting line SL 1 and the second selecting line SL 2 .

The selecting signal delay circuit 49 may be disposed on the second selecting line SL 2 . The selecting signal delay circuit 49 may include an even number of inverters. Accordingly, the selecting signal delay circuit 49 may further delay the delayed basic selecting signal SS 0 , and output the further delayed basic selecting signal SS 0 as a second selecting signal SS 2 . The delayed basic selecting signal SS 0 provided to the first selecting line SL 1 by the pulse delay circuit 29 may be provided as a first selecting signal SS 1 . Accordingly, the second selecting signal SS 2 may be more delayed than the first selecting signal SS 1 . The first selecting signal SS 1 may be applied to gate electrodes of first transistors of the first unit synapses through the first selecting line SL 1 , and the second selecting signal SS 2 may be applied to gate electrodes of second transistors of the second unit synapses through the second selecting line SL 2 . In an embodiment, the first transistors and the second transistors may include the first transistor 35 _ 1 and the second transistor 35 _ 2 , respectively, illustrated in FIGS. 3A and 3B .

Referring to FIG. 5B , a post-synaptic neuron 20 b of a synapse array of a neuromorphic device in accordance with an embodiment of the present disclosure may include a first totalizer 21 , a second totalizer 22 , a normalizer 23 , an integrator 24 , a comparator 25 , a selecting controller 40 , and a selecting signal delay circuit 49 . In comparison with the post-synaptic neuron 20 a shown in FIG. 5A , the post-synaptic neuron 20 b may omit the pulse generator 27 and the pulse delay circuit 29 , and may further include the selecting controller 40 . Portions of the output signal Pout of the comparator 25 may be input to the selecting controller 40 . The selecting controller 40 may generate and delay pulses based on the output signal Pout. For example, the selecting controller 40 may include the pulse generator 27 and the pulse delay circuit 29 shown in FIG. 5A . In another embodiment of the present disclosure, the post-synaptic neuron 20 b may include the pulse generator 27 as illustrated in FIG. 5A . In this embodiment, the selecting controller 40 may be separate from the pulse generator 27 , and portions of the output signal Pout of the pulse generator 27 of FIG. 5A may be input to the selecting controller 40 .

FIG. 6 is a diagram schematically illustrating a synapse array of a neuromorphic device in accordance with an embodiment of the present disclosure. FIG. 7A is a timing diagram schematically illustrating a method for depressing a synapse. FIG. 7B is a timing diagram schematically illustrating a method for potentiating the synapse.

Referring to FIGS. 6 and 7A , the method for depressing the synapse in accordance with an embodiment of the present disclosure may include gradually raising a resistance of a first memristor 33 _ 1 of a first unit synapse 31 by applying reset pulses RESET to the first memristor 33 _ 1 . Specifically, a basic row signal RS 0 generated from a row signal generator 11 may be divaricated into a first row signal RS 1 and a second row signal RS 2 , which are input to the first unit synapse 31 and the second unit synapse 32 , respectively.

The second row signal RS 2 may have an inversed phase and delayed pulse timing with respect to the first row signal RS 1 . The second row signal RS 2 may be delayed with respect to the first row signal RS 1 by a first delay time Δt 1 . The basic row signal RS 0 and the first row signal RS 1 may include a pre-pulse PP and a training pulse TP, and the second row signal RS 2 may include a pre-pulse PP′ and a training pulse TP′. The pre-pulse PP may indicate that the synapse is in an initialized state, or may set a mode of the synapse.

Portions of output signals Pout generated from a pulse generator 27 may be delayed by a pulse delay circuit 29 and provided as a first selecting signal SS 1 on a first selecting line SL 1 and as a second selecting signal SS 2 on a second selecting line SL 2 .

The pulse delay circuit 29 may delay the portions of the output signals Pout by a second delay time Δt 2 . The second delay time Δt 2 may be set so that the training pulses TP of the first row signal RS 1 overlap with pulses of the first selecting signal SS 1 , and so that inverted training pulses TP′ of the second row signal RS 2 do not overlap with pulses of the second selecting signal SS 2 . The second delay time Δt 2 may be controlled by the pulse delay circuit 29 .

The pulse timing of the second selecting signal SS 2 may be delayed with respect to the first selecting signal SS 1 by the selecting signal delay circuit 49 . The second selecting signal SS 2 may be delayed with respect to the first selecting signal SS 1 by a third delay time Δt 3 .

During a depressing time period Δtd, in which the training pulses TP of the first row signals RS 1 and the pulses of the first selecting signal SS 1 overlap each other, the reset pulse RESET can depress the first memristor 33 _ 1 .

Referring to FIGS. 6 and 7B , the method for potentiating the synapse in accordance with an embodiment of the present disclosure may include gradually lowering a resistance of the second memristor 33 _ 2 by applying set pulses SET to the second memristor 33 _ 2 of the second unit synapse 32 .

Portions of the output signals Pout generated from the pulse generator 27 may be delayed by the pulse delay circuit 29 and provided as the first selecting signal SS 1 on the first selecting line SL 1 , and the portions of the output signals Pout further delayed by the third delay time Δt 3 may be provided as the second selecting signal SS 2 on the second selecting line SL 2 . The second delay time Δt 2 and the third delay time Δt 3 may be set so that the inverted training pulses TP′ of the second row signal RS 2 overlaps with pulses of the second selecting signal SS 2 , and so that the training pulses TP of the first row signal RS 1 do not be overlap with pulses of the first selecting signal SS 1 . During a potentiating time period Δtp, in which the inverted training pulses TP′ of the second row pulse RS 1 and the pulses of the second selecting signal SS 2 overlap each other, the set pulse SET can potentiate the second memristor 33 _ 2 .

Referring to FIG. 6 , in the read-out mode, first column signals CS 1 of the first unit synapses 31 and second column signals CS 2 of the second unit synapses 32 may be totalized by a first totalizer 21 and a second totalizer 22 , respectively. A normalizer 23 may generate normalized synapse weights by normalizing the totalized first column signals CS 1 and the totalized second column signals CS 2 . The normalized synapse weights may be provided to an integrator 24 . In the read-out mode, the first row signals RS 1 and the second row signals RS 2 may have the same phase and the same pulse timing.

When polarities of the resistive memory device used as the first memristor 33 _ 1 and the phase-changeable memory device used as the second memristor 33 _ 2 are changed, polarities of the set pulse SET and the reset pulse RESET can be changed. For example, a positive pulse can be changed into a negative pulse, and/or a negative pulse can be changed into a positive pulse.

FIG. 8 is a diagram schematically illustrating a pattern recognition system 900 in accordance with an embodiment of the present disclosure. For example, the pattern recognition system 900 may include any of a speech recognition system, an imaging recognition system, a code recognition system, a signal recognition system, and one or more systems for recognizing various patterns.

Referring to FIG. 8 , the pattern recognition system 900 in accordance with the embodiment of the present disclosure may include a Central Processing Unit (CPU) 910 , a memory unit 920 , a communication control unit 930 , a network 940 , an output unit 950 , an input unit 960 , an Analog-Digital Converter (ADC) 970 , a neuromorphic unit 980 , and/or a bus 990 . The CPU 910 may generate and transmit various signals for a learning process of the neuromorphic unit 980 , and perform various processes and functions for recognizing patterns according to an output from the neuromorphic unit 980 . For example, the CPU 910 may perform processes and functions for recognizing speech and imaging patterns based on the output from the neuromorphic unit 980 .

The CPU 910 may be connected with the memory unit 920 , the communication control unit 930 , the output unit 950 , the ADC 970 , and the neuromorphic unit 980 through the bus 990 .

The memory unit 920 may store various pieces of information, which are stored in the pattern recognition system 900 . The memory unit 920 may include one or more of a volatile memory device, such as a DRAM or SRAM, a nonvolatile memory, such as PRAM, MRAM, ReRAM, or NAND flash memory, and one or more various memory units, such as a Hard Disk Drive (HDD) and a Solid State Drive (SSD).

The communication control unit 930 may transmit and/or receive data to and/or from a communication control unit of another system through the network 940 . For example, the communication control unit 930 may transmit speech and/or image recognition data through the network 940 .

The output unit 950 may output data in various manners. For example, the output unit 950 may include one or more of a speaker, a printer, a monitor, a display panel, a beam projector, a hologrammer, or other various output devices. The output unit 950 may output, for example, speech and/or image recognition data.

The input unit 960 may include one or more of a microphone, a camera, a scanner, a touch pad, a keyboard, a mouse, a mouse pen, or one or more of various sensors.

The ADC 970 may convert analog data inputted from the input unit 960 into digital data.

The neuromorphic unit 980 may perform learning or recognition using the data outputted from the ADC 970 , and output data corresponding to recognized patterns. The neuromorphic unit 980 may include one or more of the neuromorphic devices in accordance with the various embodiments described above.

According to the embodiments of the present disclosure, the synapse includes the dual memristors so that the synapse can have symmetric resistance variations in the potentiation operation and the depression operation.

The foregoing was for illustration of the embodiments only and is not to be construed as limiting thereof. Although a few embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, as defined in the following claims.