Clock signal transmission circuit and driving method thereof, gate driving circuit, and display device

This disclosure claims the benefit of the Chinese patent application 201710066108.4, entitled “Clock Signal Transmission Circuit and Drive Method thereof, Gate Driving Circuit and Display Device,” filed on Feb. 6, 2017, which is hereby incorporated herein by reference.

Embodiments of the present disclosure relate to a display technique, and more particularly to a clock signal transmission circuit and a driving method thereof, a gate driving circuit, and a display device.

When a display unit is switched on, sudden access to a power supply may cause unpredictable voltage fluctuations on some lines. For example, there might have been an undesired high voltage on a clock signal line coupled to a gate driving circuit before the display of an image is started. At this point, the high voltage on the clock signal line may cause a shift register unit (for example, transistors therein) in the gate driving circuit to malfunction. In the case where the gate driving circuit is integrated on an array substrate (GOA), it is difficult to produce additional filtering or protection circuits due to limitations of the manufacturing process. Accordingly, such a case is particularly likely to occur.

When the shift register unit in the gate driving circuit malfunctions, the power supply chip may be readily short-circuited, resulting in a high-current overload. The high-current overload, on the one hand, may readily damage the circuits and shorten the life of the display device and, on the other hand, will lead to a protective shut-down of the power supply chip, so that the display device may present a black screen after its power-on.

Therefore, there is still a need for improvements of an existing display device.

Embodiments of the present disclosure provide a clock signal transmission circuit, a driving method thereof, a gate driving circuit, and a display device.

According to an aspect of the present disclosure, a clock signal transmission circuit is provided, which comprises: an input circuit, a pull-up circuit, a reset circuit, a pull-down control circuit, a pull-down circuit, and a pull-up holding circuit. The input circuit is coupled to an input signal terminal and a pull-up point, and is configured to cause a voltage at the pull-up point to be an enabling voltage under the control of a voltage at the input signal terminal. The pull-up circuit is coupled to the pull-up point, a clock signal terminal and an output signal terminal, and is configured to couple the clock signal terminal to the output signal terminal under the control of a voltage at the pull-up point. The reset circuit is coupled to a reset signal terminal, a first voltage terminal and the pull-up point, and is configured to couple the first voltage terminal to the pull-up point under the control of a voltage at the reset signal terminal. The pull-down control circuit is coupled to the pull-up point, the first voltage terminal, a second voltage terminal and a pull-down point, and is configured to selectively couple one of the first voltage terminal and the second voltage terminal to the pull-down point under the control of a voltage at the pull-up point. The pull-down circuit is coupled to the pull-down point, the first voltage terminal and the output signal terminal, and is configured to couple the first voltage terminal to the output signal terminal under the control of a voltage at the pull-down point. The pull-up holding circuit is coupled to the pull-up point and a third voltage terminal, and is configured to couple the third voltage terminal to the pull-up point under the control of a voltage at the pull-up point.

In an embodiment of the present disclosure, the pull-up holding circuit comprises a first transistor. The first transistor has a control electrode coupled to the pull-up point, a first electrode coupled to the third voltage terminal, and a second electrode coupled to the pull-up point.

In an embodiment of the present disclosure, the pull-up holding circuit is further coupled to the second voltage terminal, and comprises a first transistor, a second transistor, and a third transistor. The first transistor has a control electrode coupled to the pull-up point, a first electrode coupled to the second voltage terminal, and a second electrode coupled to a control electrode of the third transistor. The second transistor has a control electrode and a first electrode coupled to the third voltage terminal, and a second electrode coupled to a first electrode of the third transistor. The third transistor has a second electrode coupled to the pull-up point.

In an embodiment of the present disclosure, the third voltage terminal is coupled to the second voltage terminal.

In an embodiment of the present disclosure, the pull-up holding circuit is further coupled to a fourth voltage terminal, and further comprises: a fourth transistor and a fifth transistor. The fourth transistor has a control electrode and a first electrode coupled to the fourth voltage terminal, and a second electrode coupled to a first electrode of the fifth transistor. The fifth transistor has a control electrode coupled to the second electrode of the first transistor, and a second electrode coupled to the pull-up point.

In an embodiment of the present disclosure, the reset circuit is further coupled to the second electrode of the first transistor, and is further configured to couple the first voltage terminal to the second electrode of the first transistor under the control of a voltage at the reset signal terminal. The reset circuit comprises a sixth transistor and a seventh transistor. The sixth transistor has a control electrode coupled to the reset signal terminal, a first electrode coupled to the pull-up point, and a second electrode coupled to the first voltage terminal. The seventh transistor has a control electrode coupled to the reset signal terminal, a first electrode coupled to the second electrode of the first transistor, and a second electrode coupled to the first voltage terminal.

In an embodiment of the present disclosure, the pull-down circuit is further coupled to the second electrode of the first transistor, and is further configured to couple the first voltage terminal to the second electrode of the first transistor under the control of a voltage at the pull-down point.

In an embodiment of the present disclosure, the pull-down circuit comprises an eighth transistor and a ninth transistor. The eighth transistor has a control electrode coupled to the pull-down point, a first electrode coupled to the second electrode of the first transistor, and a second electrode coupled to the first voltage terminal. The ninth transistor has a control electrode coupled to the pull-down point, a first electrode coupled to the output signal terminal, and a second electrode coupled to the first voltage terminal.

In an embodiment of the present disclosure, the pull-down control circuit comprises a tenth transistor and an eleventh transistor. The tenth transistor has a control electrode coupled to the pull-up point, a first electrode coupled to the pull-down point, and a second electrode coupled to the first voltage terminal. The eleventh transistor has a control electrode and a first electrode coupled to the second voltage terminal, and a second electrode coupled to the pull-down point.

In an embodiment of the present disclosure, the input circuit comprises a twelfth transistor. The twelfth transistor has a control electrode coupled to the input signal terminal, a first electrode coupled to the second voltage terminal, and a second electrode coupled to the pull-up point.

In an embodiment of the present disclosure, the input circuit comprises a twelfth transistor. The twelfth transistor has a control electrode and a first electrode coupled to the input signal terminal, and a second electrode coupled to the pull-up point.

In an embodiment of the present disclosure, the pull-up circuit comprises a thirteenth transistor. The thirteenth transistor has a control electrode coupled to the pull-up point, a first electrode coupled to the clock signal terminal, and a second electrode coupled to the output signal terminal.

According to a second aspect, an embodiment of the present disclosure provides a driving method for the above-mentioned clock signal transmission circuit, comprising: applying an enabling voltage to a reset signal terminal, and applying a disabling voltage to an input signal terminal to cause a voltage at a pull-up point to be a disabling voltage, so that the pull-up circuit decouples a clock signal terminal from an output signal terminal, and the pull-down circuit couples a first voltage terminal to the output signal terminal, wherein the output signal terminal outputs a disabling voltage. An enabling voltage is applied to the input signal terminal, and a disabling voltage is applied to the reset signal terminal to cause a voltage at the pull-up point to be an enabling voltage, so that the pull-up circuit couples the clock signal terminal to the output signal terminal, and the output signal terminal outputs a clock signal from the clock signal terminal, wherein the pull-up holding circuit holds the enabling voltage at the pull-up point.

According to a third aspect, an embodiment of the present disclosure provides a gate driving circuit comprising the above-mentioned clock signal transmission circuit and a plurality of cascaded shift register units. A clock signal source of the gate driving circuit is coupled to the clock signal terminal of the clock signal transmission circuit, and the output signal terminal of the clock signal transmission circuit is coupled to clock signal terminals of the shift register units.

According to a fourth aspect, an embodiment of the present disclosure provides a display device comprising the gate driving circuit mentioned above.

In order to more clearly illustrate the technical solution of embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the drawings described below relate only to some embodiments of the disclosure and are not to be construed as limiting the disclosure, in which:

FIG. 1 is a schematic block diagram of a clock signal transmission circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic circuit diagram of the clock signal transmission circuit shown in FIG. 1 ;

FIG. 3 is another schematic circuit diagram of the clock signal transmission circuit shown in FIG. 1 ;

FIG. 4 is a schematic diagram showing a structure in which a pull-up holding circuit is constituted by one transistor;

FIG. 5 is a schematic diagram showing a structure in which a pull-up holding circuit is constituted by three transistors;

FIG. 6 is another schematic diagram of the input circuit shown in FIG. 1 ;

FIG. 7 is a schematic flow diagram of the driving method for the clock signal transmission circuit shown in FIG. 1 ;

FIG. 8 is a timing diagram of the clock signal transmission circuit of FIG. 7 ; and

FIG. 9 is a schematic diagram of a structure of the gate driving circuit according to an embodiment of the present disclosure.

In order to make the technical solutions and advantages of embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be described clearly and thoroughly below with reference to the accompanying drawings. Obviously, the described embodiments are only parts, rather than all, of embodiments of the present disclosure. All other embodiments which may be obtained by those skilled in the art without any inventive efforts are also within the protection scope of the present disclosure, based on the described embodiments of the disclosure.

In the following description, as the typical understanding of those skilled in the art, an enabling voltage is a voltage applied to a circuit so as to causes the circuit to operate. For example, if the circuit is composed of an N-type transistor, the enabling voltage may be a high voltage that causes the N-type transistor to be turned on when being applied to the gate of the N-type transistor. Correspondingly, if the transistor is of P-type, the enabling voltage is a low voltage that causes the P-type transistor to be turned on when being applied to the gate of the P-type transistor. It should be understood that the words “high” and “low” herein are used only to distinguish relative amplitudes of voltages, rather than specific definitions of these voltages. For example, “high voltage” may be any of 5V, 8V, 30V, etc., while “low voltage” may be any of −5V, −8V, −30V and so on.

In addition, as will be appreciated by those skilled in the art, for a transistor, the control electrode may be the gate, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain.

Additionally, as the typical understanding of those skilled in the art, A is coupled to B means that A is electrically connected to B directly or via an intermediate unit.

FIG. 1 is a schematic block diagram of a clock signal transmission circuit according to an embodiment of the present disclosure. As shown in FIG. 1 , the clock signal transmission circuit comprises an input circuit 1 , a pull-up circuit 2 , a reset circuit 3 , a pull-down control circuit 4 , a pull-down circuit 5 , and a pull-up holding circuit 6 . The input circuit 1 is coupled to an input signal terminal IP and a pull-up point P 1 , and is configured to cause a voltage at the pull-up point P 1 to be an enabling voltage under the control of a voltage at the input signal terminal IP. The pull-up circuit 2 is coupled to the pull-up point P 1 , a clock signal terminal CLK and an output signal terminal OP, and is configured to couple the clock signal terminal CLK to the output signal terminal OP under the control of a voltage at the pull-up point P 1 . The reset circuit 3 is coupled to a reset signal terminal RST, a first voltage terminal V 1 and the pull-up point P 1 , and is configured to couple the first voltage terminal V 1 to the pull-up point P 1 under the control of a voltage at the reset signal terminal RST. The pull-down control circuit 4 is coupled to the pull-up point P 1 , the first voltage terminal V 1 , a second voltage terminal V 2 and a pull-down point P 2 , and is configured to selectively couple one of the first voltage terminal V 1 and the second voltage terminal V 2 to the pull-down point P 2 under the control of a voltage at the pull-up point P 1 . The pull-down circuit 5 is coupled to the pull-down point P 2 , the first voltage terminal V 1 and the output signal terminal OP, and is configured to couple the first voltage terminal V 1 to the output signal terminal OP under the control of a voltage at the pull-down point P 2 . The pull-up holding circuit 6 is coupled to the pull-up point P 1 and a third voltage terminal V 3 , and is configured to couple the third voltage terminal V 3 to the pull-up point P 1 under the control of a voltage at the pull-up point P 1 .

The clock signal transmission circuit may be provided between the clock signal source and each shift register unit of the gate driving circuit, where the clock signal terminal CLK is coupled to the clock signal source, and the output signal terminal OP is coupled to each shift register unit of the gate driving circuit. When the input signal terminal IP is applied with a disabling voltage, a voltage at the pull-up point P 1 remains disabled, and the pull-up circuit 2 causes the clock signal terminal CLK to be disconnected from the output signal terminal OP. Shift register units of the gate driving circuit then will not receive the clock signal in any forms, which can prevent malfunctions of the gate driving circuit caused by an undesired high voltage on the clock signal line. After the input signal terminal IP is applied with an enabling voltage, a voltage at the pull-up point P 1 remains enabled, and the pull-up circuit 2 causes the clock signal terminal CLK to be coupled to the output signal terminal OP. Each shift register unit of the gate driving circuit receives a clock signal from the clock source, and operates normally. By the utilization of the pull-up holding circuit 6 , once the voltage at the pull-up point P 1 is enabled, a third voltage terminal V 3 is coupled to the pull-up point P 1 , and the enabling voltage at the pull-up point P 1 will be maintained. Thereafter, even if the voltage at the input signal terminal IP has been changed to be disabled, the voltage at the pull-up point P 1 can also remain enabled, and the coupling between the clock signal terminal CLK and the output signal terminal OP will be maintained.

According to the clock signal transmission circuit of the embodiment of the present disclosure, it is possible to decouple the clock signal source from shift register units in the gate driving circuit before the display device displays a screen, preventing malfunctions of the gate driving circuit caused by an undesired high voltage on the clock signal line.

FIG. 2 is a schematic flow diagram of the driving method for the clock signal transmission circuit shown in FIG. 1 . As shown in FIG. 2 , the pull-up holding circuit 6 is further coupled to the second voltage terminal V 2 and a fourth voltage terminal V 4 , and the pull-up holding circuit 6 comprises a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , and a fifth transistor M 5 . The first transistor M 1 has a control electrode coupled to the pull-up point P 1 , a first electrode coupled to the second voltage terminal V 2 , and a second electrode P 3 coupled to a control electrode of the third transistor M 3 and a control electrode of the fifth transistor M 5 . The second transistor M 2 has a control electrode and a first electrode coupled to the third voltage terminal V 3 , and a second electrode coupled to a first electrode of the third transistor M 3 . The third transistor M 3 has a second electrode coupled to the pull-up point P 1 . The fourth transistor M 4 has a control electrode and a first electrode coupled to a fourth voltage terminal V 4 , and a second electrode coupled to a first electrode of the fifth transistor M 5 . The fifth transistor M 5 has a control electrode coupled to the second electrode P 3 of the first transistor M 1 , and a second electrode coupled to the pull-up point P 1 .

The enabling voltage at the pull-up point P 1 causes the first transistor M 1 to be turned on to couple the second voltage terminal V 2 to the control electrode of the third transistor M 3 and to the control electrode of the fifth transistor M 5 . The enabling voltage at the second voltage terminal V 2 will cause the third transistor M 3 and the fifth transistor M 5 to turn on. Thereafter, when the voltage at the third voltage terminal V 3 is enabled, the second transistor M 2 is turned on, and the third voltage terminal V 3 is coupled to the pull-up point P 1 via the second transistor M 2 and the third transistor M 3 . When the voltage at the fourth voltage terminal V 4 is enabled, the fourth transistor M 4 is turned on, and the fourth voltage terminal V 4 is coupled to the pull-up point P 1 via the fourth transistor M 4 and the fifth transistor M 5 .

According to the above structure, when the voltage at the second voltage terminal V 2 remains enabled and at least one of the voltage at the third voltage terminal V 3 and the voltage of the fourth voltage terminal V 4 remains enabled, the voltage at the pull-up point P 1 will remain enabled. This is particularly applicable to a gate driving circuit having a plurality of power supplies. In the gate driving circuit, the voltage of one power supply is always enabled and can be connected to the second voltage terminal V 2 ; the voltage of one power supply is always disabled and can be connected to the first voltage terminal V 1 ; and voltages of a pair of power supplies are switched between enabled and disabled, and the voltages of the two power supplies in this pair are always opposite each other (i.e., one is always enabled and the other is always disabled), this pair of power supplies can be connected to the third voltage terminal V 3 and the fourth voltage terminal V 4 , respectively. Thus, the second transistor M 2 and the third transistor M 3 are turned on for a certain period of time, and the fourth transistor M 4 and the fifth transistor M 5 are turned on for the remaining period of time. The alternate turning-on of the transistors can extend their lifetime.

As shown in FIG. 2 , the reset circuit 3 is further coupled to the second electrode P 3 of the first transistor M 1 , and is further configured to couple the first voltage terminal V 1 to the second electrode P 3 of the first transistor M 1 under the control of a voltage at the reset signal terminal RST. The reset circuit 3 comprises a sixth transistor M 6 and a seventh transistor M 7 . The sixth transistor M 6 has a control electrode coupled to the reset signal terminal RST, a first electrode coupled to the pull-up point P 1 , and a second electrode coupled to the first voltage terminal V 1 . The seventh transistor M 7 has a control electrode coupled to the reset signal terminal RST, a first electrode coupled to the second electrode P 3 of the first transistor M 1 , and a second electrode coupled to the first voltage terminal V 1 .

When the voltage at the reset signal terminal RST is enabled, the sixth transistor M 6 is turned on so that the pull-up point P 1 is coupled to the first voltage terminal V 1 and the voltage at the pull-up point P 1 is disabled. The pull-up circuit 2 is turned off, and the clock signal terminal CLK is disconnected from the output signal terminal OP. In addition, the seventh transistor M 7 is turned on, the second electrode P 3 of the first transistor M 1 is coupled to the first voltage terminal V 1 , and the voltage at the second electrode P 3 of the first transistor M 1 is disabled. The third transistor M 3 and the fifth transistor M 5 in the pull-up holding circuit 6 are turned off, disconnecting the third voltage terminal V 3 and the fourth voltage terminal V 4 from the pull-up point P 1 , and ensuring that the voltage of the pull-up point P 1 is disabled. It will be appreciated that the seventh transistor M 7 may also be omitted without affecting the basic functions of the circuit.

As shown in FIG. 2 , in an embodiment of the present disclosure, the pull-down circuit 5 is further coupled to the second electrode P 3 of the first transistor M 1 , and is further configured to couple the first voltage terminal V 1 to the second electrode P 3 of the first transistor M 1 under the control of a voltage at the pull-down point P 2 . The pull-down circuit 5 comprises an eighth transistor M 8 and a ninth transistor M 9 . The eighth transistor M 8 has a control electrode coupled to the pull-down point P 2 , a first electrode coupled to the second electrode P 3 of the first transistor M 1 , and a second electrode coupled to the first voltage terminal V 1 . The ninth transistor M 9 has a control electrode coupled to the pull-down point P 2 , a first electrode coupled to the output signal terminal OP, and a second electrode coupled to the first voltage terminal V 1 . It will be appreciated that the eighth transistor M 8 may also be omitted without affecting the basic functions of the circuit.

When the voltage at the pull-down point P 2 is enabled, the ninth transistor M 9 is turned on and the output signal terminal OP is coupled to the first voltage terminal V 1 . The voltage at the output signal terminal OP remains disabled, so that the output signal terminal OP can be prevented from outputting an undesired voltage (for example, a high voltage). In addition, the eighth transistor M 8 is turned on, the second electrode P 3 of the first transistor M 1 is coupled to the first voltage terminal V 1 , and the voltage at the second electrode P 3 of the first transistor M 1 is disabled. The third transistor M 3 and the fourth transistor M 4 in the pull-up holding circuit 6 are turned off, disconnecting the third voltage terminal V 3 and the fourth voltage terminal V 4 from the pull-up point P 1 . It will be appreciated that the eighth transistor M 8 may also be omitted.

As shown in FIG. 2 , in an embodiment of the present disclosure, the pull-down control circuit 4 comprises a tenth transistor M 10 and an eleventh transistor M 11 . The tenth transistor M 10 has a control electrode coupled to the pull-up point P 1 , a first electrode coupled to the pull-down point P 2 , and a second electrode coupled to the first voltage terminal V 1 . The eleventh transistor M 11 has a control electrode and a first electrode coupled to the second voltage terminal V 2 , and a second electrode coupled to the pull-down point P 2 .

When the voltage at the pull-up point P 1 is disabled, the eleventh transistor M 11 causes the pull-down point P 2 to be coupled to the second voltage terminal V 2 , and the second voltage terminal V 2 supplies an enabling voltage. The voltage at the pull-down point P 2 is enabled, the pull-down circuit 5 causes the output signal terminal OP to be coupled to the first voltage terminal V 1 , and the output signal terminal OP outputs a disabling voltage. Further, the voltage at the pull-up point P 1 is enabled, the tenth transistor M 10 causes the pull-down point P 2 to be coupled to the first voltage terminal V 1 , and the first voltage terminal V 1 supplies a disabling voltage, so that the pull-down circuit 5 causes the output signal terminal OP to be disconnected from the first voltage terminal V 1 , and that the output signal terminal OP outputs the clock signal from the clock signal terminal CLK.

In the above circuit structure, when the pull-down point P 2 is coupled to the first voltage terminal V 1 via the tenth transistor M 10 , it is still coupled to the second voltage terminal V 2 via the eleventh transistor M 11 . In this case, the parameters of the tenth transistor M 10 and the eleventh transistor M 11 (e.g., the breadth-length ratio, etc.) can be set so that the conductivity of the tenth transistor M 10 is higher than that of the eleventh transistor M 11 , thereby the voltage at the pull-down point P 2 is the voltage at the first voltage terminal V 1 . In order to simplify the manufacturing process, the transistors in the circuit may all have the same parameters. In this case, two transistors, which are connected in parallel, can be used as the tenth transistor M 10 to enhance the conductivity, wherein the control electrodes, the first electrodes and the second electrodes of these two transistors are connected correspondingly, and the control is the same as that in the case of one transistor.

As shown in FIG. 2 , in an embodiment of the present disclosure, the input circuit 1 comprises a twelfth transistor M 12 . The twelfth transistor M 12 has a control electrode coupled to the input signal terminal IP, a first electrode coupled to the second voltage terminal V 2 , and a second electrode coupled to the pull-up point P 1 .

When the voltage at the input signal terminal IP is enabled, the twelfth transistor M 12 is turned on so that the second voltage terminal V 2 is coupled to the pull-up point P 1 and the voltage at the pull-up point P 1 is enabled.

As shown in FIG. 2 , in an embodiment of the present disclosure, the pull-up circuit 2 comprises a thirteenth transistor M 13 . The thirteenth transistor M 13 has a control electrode coupled to the pull-up point P 1 , a first electrode coupled to the clock signal terminal CLK, and a second electrode coupled to the output signal terminal OP.

When the voltage at the pull-up point P 1 is enabled, the thirteenth transistor M 13 is turned on so that the clock signal terminal CLK is coupled with the output signal terminal OP, and the output signal terminal OP outputs the clock signal from the clock signal terminal CLK.

The clock signal transmission circuit in the embodiment of the present disclosure can be implemented as a circuit composed of transistors, which facilitates the clock signal transmission circuit to be integrated into an array substrate and formed simultaneously by the process the same as that used for the shift register units in the gate driving circuit, without increasing the cost.

FIG. 3 is a schematic flow diagram of the driving method for the clock signal transmission circuit shown in FIG. 1 . As shown in FIG. 3 , there may be a plurality of clock signal terminals, for example the first clock signal terminal CLK 1 and the second clock signal terminal CLK 2 (and corresponding first output signal terminal OP 1 and second output signal terminal OP 2 ), in a clock signal transmission circuit. FIG. 3 is used to illustrate the case where the shift register units in the gate driving circuit require a plurality of synchronously input clock signals.

Parts of FIG. 3 which are the same as those in FIG. 2 will not be described repeatedly. As shown in FIG. 3 , on the basis of the circuit of FIG. 2 , the pull-up circuit 2 further comprises a fourteenth transistor M 14 . The fourteenth transistor M 14 has a control electrode coupled to the pull-up point P 1 , a first electrode coupled to the second clock signal terminal CLK 2 , and a second electrode coupled to the second output signal terminal OP 2 . During the operation of the clock signal transmission circuit, the state of the fourteenth transistor M 14 is exactly the same as that of the thirteenth transistor M 13 .

The pull-up circuit 2 further comprises a fifth transistor M 15 . The fifth transistor M 15 has a control electrode coupled to the pull-down point P 2 , a first electrode coupled to the second output signal terminal OP 2 , and a second electrode coupled to the first voltage terminal V 1 . During the operation of the clock signal transmission circuit, the state of the fifth transistor M 15 is exactly the same as that of the ninth transistor M 9 .

The clock signal transmission circuit of the embodiment of the present disclosure can be used for synchronously inputting a plurality of clock signals. It will be appreciated that a plurality of circuit structures as shown in FIG. 2 may also be provided to achieve an asynchronous transmission of a plurality of clock signals. Here voltages at the input signal terminals IP of the plurality of clock signal transmission circuits can be changed asynchronously from disabled to enabled in order to achieve an asynchronous transmission of the plurality of clock signals.

FIG. 4 is a schematic diagram showing a structure in which a pull-up holding circuit 6 is constituted by one transistor. As shown in FIG. 4 , the pull-up holding circuit 6 comprises a first transistor M 1 . The first transistor M 1 has a control electrode coupled to the pull-up point P 1 , a first electrode coupled to the third voltage terminal V 3 , and a second electrode coupled to the pull-up point P 1 . This structure is simple and easy to be implemented.

FIG. 5 is a schematic diagram showing a structure in which a pull-up holding circuit 6 is constituted by three transistors. As shown in FIG. 5 , the pull-up holding circuit 6 comprises a first transistor M 1 , a second transistor M 2 , and a third transistor M 3 . The first transistor M 1 has a control electrode coupled to the pull-up point P 1 , a first electrode coupled to the second voltage terminal V 2 , and a second electrode coupled to a control electrode of the third transistor M 3 . The second transistor M 2 has a control electrode and a first electrode coupled to the third voltage terminal V 3 , and a second electrode coupled to a first electrode of the third transistor M 3 . The third transistor M 3 has a second electrode coupled to the pull-up point P 1 . In this structure, two transistors are provided between the pull-up point P 1 and the third voltage terminal V 3 , which may reduce the mutual influence between the voltage of the pull-up point P 1 and the voltage of the third voltage terminal V 3 , and improve the reliability of the circuit.

In the structures of FIGS. 4 and 5 , the voltage at the third voltage terminal V 3 needs to be always enabled, and therefore the third voltage terminal V 3 may also be coupled to the second voltage terminal V 2 to reduce the number of lines, which may improve the reliability and reduce the cost, and is applicable to the gate driving circuits with a small number of power supplies.

FIG. 6 is another schematic diagram of the input circuit 1 shown in FIG. 1 . As shown in FIG. 6 , the input circuit 1 comprises a twelfth transistor M 12 ′. The twelfth transistor M 12 ′ has a control electrode coupled to the input signal terminal IP, a first electrode coupled to the second voltage terminal V 2 , and a second electrode coupled to the pull-up point P 1 . When the enabling voltage required for turning on the twelfth transistor M 12 ′ is the same as the enabling voltage available at the second voltage terminal V 2 (e.g., having the same amplitude), the control electrode and the first electrode of the twelfth transistor M 12 ′ can be coupled to the input signal terminal IP to reduce the number of lines.

FIG. 7 is a schematic flow diagram of the driving method for the clock signal transmission circuit shown in FIG. 1 . FIG. 8 is a timing diagram of the clock signal transmission circuit of FIG. 7 . The operation of the clock signal transmission circuit will be described in detail with reference to FIGS. 2, 7 and 8 , and exemplified by the transistors in FIG. 2 which are of N-type.

As shown in FIG. 8 , the first voltage terminal V 1 is connected to a voltage source which supplies a low voltage, the second voltage terminal V 2 is connected to a voltage source which supplies a high voltage, and the third voltage terminal V 3 and the fourth voltage terminal V 4 are connected to a pair of voltage sources the voltages of which are alternately converted. The clock signal terminals CLK 1 , CLK 2 are connected to corresponding clock sources. In the figure, T 1 shows a blanking stage during which the voltages of the third voltage terminal V 3 and the fourth voltage terminal V 4 are converted. T 2 shows the duration of the enabling voltage at the input signal terminal IP.

As shown in FIG. 7 , the driving method for a clock signal transmission circuit starts at step S 701 , i.e., the reset stage. In the reset stage, an enabling voltage is applied to a reset signal terminal RST, and a disabling voltage is applied to an input signal terminal IP to cause a voltage at a pull-up point P 1 to be a disabling voltage, so that the pull-up circuit 2 decouples a clock signal terminal CLK from an output signal terminal OP, and the pull-down circuit 5 couples a first voltage terminal V 1 to the output signal terminal OP, wherein the output signal terminal OP outputs a disabling voltage. Step S 701 may be performed in any blanking stage T 1 to better match the timing of the screen display. There is no limitation for the duration of the enabling voltage at the reset signal terminal RST, and the enabling voltage at the reset signal terminal RST may be continued until the scan start signal STV used by the gate driving circuit is enabled, so that the shift register units in the gate driving circuit will not receive the clock signal before they start to operate.

Referring to both FIGS. 2 and 8 , specifically, a high voltage at the reset signal terminal RST causes the sixth transistor M 6 and the seventh transistor M 7 to be turned on, so that the pull-up point P 1 is coupled to the first voltage terminal V 1 via the sixth transistor M 6 , and the second electrode P 3 of the first transistor M 1 is coupled to the first voltage terminal V 1 via the seventh transistor M 7 . The low voltage at the first voltage terminal V 1 is applied to the pull-up point P 1 and the second electrode P 3 of the first transistor M 1 . A low voltage at the pull-up point P 1 causes the first transistor M 1 to be turned off, and the low voltage at the second electrode P 3 of the first transistor M 1 causes the third transistor M 3 and the fifth transistor M 5 to be turned off, so that the second voltage terminal V 2 , the third voltage terminal V 3 , and the fourth voltage terminal V 4 are disconnected from the pull-up point P 1 , and the low voltage at the pull-up point P 1 is maintained. The low voltage at the pull-up point P 1 causes the thirteenth transistor M 13 to be turned off, so that the clock signal terminal CLK is disconnected from the output signal terminal OP. The low voltage at the pull-up point P 1 causes the tenth transistor M 10 to be turned off so that the pull-down point P 2 is disconnected from the first voltage terminal V 1 . A high voltage at the second voltage terminal V 2 causes the eleventh transistor M 11 to be turned on, so that the pull-down point P 2 is coupled to the second voltage terminal V 2 via the eleventh transistor M 11 . The high voltage at the second voltage terminal V 2 is applied to the pull-down point P 2 . The high voltage at the pull-down point P 2 causes the eighth transistor M 8 and the ninth transistor M 9 to be turned on, so that the second electrode P 3 of the first transistor M 1 is further coupled to the first voltage terminal V 1 via the eighth transistor M 8 . The output signal terminal OP is coupled to the first voltage terminal V 1 via the ninth transistor M 9 . A low voltage at the first voltage terminal V 1 is applied to the output signal terminal OP, and the output signal terminal OP outputs a low voltage.

In the reset stage, the pull-up point P 1 is coupled to the first voltage terminal V 1 to prevent an abnormal fluctuation of the voltage at the pull-up point P 1 , thereby effectively preventing an abnormal turning-on of the thirteenth transistor M 13 in the pull-up circuit 2 .

Then, the process proceeds to step S 702 , i.e., the clock signal transmission stage. During the clock signal transmission stage, an enabling voltage is applied to the input signal terminal IP, and a disabling voltage is applied to the reset signal terminal RST to cause a voltage at the pull-up point P 1 to be an enabling voltage, so that the pull-up circuit 2 couples the clock signal terminal CLK to the output signal terminal OP, and the output signal terminal OP outputs a clock signal from the clock signal terminal CLK, wherein the pull-up holding circuit 6 holds the enabling voltage at the pull-up point P 1 .

Referring to both FIGS. 2 and 8 , specifically, a high voltage at the input signal terminal IP causes the twelfth transistor M 12 to be turned on, so that the pull-up point P 1 is coupled to the input signal terminal IP via the twelfth transistor M 12 , and the high voltage at the input signal terminal IP is applied to the pull-up point P 1 .

The high voltage at the pull-up point P 1 causes the first transistor M 1 to be turned on and the high voltage at the second voltage terminal V 2 is applied to the second electrode P 3 of the first transistor M 1 , so that the third transistor M 3 and the fifth transistor M 5 are turned on. When the voltage at the third voltage terminal V 3 is high, the second transistor M 2 is turned on, and the pull-up point P 1 is coupled to the third voltage terminal V 3 via the second transistor M 2 and the third transistor M 3 , maintaining the high voltage at the pull-up point P 1 . When the voltage at the fourth voltage terminal V 4 is high, the fourth transistor M 4 is turned on, and the pull-up point P 1 is coupled to the fourth voltage terminal V 4 via the fourth transistor M 4 and the fifth transistor M 5 , maintaining the high voltage at the pull-up point P 1 . Since one of the voltages at the third voltage terminal V 3 and the fourth voltage terminal V 4 will be a high voltage at any time, the high voltage at the pull-up point P 1 can be well maintained.

The high voltage at the pull-up point P 1 causes the thirteenth transistor M 13 to be turned on, so that the output signal terminal OP is coupled to the clock signal terminal CLK via the thirteenth transistor M 13 , and the output signal terminal OP outputs a clock signal.

In addition, the high voltage at the pull-up point P 1 causes the tenth transistor M 10 to be turned on, so that the pull-down point P 2 is coupled to the first voltage terminal V 1 via the tenth transistor M 10 , and coupled to the second voltage terminal V 2 via the eleventh transistor M 11 . As described above, the conductivity of the tenth transistor M 10 may be set to be higher than that of the eleventh transistor M 11 , and then the voltage at the pull-down point P 2 is the low voltage at the first voltage terminal V 1 . The low voltage at the pull-down point P 2 causes the eighth transistor M 8 and the ninth transistor M 9 to be turned off, which disconnects the second electrode P 3 of the first transistor M 1 and the output signal terminal OP from the first voltage terminal V 1 , preventing the low voltage at the first voltage terminal V 1 from affecting the voltage at pull-up point P 1 and the voltage at the output signal terminal OP.

During the clock signal transmission stage, the pull-up point P 1 is stably coupled to the third voltage terminal V 3 or the fourth voltage terminal V 4 to ensure the transmission of the clock signal.

In an embodiment of the present disclosure, the voltage sources to which the first, second, third, and fourth voltage terminals are connected may be voltage sources used by an existing gate driving circuit, which may reduce the number of lines. In addition, there is no limitation in embodiments of the present disclosure for signal sources to which the input signal terminal IP and the reset signal terminal RST are connected, as long as the above timing is satisfied.

For example, FIG. 8 further shows the waveform of the scan start signal STV used by the gate driving circuit, and the input signal terminal IP may also reuse this signal. In this case, when the scan start signal STV has a high voltage, the twelfth transistor M 12 is turned on so that the voltage at the pull-up point P 1 is a high voltage. When the scan start signal STV has a low voltage, the twelfth transistor M 12 is turned off, which disconnects the pull-up point P 1 from the input signal terminal IP.

Further, when the scan start signal STV is reused, as shown in FIG. 6 , one may cause the control electrode of the twelfth transistor M 12 ′ to be coupled to the input signal terminal IP and the first electrode of the twelfth transistor M 12 ′ to be coupled to the second voltage terminal V 2 , which may prevent a potential effect of the voltage at the pull-up point P 1 on the scan start signal STV.

For the reset signal terminal RST, if the existing gate driving circuit uses a signal RTA that is used to reset once all the shift register units before the shift register units start to operate, this signal can also be reused at the reset signal terminal RST.

FIG. 9 is a schematic diagram of a structure of the gate driving circuit according to an embodiment of the present disclosure. As shown in FIG. 9 , the gate driving circuit comprises the above-mentioned clock signal transmission circuit and a plurality of cascaded shift register units. A clock signal source of the gate driving circuit is coupled to the clock signal terminal of the clock signal transmission circuit, and the output signal terminal of the clock signal transmission circuit is coupled to clock signal terminals of the shift register units.

In the gate driving circuit, the clock signal transmission circuit can decouple the clock signal source from each shift register unit in the gate driving circuit before the display device displays a screen, preventing malfunctions of the gate driving circuit caused by an undesired high voltage on the clock signal line.

Furthermore, an embodiment of the present disclosure further provides a display device comprising the gate driving circuit mentioned above. The display device may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

The display device according to the embodiment of the present disclosure can decouple the clock signal source from each shift register unit in the gate driving circuit before a screen is displayed, preventing malfunctions of the gate driving circuit caused by an undesired high voltage on the clock signal line.

It is to be understood that the above embodiments are merely illustrative embodiments for the purpose of illustrating the principles of the disclosure, but the disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and essence of the disclosure, which are also considered to be within the protection scope of the present disclosure.