Stacked semiconductor device

The present application claims priority of Korean Patent Application No. 10-2017-0026018, filed on Feb. 28, 2017, which is herein incorporated by reference in its entirety.

1. Field

Various embodiments relate to a semiconductor design technology, and more particularly, to a stacked semiconductor device with a multi-channel structure.

2. Description of the Related Art

With the rapid development of semiconductor technology, the packaging technology for semiconductor integrated devices has required high integration and high performance. Therefore, a variety of techniques for a three-dimensional (3D) structure in which a plurality of semiconductor chips are vertically stacked have been developed, in addition to a two-dimensional (2D) structure in which semiconductor chips having integrated circuits formed therein are two-dimensionally arranged on a printed circuit board (PCB) through wires or bumps.

Such a 3D structure can be implemented through a stacked semiconductor device in which a plurality of semiconductor chips are vertically stacked. The semiconductor chips stacked in the vertical direction may be mounted on a semiconductor package substrate while being electrically connected to each other through a plurality of through-electrodes, for example, through-silicon vias (TSVs).

In the TSVs, various types of defects may occur. The defects may include a void which occurs when a TSV is not completely filled with a conductive material, a bump contact fail which occurs when a chip is bent or a bump material is moved, and a crack of a TSV. Since the TSVs perform a function of electrically connecting the plurality of chips, the TSVs may not perform a normal function when the TSVs are open in the middle. Therefore, any potential defects of the TSVs need to be detected using a test.

Various embodiments are directed to a stacked semiconductor device with a multi-channel structure, which is capable of verifying whether through-electrodes are operating normally, depending on channel information.

In an embodiment, a stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die, and suitable for communicating with allocated channels through a plurality of through-electrodes. Each of the core dies may include: a through-electrode scan unit enabled according to allocated channel information, and suitable for performing a down scan of transmitting a downward signal and an up scan of transmitting an upward signal, to through-electrodes connected in a column direction among the through-electrodes; and a defect detection unit suitable for detecting whether the through-electrodes have a defect, based on the down scan and the up scan.

In an embodiment, there is provided a stacked semiconductor device including: a plurality of semiconductor chips stacked to transmit signals through a plurality of through-electrodes, and having one or more channels allocated thereto. Each of the semiconductor chips may include: an identification (ID) allocation unit suitable for generating an allocated chip ID signal according to an initial signal; and a test circuit suitable for generating an upper chip enable signal according to the chip ID signal and allocated channel information, performing a test on through-electrodes connected in a column direction among the through-electrodes in response to the upper chip enable signal, and detecting whether the through-electrodes have a defect.

FIG. 1 is a diagram illustrating a semiconductor memory system in accordance with an embodiment of the present invention.

FIG. 2 is a diagram illustrating connections between dies and channels in a stacked memory device of FIG. 1 .

FIG. 3 is a diagram illustrating a stacked memory device in accordance with an embodiment of the present embodiment.

FIGS. 4A to 4D are diagrams for describing scan operations on through-electrodes for respective channels and configurations of through-electrode scan units in the stacked memory device of FIG. 3 .

FIG. 5 is a circuit diagram illustrating a defect detection unit of a base die in FIG. 3 .

FIGS. 6A and 6B are timing diagrams for describing an operation of the stacked memory device of FIG. 3 .

FIG. 7 is a diagram illustrating a stacked memory device in accordance with an embodiment of the present invention.

FIG. 8 is a detailed diagram illustrating an upper chip recognition unit of FIG. 7 .

FIG. 9 is a circuit diagram illustrating a defect detection unit of a base die in FIG. 7 .

FIG. 10A is a block diagram illustrating a control signal generation unit of FIG. 7 .

FIG. 10B is a timing diagram for describing an operation of the control signal generation unit of FIG. 10A .

Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

Hereafter, a semiconductor memory system will be described as an example of a stacked semiconductor device. A semiconductor memory system in accordance with an embodiment may be implemented in the form of a system-in-package (SIP) module, multi-chip-package (MCP) module or system-on-chip (SoC) module, or implemented in the form of a package-on-package (PoP) module including a plurality of packages.

FIG. 1 is a diagram illustrating a semiconductor memory system 100 in accordance with an embodiment of the present invention.

Referring to FIG. 1 , the memory system 100 may include a stacked memory device 110 , a memory controller 120 , an interposer 130 and a package substrate 140 .

The interposer 130 may be formed over the package substrate 140 .

The stacked memory device 110 and the memory controller 120 may be formed over the interposer 130 .

Physical regions PHY of the stacked memory device 110 and the memory controller 120 may be connected through the interposer 130 .

The stacked memory device 110 may include a high bandwidth memory (HBM) in which a plurality of dies or chips are stacked and electrically connected through through-silicon vias (TSVs). The HBM can increase the number of input/output units, thereby raising the bandwidth.

The stacked memory device 110 may include a base die 114 and a plurality of core dies 112 . The core dies 112 may be stacked over the base die 114 , and connected to each other through a plurality of TSVs, for example, two TSVs as illustrated in FIG. 1 . The TSVs will be referred to as through-electrodes.

The core die 112 may include a plurality of memory cells for storing data and circuits for core operations on the memory cells. The base die 114 may include circuits for interfacing the core dies 112 and the memory controller 120 . Thus, the base die 114 may perform various functions in the semiconductor memory system, for example, a memory management function such as a power management or refresh function of the memory cells and a timing adjusting function between the core dies 112 and the memory controller 120 .

The controller die 120 may be or include at least one of a central processing unit (CPU) die, a graphic process unit (GPU) die, a system on chip (SOC) die and the like.

FIG. 2 is a diagram illustrating connections between the dies and channels in the stacked memory device 110 of FIG. 1 .

Referring to FIG. 2 , the plurality of dies may include the base die 114 and the plurality of core dies 112 _ 0 to 112 _ 3 . The plurality of dies may be connected in a column direction through a plurality of through-electrodes formed therein, in order to transmit signals. The through-electrodes formed in each of the dies may be connected to the through-electrodes formed in the upper or lower die through bump pads BP.

In the stacked memory device with a multi-channel structure, each of the core dies 112 _ 0 to 112 _ 3 can communicate with a specific channel depending on a position where the core die is stacked. For this structure, the plurality of through-electrodes formed through each of the core dies 112 _ 0 to 112 _ 3 may be grouped by a predetermined number of through-electrodes, and allocated to the respective channels. Each of the core dies 112 _ 0 to 112 _ 3 may communicate with a corresponding channel through the through-electrodes allocated to the corresponding channel and the base die 114 . For example, the plurality of through-electrodes may be grouped into first-channel through-electrodes TVS 01 to TSV 41 , second-channel through-electrodes TSV 02 to TSV 42 , third-channel through-electrodes TSV 03 to TSV 43 and fourth-channel through-electrodes TSV 04 to TSV 44 . When the first channel CH 0 is allocated to the first core die 112 _ 0 , the first core die 112 _ 0 may communicate with the first channel CH 0 or an external device connected to the first channel CH 0 through the first-channel through-electrodes TSV 01 to TSV 41 . When the third channel CH 2 is allocated to the third core die 112 _ 2 , the third core die 112 _ 2 may communicate with the third channel CH 2 or an external device connected to the third channel CH 2 through the third-channel through-electrodes TSV 03 to TSV 43 .

In the stacked memory device with a multi-channel structure, when a specific channel is selected, the corresponding core die may be enabled, and signals may be transmitted through the through-electrodes allocated to the specific channel. The through-electrodes, indicated by dotted lines, formed in the core dies stacked over the enabled core die may not be used. For example, when the second channel CH 1 is selected, the corresponding second core die 112 _ 1 may be enabled, and signals may be transmitted through the second-channel through-electrodes TSV 02 to TSV 12 , but the through-electrodes TSV 22 to TSV 42 formed in the third and fourth core dies 112 _ 2 and 112 _ 3 may not be actually used. However, since all of the through-electrodes need to guarantee physical connections even though the through-electrodes are not actually used, all of the through-electrodes need to pass a test, for example, an open/short (OS) test. When defects are detected during the OS test which is performed on all through-electrodes connected in the column direction, through-electrodes having defects may be repaired by redundancy through-electrodes RTSV 01 to RTSV 42 .

The number of through-electrodes which are not used may gradually increase toward the upper core dies. Since the OS test does not consider whether through-electrodes are actually used, the OS test cannot screen through-electrodes which are not actually used. Therefore, when a defective through-electrode is detected, the defective through-electrode may be unconditionally repaired. When a large number of defective through-electrodes exceeding the number of redundancy through-electrodes RTSV 01 to RTSV 42 are detected, the corresponding device may be considered and discarded as a fail device, even though the device has no problems in operation.

Hereafter, a method capable of raising the yield of the entire device by performing an OS test on through-electrodes in each core die based on channel information will be described.

FIG. 3 is a diagram illustrating a stacked memory device in accordance with an embodiment of present embodiment. FIG. 3 illustrates components related to the present embodiment.

Referring to FIG. 3 , the stacked memory device may include a base die 210 and a plurality of core dies 220 _ 0 to 220 _ 3 which are stacked over the base die 210 and communicate with channels allocated through a plurality of through-electrodes TSV 0 X to TSV 4 X. FIG. 3 illustrates the through-electrodes TSV 0 X to TSV 4 X connected as one in the column direction. In reality, however, a plurality of through-electrodes may be formed in each of the core dies 220 _ 0 to 220 _ 3 as illustrated in FIG. 2 .

The first to fourth core dies 220 _ 0 to 220 _ 3 may include through-electrode scan units 230 _ 1 to 230 _ 4 and defect detection units 240 _ 1 to 240 _ 4 , respectively.

The through-electrode scan units 230 _ 1 to 230 _ 4 may be enabled according to channel information allocated thereto, and perform a down scan and an up scan on the through-electrodes TSV 0 X to TSV 4 X connected in the column direction among the through-electrodes. The down scan may indicate transmitting a signal in the downward direction, and the up scan may indicate transmitting a signal in the upward direction. The defect detection units 240 _ 1 to 240 _ 4 may detect whether the through-electrodes TSV 0 X to TSV 4 X have defects, based on the down scan and the up scan.

The base die 210 and the first to fourth core dies 220 _ 0 to 220 _ 3 may include identification (ID) allocation units 250 _ 0 to 250 _ 4 for generating chip ID signals SID<0:3><1:0> for the respective core dies, during a boot-up operation or an initial operation. The ID allocation unit 250 _ 0 of the base die 210 may generate an initial ID signal SID<1:0> having an initial value of ‘00’ in response to a reset signal SET, and transmit the initial ID signal SID<1:0> to a separate through-electrode TSVC 0 . The ID allocation units 250 _ 1 to 250 _ 4 of the first to fourth core dies 220 _ 0 to 220 _ 3 may receive the initial ID signal SID<1:0> transmitted through separate through-electrodes TSVC 0 to TSVC 3 from the respective lower dies, and generate the chip ID signals SID<0:3><1:0> which sequentially increase. For example, the first core die 220 _ 0 may generate the chip ID signal SID 0 <1:0> having the same value of ‘00’ as the initial ID signal SID<1:0> of ‘00’, the second core die 220 _ 1 may generate the chip ID signal SID 1 <1:0> of ‘01’ by increasing the chip ID signal SID 0 <1:0> of ‘00’ by 1, the third core die 220 _ 2 may generate the chip ID signal SID 2 <1:0> of ‘10’ by increasing the initial ID signal SID<1:0> by 2, and the fourth core die 220 _ 3 may generate the chip ID signal SID 3 <1:0> of ‘11’ by increasing the initial ID signal SID<1:0> by 3. However, the present embodiment is not limited thereto, but the chip ID signals SID<0:3><1:0> by which the core dies 220 _ 0 to 220 _ 3 can be distinguished may be generated through various methods.

The through-electrode scan units 230 _ 1 to 230 _ 4 may include upper chip recognition units 231 _ 1 to 231 _ 4 , down scan units 232 _ 1 to 232 _ 4 and PM 1 to PM 4 , and up scan units 234 _ 1 to 234 _ 4 and NM 1 to NM 4 , respectively.

The upper chip recognition units 231 _ 1 to 231 _ 4 may generate upper chip enable signals CH_INF 0 to CH_INF 3 by decoding the chip ID signals SID<0:3><1:0> according to channel information allocated thereto.

The down scan units 232 _ 1 to 232 _ 4 and PM 1 to PM 4 may be enabled according to the upper chip enable signals CH_INF 0 to CH_INF 3 , and perform a down scan by flowing a current downward through the through-electrodes TSV 0 X to TSV 4 X connected in the column direction. The down scan units 232 _ 1 to 232 _ 4 and PM 1 to PM 4 may include down scan control units 232 _ 1 to 232 _ 4 and current source units PM 1 to PM 4 , respectively. The down scan control units 232 _ 1 to 232 _ 4 may selectively activate a global down scan signal DN_SCAN to and output local down scan signals DS 1 X to DS 4 X, in response to the upper chip enable signals CH_INF 0 to CH_INF 3 , respectively. The current source units PM 1 to PM 4 may provide a current source to one terminal NO 1 to NO 4 of the through-electrodes TSV 1 X to TSV 4 X in response to the respective local down scan signals DS 1 X to DS 4 X. For reference, since the local down scan signals DS 1 X to DS 4 X are signals for driving the current source units PM 1 to PM 4 implemented with PM 0 S transistors, the local down scan signals DS 1 X to DS 4 X may be activated to a logic low level.

The up scan units 234 _ 1 to 234 _ 4 and NM 1 to NM 4 may be enabled according to the upper chip enable signals CH_INF 0 to CH_INF 3 , and perform an up scan by flowing a current upward through the through-electrodes TSV 0 X to TSV 4 X connected in the column direction. The up scan units 234 _ 1 to 234 _ 4 and NM 1 to NM 4 may include up scan control units 234 _ 1 to 234 _ 4 and current sink units NM 1 to NM 4 , respectively. The up scan control units 234 _ 1 to 234 _ 4 may selectively activate a global up scan signal UP_SCAN to output local up scan signals US 1 X to US 4 X, in response to the upper chip enable signals CH_INF 0 to CH_INF 3 , respectively. The current sink units NM 1 to NM 4 may sink signals transmitted through the terminals NO 1 to NO 4 of the through-electrodes TSV 1 X to TSV 4 X in response to the respective local up scan signals US 1 X to US 4 X. For reference, since the local up scan signals US 1 X to US 4 X are signals for driving the current sink units NM 1 to NM 4 implemented with NM 0 S transistors, the local up scan signals US 1 X to US 4 X may be activated to a logic high level.

The defect detection unit 240 _ 1 to 240 _ 4 may store a down scan result as a first value according to the global down scan signal DN_SCAN and a latch signal LAT, store an up scan result as a second value according to the global up scan signal UP_SCAN and the latch signal LAT, and combine the stored first and second values to generate a fail determination signal FAIL<X> indicating whether the through-electrodes TSV 0 X to TSV 4 X have a defect.

The base die 210 may include a current sink unit NM 0 and a current source unit PM 0 . The current sink unit NM 0 may sink a signal transmitted in the downward direction through one terminal NO 0 of the through-electrode TSV 0 X in response to the global down scan signal DN_SCAN, and the current source unit PM 0 may provide a current source of a signal transmitted in the upward direction to the terminal NO 0 of the through-electrode TSV 0 X in response to the global up scan signal UP_SCAN. For reference, since the global down scan signal DN_SCAN and the global up scan signal UP_SCAN are activated to a logic high level, the base die 210 may include an inverter INV 10 for driving the current source unit PM 0 implemented with a PM 0 S transistor by inverting the global up scan signal UP_SCAN. The base die 210 may include a defect detection unit 240 _ 0 having the same configuration as each of the defect detection units 240 _ 1 to 240 _ 4 of the first to fourth core dies 220 _ 0 to 220 _ 3 .

In the present embodiment, the stacked memory device may decode the chip ID signals SID<0:3><1:0> of the corresponding core dies according to the channel information, and enable only the through-electrode scan unit of the uppermost chip when a specific channel is used. Therefore, only through-electrodes which are actually used during a down scan and an up scan can be tested to remove repair operations caused by defects of through-electrodes and bump pads which are not actually used. Therefore, the yield of the whole semiconductor devices can be increased.

FIGS. 4A to 4D are diagrams for describing scan operations on the through-electrodes for the respective channels and configurations of the through-electrode scan units 230 _ 1 to 230 _ 4 in the stacked memory device of FIG. 3 . In FIGS. 3 to 4D , the same components will be represented by like reference numerals. The ID allocation units 250 _ 0 to 250 _ 4 of FIG. 3 are omitted in FIGS. 4A to 4D for convenience of description.

FIG. 4A illustrates a scan operation on the through-electrodes TSV 01 to TSV 41 for the first channel CH 0 .

Referring to FIG. 4A , the upper chip recognition units 231 _ 1 to 231 _ 4 of the through-electrode scan units ( 230 _ 1 to 230 _ 4 of FIG. 3 ) may include NOR gates NR 11 to NR 41 which perform a NOR operation on the respective chip ID signals SID<0:3><1:0> to output the upper chip enable signals CH_INF 0 to CH_INF 3 , respectively. The down scan control units 232 _ 1 to 232 _ 4 may include NAND gates ND 11 to ND 41 which perform a NAND operation on the upper chip enable signals CH_INF 0 to CH_INF 3 and the global down scan signal DN_SCAN to output the local down scan signals DS 11 to DS 41 , respectively. The up scan control units 234 _ 1 to 234 _ 4 may include AND gates AND 11 to 0 AND 41 which perform an AND operation on the upper chip enable signals CH_INF 0 to CH_INF 3 and the global up scan signal UP_SCAN to output the local up scan signals US 11 to US 41 , respectively.

Therefore, the upper chip recognition unit 231 _ 1 of the first core die 220 _ 0 may receive the chip ID signal SID 0 <1:0> that is, ‘00’ of the first core die 220 _ 0 corresponding to the first channel CH 0 , and generate the upper chip enable signal CH_INF 0 which is activated to a logic high level. When the global down scan signal DN_SCAN or the global up scan signal UP_SCAN is activated to a logic high level, the down scan unit or the up scan unit of the first core die 220 _ 0 may perform a down scan {circle around ( 1 )} or an up scan {circle around ( 2 )} on the through-electrode TSV 01 . Alternately, the upper chip recognition units 231 _ 2 to 231 _ 4 of the other second to fourth core dies 220 _ 1 to 220 _ 3 may generate the upper chip enable signals CH_INF 1 to CH_INF 3 which are deactivated to a logic low level. Thus, the down scan units and the up scan units of the second to fourth core dies 220 _ 1 to 220 _ 3 may not operate even though the global down scan signal DN_SCAN or the global up scan signal UP_SCAN is activated.

Therefore, during the scan operation on the through-electrodes TSV 01 to TSV 41 for the first channel CH 0 , only the through-electrode TSV 01 which is actually used may be tested through an OS test. Thus, since repair operations caused by defects of the bump pads and the through-electrodes TSV 11 to TSV 41 which are not actually used can be removed, the yield of the whole semiconductor devices can be increased.

FIG. 4B illustrates a scan operation on the through-electrodes TSV 02 to TSV 42 for the second channel CH 1 .

Referring to FIG. 4B , the through-electrode scan units may have substantially the same configuration as FIG. 4A , except for the upper chip recognition units 231 _ 1 to 231 _ 4 . The upper chip recognition units 231 _ 1 to 231 _ 4 of FIG. 4B may include inverters INV 12 to INV 42 and NOR gates NR 12 to NR 42 , respectively. The inverters INV 12 to INV 42 may invert first bits SID<0:3><0> of the chip ID signals SID<0:3><1:0>, and the NOR gates NR 12 to NR 42 may perform a NOR operation on output signals of the inverters INV 12 to INV 42 and second bits SID<0:3><1> of the chip ID signals SID<0:3><1:0> to output the upper chip enable signals CH_INF 0 to CH_INF 3 , respectively.

Therefore, the upper chip recognition unit 231 _ 2 of the second core die 220 _ 1 may receive the chip ID signal SID 1 <1:0> that is, ‘01’, of the second core die 220 _ 1 corresponding to the second channel CH 1 , and generate the upper chip enable signal CH_INF 1 which is activated to a logic high level. When the global down scan signal DN_SCAN or the global up scan signal UP_SCAN is activated to a logic high level, the down scan unit or the up scan unit of the second core die 220 _ 1 may perform a down scan {circle around ( 1 )} or an up scan {circle around ( 2 )} on the through-electrodes TSV 02 and TSV 12 . Thus, during the scan operation on the through-electrodes TSV 02 to TSV 42 for the second channel CH 1 , only the through-electrodes TSV 02 and TSV 12 which are actually used may be tested through an OS test.

FIG. 4C illustrates a scan operation on the through-electrodes TSV 03 to TSV 43 for the third channel CH 2 .

Referring to FIG. 4C , the through-electrode scan units may have substantially the same configuration as FIG. 4A , except for the upper chip recognition units 231 _ 1 to 231 _ 4 . The upper chip recognition units 231 _ 1 to 231 _ 4 of FIG. 4C may include inverters INV 13 to INV 43 and NOR gates NR 13 to NR 43 , respectively. The inverters INV 13 to INV 43 may invert second bits SID<0:3><1> of the chip ID signals SID<0:3><1:0>, and the NOR gates NR 13 to NR 43 may perform a NOR operation on output signals of the inverters INV 13 to INV 43 and first bits SID<0:3><0> of the chip ID signals SID<0:3><1:0> to output the upper chip enable signals CH_INF 0 to CH_INF 3 , respectively.

Therefore, the upper chip recognition unit 231 _ 3 of the third core die 220 _ 2 may receive the chip ID signal SID 2 <1:0> that is, ‘10’, of the third core die 220 _ 2 corresponding to the third channel CH 2 , and generate the upper chip enable signal CH_INF 2 which is activated to a logic high level. When the global down scan signal DN_SCAN or the global up scan signal UP_SCAN is activated to a logic high level, the down scan unit or the up scan unit of the third core die 220 _ 2 may perform a down scan {circle around ( 1 )} or an up scan {circle around ( 2 )} on the through-electrodes TSV 03 to TSV 23 . Thus, during the scan operation on the through-electrodes TSV 03 to TSV 43 for the third channel CH 2 , only the through-electrodes TSV 03 to TSV 23 which are actually used may be tested through an OS test.

FIG. 4D illustrates a scan operation on the through-electrodes TSV 04 to TSV 44 for the fourth channel CH 3 .

Referring to FIG. 4D , the through-electrode scan units may have substantially the same configuration as FIG. 4A , except for the upper chip recognition units 231 _ 1 to 231 _ 4 . The upper chip recognition units 231 _ 1 to 231 _ 4 of FIG. 4D may include first inverters INV 141 to INV 441 , second inverters INV 142 to INV 442 , and NOR gates NR 14 to NR 44 , respectively. The first inverters INV 141 to INV 441 may invert first bits SID<0:3><0> of the chip ID signals SID<0:3><1:0>, the second inverters INV 142 to INV 442 may invert second bits SID<0:3><1> of the chip ID signals SID<0:3><1:0>, and the NOR gates NR 14 to NR 44 may perform a NOR operation on output signals of the first inverters INV 141 to INV 441 and output signals of the second inverters INV 142 to INV 442 to output the upper chip enable signals CH_INF 0 to CH_INF 3 , respectively.

Therefore, the upper chip recognition unit 231 _ 4 of the fourth core die 220 _ 3 may receive the chip ID signal SID 2 <1:0> that is, ‘11’, of the fourth core die 220 _ 3 corresponding to the fourth channel CH 3 , and generate the upper chip enable signal CH_INF 3 which is activated to a logic high level. When the global down scan signal DN_SCAN or the global up scan signal UP_SCAN is activated to a logic high level, the down scan unit or the up scan unit of the fourth core die 220 _ 3 may perform a down scan {circle around ( 1 )} or an up scan {circle around ( 2 )} on the through-electrodes TSV 04 to TSV 34 . Thus, during the scan operation on the through-electrodes TSV 04 to TSV 44 for the fourth channel CH 3 , only the through-electrodes TSV 04 to TSV 34 which are actually used may be tested through an OS test.

FIG. 5 is a circuit diagram illustrating the defect detection unit 240 _ 0 of the base die 210 of FIG. 3 . For reference, the defect detection units 240 _ 1 to 240 _ 4 included in the first to fourth core dies 220 _ 0 to 220 _ 3 of FIG. 3 may have substantially the same configuration as the defect detection unit 240 _ 0 of FIG. 5 .

Referring to FIG. 5 , the defect detection unit 240 _ 0 may include a down scan storage unit 310 , an up scan storage unit 320 and a signal generation unit 330 .

The down scan storage unit 310 may store a down scan result as a first value DN_FAIL, according to the global down scan signal DN_SCAN and the latch signal LATCH.

The down scan storage unit 310 may include a first signal transmission unit 312 and a first latch unit 314 . The first signal transmission unit 312 may transmit a signal outputted from one terminal NO 0 of the through-electrode TSV 0 X according to the global down scan signal DN_SCAN and the latch signal LATCH, and the first latch unit 314 may store a signal outputted from the first signal transmission unit 312 as the first value DN_FAIL.

For example, the first signal transmission unit 312 may include a first AND gate AND 1 , a first inverter INV 1 and a first three-phase inverter TRI_INV 1 . The first AND gate AND 1 may perform an AND operation on the global down scan signal DN_SCAN and the latch signal LATCH. The first inverter INV 1 may invert an output of the first AND gate AND 1 . The first three-phase inverter TRI_INV 1 may be enabled according to an output of the first AND gate AND 1 and an output of the first inverter INV 1 , and invert a signal transmitted through the terminal NO 0 of the through-electrode TSV 0 X. The first latch unit 314 may include cross-coupled inverters INV 2 and INV 3 . According to the above-described configuration, the down scan storage unit 310 may store the signal outputted from the terminal NO 0 of the through-electrode TSV 0 X as the first value DN_FAIL, when both the global down scan signal DN_SCAN and the latch signal LATCH are activated.

The up scan storage unit 320 may store an up scan result as a second value UP_FAIL, according to the global up scan signal UP_SCAN and the latch signal LATCH. The up scan storage unit 320 may include a second signal transmission unit 322 and a second latch unit 324 . The second signal transmission unit 322 may transmit a signal outputted from the terminal NO 0 of the through-electrode TSV 0 X according to the global up scan signal UP_SCAN and the latch signal LATCH, and the second latch unit 324 may store a signal outputted from the second signal transmission unit 322 as the second value UP_FAIL. The second signal transmission unit 322 and the second latch unit 324 may have substantially the same configuration as the first signal transmission unit 312 and the first latch unit 314 . According to the above-described configuration, the up scan storage unit 320 may store the signal outputted from the terminal NO 0 of the through-electrode TSV 0 X as the second value UP_FAIL, when both the global up scan signal UP_SCAN and the latch signal LATCH are activated.

The signal generation unit 330 may generate a fail determination signal FAIL<X> by combining the first value DN_FAIL stored in the down scan storage unit 310 and the second value UP_FAIL stored in the up scan storage unit 320 . For example, the signal generation unit 330 may include a NAND gate ND 1 which performs a NAND operation on the first and second values DN_FAIL and UP_FAIL to output the fail determination signal FAIL<X>.

Hereafter, referring to FIGS. 2 to 6B , an operation of the stacked memory device in accordance with the present embodiment will be described.

FIGS. 6A and 6B are timing diagrams for describing an operation of the stacked memory device of FIG. 3 .

FIG. 6A is a timing diagram for describing a scan operation on the through-electrodes TSV 01 to TSV 41 for the first channel CH 0 of FIG. 4A . At this time, suppose that the through-electrode TSV 01 which is actually used has no defects.

Referring to FIG. 6A , when the reset signal SET is activated, the ID allocation units 250 _ 1 to 250 _ 4 of the first to fourth core dies 220 _ 0 to 220 _ 3 may generate the chip ID signals SID<0:3><1:0> which are distinguished from each other.

The upper chip recognition unit 231 _ 1 of the first core die 220 _ 0 may receive the chip ID signal SID 0 <1:0> that is, ‘00’, of the first core die 220 _ 0 corresponding to the first channel CH 0 , and generate the upper chip enable signal CH_INF 0 which is activated to a logic high level.

When the global down scan signal DN_SCAN is activated, the down scan control unit 232 _ 1 of the first core die 220 _ 0 may activate the local down scan signal DS 11 to a logic low level in response to the upper chip enable signal CH_INF 0 , and the current source unit PM 1 may provide a current source to one terminal NO 1 of the through-electrode TSV 11 in response to the local down scan signal DS 11 . Furthermore, the current sink unit NM 0 of the base die 210 may sink a signal transmitted in the downward direction through one terminal NO 0 of the through-electrode TSV 01 in response to the global down scan signal DN_SCAN. Thus, a down scan {circle around ( 1 )} for the through-electrode TSV 01 may be performed. At this time, since the through-electrode TSV 01 has no defects, the defect detection unit 240 _ 0 of the base die 210 may store a high-level signal transmitted through the terminal NO 0 of the through-electrode TSV 01 as the first value DN_FAIL, according to the global down scan signal DN_SCAN and the latch signal LATCH.

When the global up scan signal UP_SCAN is activated, the current source unit PM 0 of the base die 210 may provide a current source of a signal transmitted in the upward direction to the terminal NO 0 of the through-electrode TSV 01 in response to the global up scan signal UP_SCAN. Furthermore, the up scan control unit 234 _ 1 of the first core die 220 _ 0 may activate the local up scan signal US 11 in response to the upper chip enable signal CH_INF 0 , and the current sink unit NM 1 may sink a signal transmitted through the terminal NO 1 of the through-electrode TSV 11 in response to the local up scan signal US 11 . Thus, an up scan {circle around ( 2 )} for the through-electrode TSV 01 may be performed. At this time, since the through-electrode TSV 01 has no defects, the defect detection unit 240 _ 0 of the base die 210 may store a high-level signal transmitted through the terminal NO 0 of the through-electrode TSV 01 as the second value UP_FAIL, according to the global up scan signal UP_SCAN and the latch signal LATCH.

Finally, the defect detection unit 240 _ 0 may generate a fail determination signal FAIL<1> at a logic low level, based on the first and second values DN_FAIL and UP_FAIL at a logic high level. A test device (not illustrated) or a memory controller (not illustrated) may determine that the actually used through-electrode TSV 01 has no defects, based on the low-level fail determination signal FAIL<1>.

In the second to fourth core dies 220 _ 1 to 220 _ 3 , the local down scan signals DS 21 to DS 41 and the local up scan signals US 21 to US 41 may not be activated according to the upper chip enable signals CH_INF 1 to CH_INF 3 which are deactivated to a logic low level, even though the global down scan signal DN_SCAN and the global up scan signal UP_SCAN are activated. Therefore, the down scan units and the up scan units of the second to fourth core dies 220 _ 1 to 220 _ 3 may not operate.

FIG. 6B is a timing diagram for describing a scan operation on the through-electrodes TSV 03 to TSV 43 for the third channel CH 2 of FIG. 4C . As an example, one through-electrode TSV 13 among the through-electrodes TSV 03 to TSV 23 which are actually used, has a defect.

Referring to FIG. 6B , when the reset signal SET is activated and the chip ID signals SID<0:3><1:0> are generated, the upper chip recognition unit 231 _ 3 of the third core die 220 _ 2 may receive the chip ID signal SID 2 <1:0> that is, ‘10’, of the third core die 220 _ 2 corresponding to the third channel CH 2 , and generate the upper chip enable signal CH_INF 2 which is activated to a logic high level.

When the global down scan signal DN_SCAN is activated, the down scan control unit 232 _ 3 of the third core die 220 _ 2 may activate the local down scan signal DS 33 to a logic low level in response to the upper chip enable signal CH_INF 2 , and the current source unit PM 3 may provide a current source to one terminal NO 3 of the through-electrode TSV 33 in response to the local down scan signal DS 33 . Thus, a down scan {circle around ( 1 )} for the through-electrodes TSV 03 to TSV 23 may be performed. At this time, since the through-electrode TSV 13 has a defect, the current source does not transferred to the terminal NO 0 of the through-electrode TSV 03 . Accordingly, the defect detection unit 240 _ 0 may store a low-level signal of the terminal NO 0 of the through-electrode TSV 03 as the first value DN_FAIL, according to the global down scan signal DN_SCAN and the latch signal LATCH.

When the global up scan signal UP_SCAN is activated, the up scan control unit 234 _ 3 of the third core die 220 _ 2 may activate the local up scan signal US 33 in response to the upper chip enable signal CH_INF 0 , and the current sink unit NM 3 may sink the signal transmitted through the terminal NO 3 of the through-electrode TSV 33 in response to the local up scan signal US 33 . Thus, an up scan {circle around ( 2 )} for the through-electrodes TSV 03 to TSV 23 may be performed. The defect detection unit 240 _ 0 may store a high-level signal transmitted through the terminal NO 0 of the through-electrode TSV 03 as the second value UP_FAIL, according to the global up scan signal UP_SCAN and the latch signal LATCH.

Finally, the defect detection unit 240 _ 0 may generate a fail determination signal FAIL<3> at a logic high level, based on the first value DN_FAIL of the low level and the high-level second value UP_FAIL of the high level. The test device (not illustrated) or the memory controller (not illustrated) may determine that the through-electrodes TSV 03 to TSV 23 which are actually used have a defect, based on the high-level fail determination signal FAIL<3>.

In the remaining core dies 220 _ 0 , 220 _ 1 , and 220 _ 3 , the local down scan signals DS 13 , DS 23 and DS 43 and the local up scan signals US 13 , US 23 and US 43 may not be activated according to the upper chip enable signals CH_INF 1 , CH_INF 2 and CH_INF 4 which are deactivated to a logic low level, even though the global down scan signal DN_SCAN and the global up scan signal UP_SCAN are activated. Therefore, the down scan units and the up scan units of the remaining core dies 220 _ 0 , 220 _ 1 , and 220 _ 3 may not operate.

The stacked memory device in accordance with the present embodiment can test only a through-electrode which is actually used among the through-electrodes which are physically connected, and determine whether the through-electrode has a defect. In the following embodiment, a method capable of not only determining whether an actually-used through-electrode has a defect, but also determining where a defect occurred among the through-electrodes included in the core dies will be described.

FIG. 7 is a diagram illustrating a stacked memory device in accordance with an embodiment of the present invention. FIG. 8 is a detailed diagram illustrating an upper chip recognition unit 431 _ 1 of a first core die 420 _ 0 in FIG. 7 .

Referring to FIG. 7 , the stacked memory device may include a base die 410 and a plurality of core dies 420 _ 0 to 420 _ 3 which are stacked over the base die 410 and communicate with a channel allocated through a plurality of through-electrodes TSV 0 X to TSV 4 X. For convenience of description, FIG. 7 illustrates the through-electrodes TSV 0 X to TSV 4 X connected as one in the column direction. In reality, however, a plurality of through-electrodes may be installed in each of the core dies 420 _ 0 to 420 _ 3 as illustrated in FIG. 2 .

The first to fourth core dies 420 _ 0 to 420 _ 3 may include through-electrode scan units 430 _ 1 to 430 _ 4 and defect detection units 440 _ 1 to 440 _ 4 , respectively.

The through-electrode scan units 430 _ 1 to 430 _ 4 may be enabled according to channel information allocated thereto, and perform a down scan and an up scan on the through-electrodes TSV 0 X to TSV 4 X connected in the column direction among the through-electrodes. The down scan may indicate transmitting a signal in the downward direction, and the up scan may indicate transmitting a signal in the upward direction.

The through-electrode scan units 430 _ 1 to 430 _ 4 may include upper chip recognition units 431 _ 1 to 431 _ 4 , down scan units 432 _ 1 to 432 _ 4 and PM 6 to PM 9 , and up scan units 434 _ 1 to 434 _ 4 and NM 6 to NM 9 , respectively.

The upper chip recognition units 431 _ 1 to 431 _ 4 may select one of a plurality of channel enable signals CH_EN<3:0> which are sequentially activated, according to chip ID signals SID<0:3><1:0>, and generate upper chip enable signals CH_INF 0 to CH_INF 3 , respectively. The number of channel enable signals CH_EN<3:0> may correspond to the number of the first to fourth core dies 420 _ 0 to 420 _ 3 . Referring to FIG. 8 , each of the upper chip recognition units 431 _ 1 to 431 _ 4 may include a 4-to-1 multiplexer MUX which selects one of four input signals, and outputs the selected signals as one of the upper chip enable signals CH_INF 0 to CH_INF 3 .

The down scan units 432 _ 1 to 432 _ 4 and PM 6 to PM 9 may be enabled according to the upper chip enable signals CH_INF 0 to CH_INF 3 , and perform a down scan by flowing a current downward through the through-electrodes TSV 0 X to TSV 4 X connected in the column direction. The down scan units 432 _ 1 to 432 _ 4 and PM 6 to PM 9 may include down scan control units 432 _ 1 to 432 _ 4 and current source units PM 6 to PM 9 , respectively. Since the down scan units of FIG. 7 has substantially the same configuration as the down scan units of FIG. 3 , the detailed descriptions thereof are omitted herein.

The up scan units 434 _ 1 to 434 _ 4 and NM 6 to NM 9 may be enabled according to the upper chip enable signals CH_INF 0 to CH_INF 3 , and perform an up scan by flowing a current upward through the through-electrodes TSV 0 X to TSV 4 X connected in the column direction. The up scan units 434 _ 1 to 434 _ 4 and NM 6 to NM 9 may include up scan control units 434 _ 1 to 434 _ 4 and current sink units NM 6 to NM 9 , respectively. Since the up scan units of FIG. 7 has substantially the same configuration as the up scan units of FIG. 3 , the detailed descriptions thereof are omitted herein.

Although not illustrated, the base die 410 and the first to fourth core dies 420 _ 0 to 420 _ 3 may include identification (ID) allocation units that generate the chip ID signals SID<0:3><1:0> for the respective core dies, during a boot-up operation or initial operation. Since the ID allocation units have substantially the same configuration as the ID allocation units 250 _ 0 to 250 _ 4 of FIG. 3 , the detailed descriptions thereof are omitted herein.

The base die 410 may include a current sink unit NMS 5 and a current source unit PM 5 . The current sink unit NM 5 may sink a signal transmitted in the downward direction through one terminal NO 0 of the through-electrode TSV 0 X during a down scan, in response to the global down scan signal DN_SCAN, and the current source unit PM 5 may provide a current source of a signal transmitted in the upward direction to the terminal NO 0 of the through-electrode TSV 0 X during an up scan, in response to the global up scan signal UP_SCAN. For reference, since the global down scan signal DN_SCAN and the global up scan signal UP_SCAN are activated to a logic high level, the base die 210 may include an inverter INV 40 for driving the current source unit PM 5 implemented with a PM 0 S transistor by inverting the global up scan signal UP_SCAN. Furthermore, the base die 410 may include a defect detection unit 440 _ 0 having the same configuration as the defect detection units 440 _ 1 to 440 _ 4 of the first to fourth core dies 420 _ 0 to 420 _ 3 .

Each of the defect detection units 440 _ 0 to 440 _ 4 of the stacked semiconductor device illustrated in FIG. 7 may include a detection unit 442 and a masking unit 444 , respectively. For example, the detection unit 442 442 includes first to fourth sub defect detection units 442 _ 1 to 442 _ 4 corresponding to the first to fourth core dies 420 _ 0 to 420 _ 3 .

The first to fourth sub defect detection units 442 _ 1 to 442 _ 4 may be sequentially enabled according to the first to fourth channel enable signals CH_EN<3:0>, detect whether the through-electrodes TSV 0 X to TSV 4 X have a defect based on the down scan and the up scan, and generate first to fourth fail determination flags FLAG 1 to FLAG 4 . The masking unit 444 may mask the first to fourth fail determination flags FLAG 1 to FLAG 4 in response to a mask signal (CH_MSK<3:0> of FIG. 9 ) which is preset in the mask unit 444 according to the channel information, and output a fail determination signal FAIL<X> indicating whether the through-electrodes TSV 0 X to TSV 4 X have a defect.

The base die 410 may further include a control signal generation unit 460 configured to generate the first to fourth channel enable signals CH_EN<3:0> which are sequentially activated, according to the global down scan signal DN_SCAN and the global up scan signal UP_SCAN.

FIG. 9 is a circuit diagram illustrating the defect detection unit 440 _ 0 of the base die 410 of FIG. 7 . The defect detection units 440 _ 1 to 440 _ 4 included in the first to fourth core dies 420 _ 0 to 420 _ 3 of FIG. 7 may have substantially the same configuration as the defect detection unit 440 _ 0 of FIG. 9 .

Referring to FIG. 9 , the first sub defect detection unit 442 _ 1 may be enabled according to the first channel enable signal CH_EN<0>, store a down scan result transmitted through one terminal NO 0 of the through-electrode TSV 0 X as a first value according to the global down scan signal DN_SCAN and the latch signal LAT, store an up scan result transmitted through the terminal NO 0 of the through-electrode TSV 0 X as a second value according to the global up scan signal UP_SCAN and the latch signal LAT, and combine the stored first and second values to generate and store the first fail determination flag FLAG 1 indicating whether the through-electrodes TSV 0 X to TSV 4 X have a defect. Similarly, the second to fourth sub defect detection units 442 _ 2 to 442 _ 4 may be sequentially enabled according to the second to fourth channel enable signals CH_EN<3:1>, and generate and store the second to fourth fail determination flags FLAG 2 to FLAG 4 . Therefore, a test device (not illustrated) or memory controller (not illustrated) can extract the first to fourth fail determination flags FLAG 1 to FLAG 4 stored in the first to fourth sub defect detection units 442 _ 1 to 442 _ 4 , and recognize where a defect occurred among the through-electrodes included the core dies.

The first to fourth sub defect detection units 442 _ 1 to 442 _ 4 may have substantially the same configuration as the defect detection unit 240 _ 0 of FIG. 5 , except that the first to fourth sub defect detection units 442 _ 1 to 442 _ 4 are sequentially enabled according to the first to fourth channel enable signals CH_EN<3:0>.

The masking unit 444 may include first to fifth NAND gates ND 2 to ND 6 . The first to fourth NAND gates ND 2 to ND 6 may perform a NAND operation on the respective bits of the mask signal CH_MSK<3:0> and the first to fourth fail determination flags FLAG 1 to FLAG 4 , respectively, and the fifth NAND gate ND 6 may perform a NAND operation on outputs of the first to fourth NAND gates ND 2 to ND 5 and output the fail determination signal FAIL<X>. That is, the masking unit 444 may output the fail determination flags FLAG 1 to FLAG 4 corresponding to the respective bits of the mask signal CH_MSK<3:0> having a logic high level as the fail determination signal FAIL<X>.

At this time, the mask signal CH_MSK<3:0> may be preset in the masking unit 444 according to the channel information, and configured as described in Table 1 below. For example, in the case of the through-electrode for the first channel CH 0 , the mask signal CH_MSK<3:0> may be preset to ‘0001’, and the masking unit 444 may output the first fail determination flag FLAG 1 stored in the first sub defect determination unit 442 _ 1 as the fail determination signal FAIL<X>.

FIG. 10A is a block diagram illustrating the control signal generation unit 460 of FIG. 7 .

Referring to FIG. 10A , the control signal generation unit 460 may include a scan enable signal generation unit 462 and a counting unit 464 .

The scan enable signal generation unit 462 may generate a scan enable signal SCAN_EN which is activated according to the global down scan signal DN_SCAN and deactivated according to the global up scan signal UP_SCAN. The counting unit 464 may perform a counting operation on the scan enable signal SCAN_EN, and generate the first to fourth channel enable signals CH_EN<3:0> which are sequentially activated.

The counting unit 464 may include a counter 464 _ 2 and a signal combiner 464 _ 4 .

The counter 464 _ 2 may generate first and second count signals CNT<1:0> by counting the scan enable signal SCAN_EN. The signal combiner 464 _ 4 may generate the first to fourth channel enable signals CH_EN<3:0> by combining logic levels of the first and second count signals CNT<1:0>.

FIG. 10B is a timing diagram for describing an operation of the control signal generation unit 460 of FIG. 7 .

Referring to FIG. 10B , the scan enable signal generation unit 462 may generate the scan enable signal SCAN_EN which is activated in response to a rising edge of the global down scan signal DN_SCAN and deactivated in response to a falling edge of the global up scan signal UP_SCAN.

The counter 464 _ 2 may generate first and second count signals CNT<1:0> by counting the scan enable signal SCAN_EN. The signal combiner 464 _ 4 may generate the first to fourth channel enable signals CH_EN<3:0> by combining the logic levels of the first and second count signals CNT<1:0>.

Therefore, the control signal generation unit 460 may generate the first to fourth channel enable signals CH_EN<3:0> which are sequentially activated, whenever the global down scan signal DN_SCAN and the global up scan signal UP_SCAN are inputted.

The stacked semiconductor device in accordance with the present embodiment may sequentially perform a down scan and an up scan between the first to fourth core dies 420 _ 0 to 420 _ 3 and the base die 410 in response to the first to fourth channel enable signals CH_EN<3:0> which are sequentially activated. For example, when the fourth core die 420 _ 3 is selected in response to the fourth channel enable signal CH_EN<3>, the stacked semiconductor device may perform a down scan and an up scan on the through-electrodes TSV 0 X to TSV 3 X which are actually used, and store the scan results in the fourth sub defect detection unit 442 _ 4 as the fourth fail determination flag FLAG 4 . Then, when the third core die 420 _ 2 is selected in response to the third channel enable signal CH_EN<2>, the stacked semiconductor device may perform a down scan and an up scan on the through-electrodes TSV 0 X to TSV 2 X which are actually used, and store the scan results in the third sub defect detection unit 442 _ 3 as the third fail determination flag FLAG 3 . In this way, the stacked semiconductor device may sequentially and repeatedly perform a down scan and an up scan on the through-electrodes TSV 0 X to TSV 3 X, TSV 0 X to TSV 2 X, TSV 0 X and TSV 1 X, and TSV 0 X, which are actually used when the respective core dies are selected, and store the fail determination flags FLAG 1 to FLAG 4 detected for the respective core dies in the plurality of sub defect detection units 442 _ 1 to 442 _ 4 . Therefore, the stacked semiconductor device may extract the stored values and recognize where a defect occurred among the through-electrodes included in the core dies. Furthermore, the stacked semiconductor device may extract a target value among the stored values according to the channel information, and mask the other values, thereby recognizing whether actually-used through electrodes have a defect.

In accordance with the present embodiment, the stacked semiconductor device can reflect defect information of the through-electrodes according to the channel information of the stacked chips, thereby improving the whole chip yield.

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.