Image processing system and method for an image sensor

1. Field of the Invention

The present invention generally relates to an image sensor, and more particularly to a column-parallel image sensor with improved signal-chain dynamic range.

2. Description of Related Art

An image sensor, such as a complementary metal-oxide-semiconductor (CMOS) image sensor, is a device that converts an optical image into electronic signals. The image sensor has been widely used in a variety of applications such as cell phones and cameras. The CMOS image sensor may be applied to other stringent applications such as automotive and security.

Dark current, however, flows through the photodiode of the CMOS image sensor even when no outside radiation is entering the photodiode. As dark current increases exponentially with the increase of temperature, it becomes a significant source for noise in the image sensor at high temperature, for example, higher than 60° C. As a result, the output image is saturated and cannot be recognized even conventional black level compensation scheme has been adopted.

For the reasons that conventional image sensors could not function effectively at high temperature, a need has arisen to propose a novel image sensor with improved dynamic range in the signal chain, particularly at high temperature.

In view of the foregoing, it is an object of the embodiment of the present invention to provide an image sensor, of which signal-chain dynamic range can be substantially improved at high temperature based on black level estimation.

According to one embodiment, an image processing system for an image sensor includes a pixel array, an analog-to-digital conversion (ADC) unit, a correlated double sampling (CDS) unit, a black level estimation (BLE) unit, and a black level compensation (BLC) unit. The pixel array provides pixel signals, the pixel array including active pixels sensors (APSs), compensating optical black pixels (OBPs) and estimating OBPs. The ADC unit performs analog-to-digital conversion on the pixel signals, thereby generating digital pixel signals. The CDS unit performs correlated double sampling on the digital pixel signals. The BLE unit generates a negative offset voltage according to dark voltage obtained from correlated double sampling performed on the estimating OBPs, the negative offset voltage being subtracted from the pixel signals before feeding the pixel signals to the ADC unit. The BLC performs black level compensation on the APSs and the compensating OBPs.

FIG. 1 shows a block diagram illustrated of a column-parallel image sensor;

FIG. 2 shows a circuit diagram exemplifying the pixel of FIG. 1 ;

FIG. 3 shows an exemplary timing diagram illustrated of correlated double sampling (CDS) performed in the image sensor of FIG. 1 ;

FIG. 4 shows a block diagram illustrated of an image processing system for an image sensor;

FIG. 5 shows another timing diagram illustrated of correlated double sampling (CDS) performed in the image sensor of FIG. 1 ;

FIG. 6 shows a block diagram illustrated of a column-parallel image sensor according to one embodiment of the present invention;

FIG. 7 shows a block diagram illustrated of an image processing system for an image sensor according to one embodiment of the present invention;

FIG. 8 shows an exemplary timing diagram illustrated of correlated double sampling (CDS) performed in the image sensor of FIG. 6 ;

FIG. 9 shows an exemplary circuit diagram illustrated of the offset generator of FIG. 7 ;

FIG. 10A shows an exemplary circuit diagram illustrated of the comparator of FIG. 6 ;

FIG. 10B shows another exemplary circuit diagram illustrated of the comparator of FIG. 6 ; and

FIG. 10C shows a further exemplary circuit diagram illustrated of the comparator of FIG. 6 .

FIG. 1 shows a block diagram illustrated of a column-parallel image sensor 100 , for example, a complementary metal-oxide-semiconductor (CMOS) image sensor. The image sensor 100 may include a pixel array 11 composed of a plurality of pixels 110 arranged in rows and columns. Specifically, the pixel array 11 may include a plurality of active pixel sensors (APSs) 111 and a plurality of optical black pixels (OBPs) 112 . The APSs 111 are configured to receive incident light, while the OBPs 112 are blocked from receiving incident light. The OBPs 112 are utilized for black level compensation (BLC), which will be described in details later in this specification.

FIG. 2 shows a circuit diagram exemplifying the pixel 110 of FIG. 1 . The pixel 110 may include a photodiode PD, a reset transistor RX, a transfer transistor TX, a source follower transistor SF, and a select transistor SX connected as shown in a 4-transistor (4T) architecture. When the reset transistor RX is turned on, a reset voltage is defined at a floating diffusing (FD) node by a power voltage VDD minus a voltage drop across the reset transistor RX. When the transfer transistor TX is turned on, a light signal integrated by the photodiode PD may then be transferred via the FD node. The source follower SF may be activated to buffer or amplify the light signal of the photodiode PD. When the select transistor SX is turned on, a pixel signal may then be read out from the pixel array 11 via a bit line BL.

Referring back to FIG. 1 , the pixel array 11 of the image sensor 100 may include a current sink array 13 that may include a plurality of current sink circuits 131 respectively coupled to output nodes of the select transistors SX as exemplified in FIG. 2 . Specifically, the current sink circuit 131 , such as a current source, is coupled between the output node of the select transistor SX and ground, and is used as a biasing circuit configured to sink a current from the output node of the select transistor SX.

The image sensor 100 may include a row decoder 12 that is configured to select one row of the pixel array 11 at a time such that the pixel signals of the selected row may then be read out.

The image sensor 100 of FIG. 1 may adopt single-slope column-parallel analog-to-digital conversion (ADC) scheme for converting the pixel signals from analog form into digital form. Specifically, the ADC scheme may include a set of comparators 14 , each of which is coupled to receive a corresponding pixel signal from the pixel array 11 and a ramp signal Vramp generated by a ramp generator 15 . The ADC scheme may include a set of counters 16 that are coupled to receive compare results of the comparators 14 , respectively. The counters 16 also receive a counter clock. The ADC scheme may further include a set of memory devices 17 that are coupled to receive counting values of the counters 16 , respectively. The data stored in the memory devices 17 may be processed by a digital image processor (not shown) to accordingly generate a digital image output. The comparator 14 , the counter 16 and the memory device 17 , among others, primarily construct a pixel readout circuit of the signal chain of the image sensor 100 .

FIG. 3 shows an exemplary timing diagram illustrated of correlated double sampling (CDS) performed in the image sensor 100 of FIG. 1 . In a reset period, a reset voltage Vrst at the FD node ( FIG. 2 ) is sampled and fed to a corresponding comparator 16 . When the ramp signal Vramp starts ramping at time t 1 , the counter 16 begins counting. When the comparator 15 detects a crossover point (at time t 2 ) at which the ramp signal Vramp is equal to the pixel signal, the counter 16 stops counting. It is noted that the counting value in the reset period includes (comparator-related) offset voltage and the reset voltage Vrst. It is observed that the reset voltage Vrst is represented by a negative quantity.

In a signal period, a light signal Vsig of the photodiode PD plus the reset voltage Vrst at the FD node is sampled and fed to a corresponding comparator 16 . It is observed that the light signal Vsig is represented by a negative quantity. When the ramp signal Vramp starts ramping at time t 3 , the counter 16 begins counting. When the comparator 15 detects a crossover point (at time t 4 ) at which the ramp signal Vramp is equal to the pixel signal, the counter 16 stops counting. It is noted that the counting value in the signal period includes offset voltage and reset voltage Vrst as in the reset period, and further includes the light signal Vsig corrupted with a dark voltage caused by dark electrons (or dark current) of the photodiode PD.

FIG. 4 shows a block diagram illustrated of an image processing system 400 for an image sensor such as a CMOS image sensor. The image processing system 400 (system 400 hereinafter) may include an ADC unit 41 that is configured to perform analog-to-digital conversion on pixel signals received from a pixel array 11 . The system 400 may include a CDS unit 42 that is configured to perform correlated double sampling (e.g., digital correlated double sampling or DDS) on digital pixel signals generated by the ADC unit 41 , thereby removing unwanted offset voltage and reset voltage to result in a correlated pixel signal. The system 400 may further include a black level compensation (BLC) unit 43 that is configured to remove unwanted dark voltage, thereby resulting in a compensated pixel signal. In an alternative system, the CDS unit 42 precedes the ADC unit 41 in a manner that (analog) correlated double sampling is performed on the pixel signal before executing analog-to-digital conversion.

Specifically speaking, the optical black pixels (OBPs) 112 ( FIG. 1 ) of the pixel array 11 are firstly processed by the ADC unit 41 in the reset period, therefore resulting in a first digital pixel signal composed of offset voltage and reset voltage. Afterwards, the OBPs 112 are processed by the ADC unit 41 in the signal period, therefore resulting in a second digital pixel signal composed of offset voltage, reset voltage and dark voltage. The first digital pixel signal is subtracted from the second digital pixel signal in the CDS unit 42 , therefore resulting in the dark voltage (containing no offset voltage and reset voltage). The resultant dark voltage is then stored temporarily in an OBP sub-unit 431 of the BLC unit 43 .

Similarly, the active pixel sensors (APSs) 111 ( FIG. 1 ) of the pixel array 11 are processed by the ADC unit 41 in the reset period, therefore resulting in a third digital pixel signal composed of offset voltage and reset voltage. Afterwards, the APSs 111 are processed by the ADC unit 41 in the signal period, therefore resulting in a fourth digital pixel signal composed of offset voltage, reset voltage, dark voltage and light signal. The third digital pixel signal is subtracted from the fourth digital pixel signal in the CDS unit 42 , therefore resulting in the dark voltage plus the light signal (containing no offset voltage and reset voltage). The resultant dark voltage plus the light signal is then stored temporarily in an APS sub-unit 432 of the BLC unit 43

Finally, the dark voltage plus the light signal stored in the APS sub-unit 432 subtracts the dark voltage stored in the OBP sub-unit 431 by a subtractor 433 of the BLC unit 43 , therefore resulting in the compensated pixel signal without being corrupted by the dark voltage. The black level compensation may be expressed as follows:

(‘dark+signal’) APS −(‘dark’) OBP =signal

Accordingly, a compensated pixel signal of black color has a value substantially near digital zero. On the contrary, without being subject to black level compensation, a correlated pixel signal of black color may probably look gray. The dark current in the photodiode PD, however, increases exponentially with the increase of temperature.

FIG. 5 shows another timing diagram illustrated of correlated double sampling (CDS) performed in the image sensor 100 of FIG. 1 . It is observed that, at high temperature, the comparator 15 may never detect a crossover point between the ramp signal Vramp and the pixel signal, and the counter 16 may overflow. Moreover, the OBP sub-unit 431 and the APS sub-unit 432 require more storage area or more bits with the increase of temperature. In order to overcome the drawbacks of the system 400 , a novel system has been proposed.

FIG. 6 shows a block diagram illustrated of a column-parallel image sensor 600 (e.g., a CMOS image sensor) according to one embodiment of the present invention. The image sensor 600 may include a pixel array 11 composed of a plurality of pixels 110 arranged in rows and columns. In the embodiment, the pixel array 11 may include a plurality of active pixel sensors (APSs) 111 , a plurality of compensating optical black pixels (OBPs) 112 , and a plurality of estimating OBPs 113 . The APSs 111 are configured to receive incident light, while the compensating OBPs 112 and the estimating OBPs 113 are blocked from receiving incident light. The compensating OBPs 112 are utilized for black level compensation (BLC) as explained above, and the estimating OBPs 113 are utilized for black level estimation (BLE) which will be described in details later in this specification.

Similar to FIG. 1 , the image sensor 600 may include a row decoder 12 that is configured to select one row of the pixel array 11 at a time such that the pixel signals of the selected row may then be read out. The pixel array 11 of the image sensor 600 may also include a current sink array 13 that may include a plurality of current sink circuits 131 respectively coupled to an outputs of the select transistors SX as exemplified in FIG. 2 . Specifically, the current sink circuit 131 , such as a current source, is coupled between the output of the select transistor SX and ground, and is used as a biasing circuit configured to sink a current from the output of the select transistor SX.

The image sensor 600 of the embodiment may adopt single-slope column-parallel analog-to-digital conversion (ADC) scheme for converting the pixel signals from analog form into digital form. Specifically, the ADC scheme may include a set of comparators 14 , each of which is coupled to receive a corresponding pixel signal from the pixel array 11 and a ramp signal Vramp generated by a ramp generator 15 . The ADC scheme may include a set of counters 16 that are coupled to receive compare results of the comparators 14 , respectively. The counters 16 also receive a counter clock. The ADC scheme may include a set of memory devices 17 that are coupled to receive counting values of the counters 16 , respectively. The data stored in the memory devices 17 may be processed by a digital image processor (not shown) to accordingly generate a digital image output.

According to one aspect of the embodiment, the image sensor 600 may include a black level estimation (BLE) unit 18 that is configured to generate a negative offset voltage Neg_offset according to an output of correlated double sampling (CDS), for example, digital correlated double sampling (DDS), performed on the estimating OBPs 113 (by a DDS unit). The negative offset voltage Neg_offset is fed to the comparators 14 for counteracting dark voltage of the pixel signals.

FIG. 7 shows a block diagram illustrated of an image processing system 700 for an image sensor such as a CMOS image sensor according to one embodiment of the present invention. The blocks shown in FIG. 7 may be implemented by hardware (e.g., circuitry) or software (e.g., performed in a digital signal processor). Details of the blocks 11 , 41 , 42 and 43 having been discussed in FIG. 4 are omitted for brevity. In the embodiment, the image processing system 700 (system 700 hereinafter) may include a black level estimation (BLE) unit 18 that is coupled to receive an output of the CDS unit 42 , according to which a negative offset voltage Neg_offset is generated. The generated negative offset voltage Neg_offset is subtracted from the pixel signal (out of the pixel array 11 ) by a subtractor 72 , and an output of the subtractor 72 is then fed to the ADC unit 41 .

Specifically, the BLE unit 18 of the embodiment may include an estimator 181 and an offset generator 182 . In the embodiment, the estimator 181 is a digital circuit or program, and the offset generator 182 is an analog circuit. The estimator 181 is coupled to receive dark voltage obtained from correlated double sampling (CDS) performed on the estimating OBPs 113 , which may be expressed as follows:

BLE:(offset+reset+dark)−(offset+reset)=dark

If the estimator 181 determines that the dark voltage is greater than a predetermined threshold, the estimator 181 activates the offset generator 182 by an offset control signal BLE<M: 0 > in order to generate the (analog) negative offset voltage Neg_offset for use to perform black level compensation on the compensating OBPs 112 and the APSs 111 . Accordingly, the dark voltage in the compensating OBPs 112 and the APSs 111 are substantively counteracted by the amount of Neg_offset. It is appreciated that the generated negative offset voltage Neg_offset may be used for performing black level compensation on a current and succeeding row or rows of the APSs 111 . The BLC unit 43 performs black level compensation as follows:

OBP:(offset+rest+dark−Neg_offset)−(offset+reset)=dark−Neg_offset

APS:(offset+reset+dark+signal−Neg_offset)−(offset+reset)=dark+signal−Neg_offset

BLC:(dark+signal−Neg_offset) APS −(dark−Neg_offset) OBP =signal

FIG. 8 shows an exemplary timing diagram illustrated of correlated double sampling (CDS) performed in the image sensor 600 of FIG. 6 . It is observed that, at high temperature, the dark voltage is substantively counteracted by the negative offset voltage Neg_offset. It is noted that the negative offset voltage Neg_offset is represented by a positive quantity, which is opposite to the light signal Vsig represented by a negative quantity. Accordingly, the comparator 15 may properly detect a crossover point between the ramp signal Vramp and the pixel signal without overflowing the counter 16 . Therefore, storage area or bit number of the OBP sub-unit 431 and the APS sub-unit 432 can be reduced and dynamic range of signal chain can be substantially improved at high temperature.

FIG. 9 shows an exemplary circuit diagram illustrated of the offset generator 182 of FIG. 7 . In the embodiment, the offset generator 182 may include a voltage divider composed of a resistor array R 0 to R N . The voltage divider distributes input voltage VB 1 -VB 2 among the resistors R 0 to R N , therefore generating reference voltages ref 1 to ref N . The offset generator 182 may include a multiplexer 91 that is coupled to receive the reference voltages ref 1 to ref N . The multiplexer 91 selects one of the reference voltages ref 1 to ref N as an output according to selection bits of the offset control signal BLE<M:0>.

The offset generator 182 may include a first switch SW 1 and a second switch SW 2 . The first switch SW 1 is connected between the output of the multiplexer 91 and an input of a buffer 92 . The second switch SW 2 has a first end connected to an input of the buffer, and a second end connected to ground. When performing BLC on the estimating OBPs 113 , the first switch SW 1 is closed and the second switch SW 2 is open, and therefore the multiplexer 91 outputs the selected reference voltage which passes through the buffer 92 as the negative offset voltage Neg_offset. Otherwise, the first switch SW 1 is open and the second switch SW 2 is closed, and therefore the buffer 92 does not generate any negative offset voltage.

FIG. 10A shows an exemplary circuit diagram illustrated of the comparator 14 of FIG. 6 . The comparator 14 may include a differential to single-ended amplifier 141 A such as an operational amplifier. The pixel signal and the negative offset voltage Neg_offset are connected to a non-inverting input of the amplifier 141 A via a first capacitor C 1 and a second capacitor C 2 , respectively. The ramp signal Vramp is connected to an inverting input of the amplifier 141 A. FIG. 10B shows another exemplary circuit diagram illustrated of the comparator 14 of FIG. 6 . The comparator 14 may include a differential to differential amplifier 141 B such as an operational amplifier. The pixel signal and the negative offset voltage Neg_offset are connected to a non-inverting input of the amplifier 141 B via a first capacitor C 1 and a second capacitor C 2 , respectively. The ramp signal Vramp is connected to an inverting input of the amplifier 141 B via a third capacitor C 3 . FIG. 10C shows a further exemplary circuit diagram illustrated of the comparator 14 of FIG. 6 . The comparator 14 may include a single-input to single-output amplifier 141 C such as an operational amplifier. The pixel signal, the negative offset voltage Neg_offset and the ramp signal Vramp are connected to an input of the amplifier 141 C via a first capacitor C 1 , a second capacitor C 2 and a third capacitor C 3 , respectively.

Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.