Multistage noise shaping sigma-delta modulator

This application claims the priority benefit of French patent application number 16/57232, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

The present disclosure relates to the field of analog-to-digital converters, and more particularly, of sigma-delta converters.

A sigma-delta converter conventionally comprises a sigma-delta modulator and a digital filter. The analog signal to be digitized is applied at the modulator input and is sampled by the latter at a relatively high frequency (relative to the maximum frequency of the input signal), called oversampling frequency. The modulator generates, at the oversampling frequency, binary samples representative of the analog input signal. The output bit train of the sigma-delta modulator is processed by the digital filter which extracts therefrom a digital value over N bits (N being the quantization resolution of the sigma-delta converter), representative of the input signal. The number of binary samples, that is, the number of oversampling periods, necessary to generate a digital output value over N bits is designated with acronym OSR, for “Over Sampling Ratio”.

The function of the sigma-delta modulator is to shape, on the one hand, the useful signal by means of its signal transfer function STF and, on the other hand, the quantization noise by means of its noise transfer function NTF. The STF is the transfer function linking the analog input signal to be digitized to the output signal of the modulator, and the NTF is the transfer function linking the quantization noise introduced by modulator to the output signal of the modulator. The NTF enables to reject the quantization noise out of the band of interest (containing the signal). The sigma-delta modulator thus forms a quantization noise shaping stage. The digital filter is designed to extract the signal from frequency bands where the attenuation of the quantization noise by the NTF is high (that is, where the signal is located). The signal transfer function, STF, is generally equal to 1, and the noise transfer function, NTF, is for example expressed, for a modulator of order p, as NTF(z=(1−z −1 )P.

FIG. 1 is a simplified electric diagram illustrating, in the form of blocks, an example of a sigma-delta modulator of order 1 .

The modulator of FIG. 1 comprises an input terminal A 1 intended to receive analog input signal Vin to be digitized, and an output terminal A 2 intended to supply a series of binary samples BS representative of signal Vin. The modulator of FIG. 1 comprises an analog integration circuit 101 , a 1-bit analog-to-digital converter 103 and a feedback loop comprising a 1-bit digital-to-analog converter 105 . Analog integration circuit 101 comprises a first input terminal connected to terminal A 1 of application of signal Vin, and an output terminal A 3 connected to the input of 1-bit analog-to-digital conversion circuit 103 , for example, a comparator. The output of I-bit analog-to-digital converter 103 is connected to output A 2 of the modulator, and is further coupled, via the feedback loop, to a second input terminal A 4 of analog integration circuit 101 . In this example, analog integration circuit 101 comprises a subtractor 107 having its positive input coupled to terminal A 1 of application of signal Vin and having its negative input coupled to output terminal A 4 of the feedback loop, and an analog integrator Ia 1 having its input connected to the output of subtractor 107 and having its output connected to input terminal A 3 of 1-bit analog-to-digital converter 103 .

For each cycle k of duration T OSR of a phase of conversion of analog input signal Vin into a digital output value, where T OSR designates the oversampling period of the converter, k is an integer in the range from 1 to OSR, and OSR is the number of successive cycles of the conversion phase, integration circuit 101 takes an analog sample Vin(k) of the input signal, and the modulator supplies, at the output of 1-bit analog-to-digital converter 103 , a binary sample BS(k) of the output signal. More particularly, in the shown example, for each cycle k, integrator Ia 1 of circuit 101 receives on its input a signal equal to the difference between input signal Vin(k) and feedback signal BS(k−1) (converted to the analog field by 1-bit digital-to-analog converter 105 ). Output value Ia 1 (k) of integrator Ia 1 is accordingly updated, that is, incremented by value Vin(k)−BS(k−1), and then quantized by analog-to-digital converter 103 to provide output sample BS(k).

As a variation, analog integration circuit 101 may comprise a plurality of cascaded analog integrators. It may also comprise one or a plurality of subtractors, one or a plurality of summing circuits, and/or one or a plurality of weighting coefficients. Number p of analog integrators generally defines the order of the sigma-delta modulator. The higher order p of the modulator, the more number OSR of samples necessary to obtain a digital output value over N bits can be decreased (for identical quantization noise levels). On the other hand, sigma-delta modulators are all the more complex to form as their order is high (difficult stabilization).

The digital filter (not shown) of a sigma-delta converter conventionally comprises, according to the modulator structure, one or a plurality of digital integrators (generally at least as many as there are analog integrators in the modulator), for example, counters, and carries out a filtering function intended to extract the useful information from the bit train generated by the sigma-delta modulator.

The forming of sigma-delta modulators having an order greater than 1 is here more particularly considered.

Thus, an embodiment provides a sigma-delta modulator comprising at least first and second sub-modulators, each comprising an analog integration circuit, the analog integration circuit of the first sub-modulator having an output node connected to an input node of the analog integration circuit of the second sub-modulator, the modulator further comprising a coupling capacitor having a first electrode connected to an output node of the analog integration circuit of the second sub-modulator, and a comparator having its input coupled to the first electrode of the coupling capacitor by a first switch and to a second electrode of the coupling capacitor by a second switch.

According to an embodiment, the modulator is capable of implementing a phase of conversion of an analog input signal into an output bit train, the conversion phase comprising a plurality of operating cycles, wherein, for each cycle of the conversion phase, during a first part of the cycle, the first and second switches are respectively off and on, and a binary value Y 1 is read from the comparator output and, during a second part of the cycle, the first and second switches are respectively on and off, and a binary value Y 2 is read from the comparator output, values Y 1 and Y 2 being then combined into an output bit of the modulator.

According to an embodiment, for each cycle of the conversion phase, the analog integration circuit of the second sub-modulator integrates a signal representative of the difference between binary value Y 1 and an output signal of the analog integration circuit of the first sub-modulator.

According to an embodiment, for each cycle of the conversion phase, a feedback signal representative of binary value Y 2 is subtracted from the signal integrated by the analog integration circuit of the second sub-modulator.

According to an embodiment, for each cycle of the conversion phase, the analog integration circuit of the first sub-modulator integrates a signal representative of the analog input signal.

According to an embodiment, for each cycle of the conversion phase, a feedback signal representative of the binary output value of the modulator is subtracted from the signal integrated by the analog integration circuit of the first sub-modulator.

According to an embodiment, the analog integration circuit of the first sub-modulator comprises at least two cascaded analog integrators, and at least one circuit achieving a weighted sum of the output values of said integrators, the output of the summing circuit forming the output of said analog integration circuit.

According to an embodiment, the analog integration circuit of the second sub-modulator comprises a single analog integrator having its input and its output respectively connected to the input and to the output of said analog integration circuit.

The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of dedicated embodiments in connection with the accompanying drawings.

FIG. 1 , previously described, schematically shows an example of a sigma-delta modulator of order 1 ;

FIG. 2 schematically shows an example of a sigma-delta modulator of order 4 ;

FIG. 3 schematically shows in the form of functional blocks an example of a multistage noise shaping sigma-delta modulator;

FIG. 4 is a detailed electric diagram of an example of implementation of the sigma-delta modulator of FIG. 3 ; and

FIG. 5 is a detailed electric diagram illustrating an embodiment of a multistage noise shaping sigma-delta modulator.

The same elements have been designated with the same reference numerals in the different drawings. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the details of the forming of the digital filters of the described sigma-delta converters have not been shown, the forming of such filters being within the abilities of those skilled in the art on reading of the present description. In the present description, term “connected” is used to designate a direct electric connection, with no intermediate electronic component, for example, by means of one or a plurality of conductive tracks or conductive wires, and term “coupled” or term “linked” is used to designate an electric connection which may be direct (then meaning “connected”) or indirect (that is, via one or a plurality of intermediate components).

FIG. 2 schematically illustrates in the form of blocks an example of a sigma-delta modulator of order 4 .

The sigma-delta modulator of FIG. 2 differs from the sigma-delta modulator of FIG. 1 essentially by the architecture of its analog integration circuit 101 . In the example of FIG. 2 , analog integration circuit 101 comprises a subtractor 107 , four cascaded analog integrators Ia 1 , Ia 2 , Ia 3 and Ia 4 , and a summing circuit 109 (Σ). Each analog integrator comprises an input and an output, and for example has a z −1 /(1−z −1 ) transfer function, that is, for each cycle, the integrated signal, or output signal of the integrator, is incremented by the value of the signal applied at the integrator input. In this example, subtractor 107 receives, on its positive input, input signal Vin(k) weighted by a coefficient b 1 and, on its negative input, feedback signal BS(k−1) weighted by a coefficient a 1 . Integrator Ia 1 receives on its input the output signal of subtractor 107 , that is, a signal equal to difference b 1 *Vin(k)−a 1 *BS(k−1). Integrator Ia 2 receives on its input a signal equal to the output signal of integrator Ia 1 weighted by a coefficient c 1 . Integrator Ia 3 receives on its input a signal equal to the output signal of integrator Ia 2 weighted by a coefficient c 2 . Integrator Ia 4 receives on its input a signal equal to the output signal of integrator Ia 3 weighted by a coefficient c 3 . Summing circuit 109 adds input signal Vin(k) weighted by a coefficient b 5 and the output signals of integrators Ia 1 , Ia 2 , Ia 3 , and Ia 4 , respectively weighted by coefficients c 7 , c 6 , c 4 , and c 4 . The output of summing circuit 109 is connected to output terminal A 3 of circuit 101 .

In this example, it is considered that input signal Vin and output signal BS of the modulator are normalized, that is, value 0 of binary signal BS corresponds to a voltage level equal to the smallest value that analog signal Vin can take, and value 1 of signal BS corresponds to a voltage level equal to the greater value that signal Vin can take. Thus, the feedback loop of the modulator is a simple conductive track coupling terminal A 2 to terminal A 4 , and the feedback signal directly is signal BS. In the case where binary output signal BS is not at the same scale as input signal Vin, the feedback loop may comprise, as in the example of FIG. 1 , a 1-bit digital-to-analog converter having its input coupled to terminal A 2 and having its output coupled to terminal A 4 , the feedback signal then being the output signal of the 1-bit digital-to-analog converter.

Many alternative architectures of analog integration circuit 101 can be envisaged. Generally, analog integration circuit 101 of a sigma-delta modulator of order p greater than or equal to 1 may comprise p analog integrators Ia j , j being an integer in the range from 1 to p, each analog integrator Ia j receiving on its input a signal equal to the difference between input signal Vin(k) weighted by a coefficient b j and feedback signal BS(k−1) weighted by a coefficient a j , to which is added, if rank j of integrator Ia j is greater than 1, the output signal of the integrator Ia j−1 of previous rank weighted by a coefficient c j−1 . Summing circuit Σ adds input signal Vin(k) weighted by a coefficient b p+1 , the output signal of integrator Ia p of rank p weighted by a coefficient c p and, if p is greater than 1, the output signal(s) of the integrators of rank p−1, 1 being an integer in the range from 1 to p−1, respectively weighted by coefficients c p+1 . Some of the above-mentioned coefficients may be zero. For example, in the modulator of order 4 of FIG. 2 , coefficients b 2 , b 3 , b 4 , a 2 , a 3 and a 4 are zero, and, in the modulator of order 1 of FIG. 1 , coefficients b 1 , a 1 , and c 1 are unit coefficients, and coefficient b 2 is zero. Further, in the sub-modulator of order 2 MOD 1 of FIG. 3 (which will be described hereafter), coefficients b 1 , a 1 , and c 2 are unit coefficients, and coefficients a 2 , b 2 , and b 3 are zero, and, in the sub-modulator of order 1 MOD 1 of FIG. 3 (which will be described hereafter), coefficients b 1 , a 1 , and c 1 are unit coefficients and coefficient b 2 is zero.

In certain architectures of order p greater than or equal to 1, summing circuit Σ may further receive as an input feedback signal BS(k−1) weighted by a specific weighting coefficient.

Further, the analog integration circuit 101 of a sigma-delta modulator of order p greater than 1 may further comprise one or a plurality of analog feedbacks from the output of an analog integrator to the input of an upstream analog integrator, through a specific weighting coefficient.

Further, in an architecture of order p greater than 1, the output of an integrator of rank i may be added, through a specific weighting coefficient, to the input of a downstream integrator having a rank greater than or equal to i+2.

Further, delays may be introduced between the different stages of circuit 101 , and/or between circuit 101 and converter 103 .

A limitation of the above-mentioned architectures with a single noise shaping stage, that is, comprising a single feedback loop from the output of quantization stage 103 to the input of analog integration circuit 101 , is that the forming of a modulator of high order is in practice complex to implement. In particular, a problem which is posed is that the modulator may have an unstable behavior for certain levels of the input signal.

To overcome this disadvantage, MASH-type (“Multi Stage Noise Shaping”) sigma-delta modulators, that is, modulators of order p greater than 1 formed by the series connection of a plurality of sigma-delta sub-modulators having an order smaller than p, have been provided, where each sub-modulator may have a conventional single-stage noise shaping architecture of the above-described type, that is, comprising an analog integration circuit, a 1-bit analog-to-digital converter, and a feedback loop capable of comprising a digital-to-analog converter. The operating principle of MASH-type sigma-delta modulators is for example described in article “Sturdy MASH Δ-Σ modulator” of Maghari et al. (ELECTRONICS LETTERS 26 Oct. 2006 Vol. 42 No. 22). As an example, a MASH-type sigma-delta modulator of order 2 comprises a first sub-modulator of order 1 , or upstream sub-modulator, for example, of the type described in relation with FIG. 1 , receiving the analog signal to be digitized on its analog input, and a second sub-modulator of order 1 , or downstream sub-modulator, for example, of the type described in relation with FIG. 1 , receiving on its analog input a signal representative of the quantization error of the upstream sub-modulator. During a phase of conversion of the analog input signal into a digital value, each of the sub-modulators of order 1 supplies a train of OSR bits at the output of its 1-bit analog-to-digital converter, the two bit trains being recombined in a single train of OSR bits by a logic recombination circuit. The recombined bit train is digitally integrated by a digital filtering circuit generating a digital output value of the sigma-delta converter. More generally, MASH topologies can be applied whatever the orders of the series-coupled sub-modulators, and whatever the number of series-coupled sub-modulators. The sub-modulators are then coupled so that each sub-modulator of the series association of sub-modulators, except for the first sub-modulator, receives an input signal representative of the quantization error of the previous sub-modulator. An advantage of MASH-type sigma-delta modulators is that they enable to obtain high modulation orders, while doing away with the problems usually encountered (particularly, instability problems) in the forming of conventional sigma-delta modulators (with a single noise shaping stage).

FIG. 3 schematically shows in the form of functional blocks an example of a MASH-type sigma-delta modulator.

In this example, the modulator is of MASH 2-1 type, that is, it comprises a first sigma-delta sub-modulator of order 2 MOD 1 , or upstream sub-modulator, followed by a second sigma-delta sub-modulator of order 1 MOD 2 , of downstream sub-modulator.

Sub-modulator MOD 1 has a conventional topology of order 2 with a single noise shaping stage. It comprises, as in the above-described examples, an analog integration circuit 101 having a first input A 1 intended to receive an analog input signal U to be converted, a 1-bit analog-to-digital converter 103 having its input coupled to an output A 3 of analog integration circuit 101 , and a feedback loop coupling output A 2 of analog-to-digital converter 103 to a second input A 4 of analog integration circuit 101 . In this example, analog integration circuit 101 comprises a subtractor 107 , two analog integrators Ia 1 and Ia 2 , and a summing circuit 109 . The positive input of subtractor 107 is coupled to input A 1 of circuit 101 , and the negative input of subtractor 107 is coupled to input A 4 of circuit 101 . The output of subtractor 107 is coupled to the input of analog integrator Ia 1 , and the output of analog integrator Ia 1 is coupled to the input of analog integrator Ia 2 via a weighting coefficient c 1 . Summing circuit 109 adds output signal O 1 of integrator Ia 1 weighted by a coefficient c 3 to output signal O 2 of integrator Ia 2 , and subtracts from this sum feedback signal Y applied to input A 4 of circuit 101 , weighted by a coefficient d. The output of summing circuit 109 forms the output (terminal A 3 ) of analog integration circuit 101 of sub-modulator MOD 1 , and is coupled to the input of analog-to-digital converter 103 of sub-modulator MOD 1 . In the example of FIG. 3 , 1-bit analog-to-digital converter 103 of sub-modulator MOD 1 is shown in the form of a summing circuit adding to output signal S 1 (terminal A 3 ) of analog integration circuit 101 of sub-modulator MOD 1 a quantization noise E 1 introduced by converter 103 . In this example, each analog integrator Ia i comprises a summing circuit 301 , and a delay operator 303 with a unit gain noted Z −1 . A first input of summing circuit 301 is coupled to the input of the analog integrator, the output of summing circuit 301 being coupled to the input of operator 303 , and the output of operator 303 being coupled, on the one hand, to the output of the analog integrator and, on the other hand, to a second input of summing circuit 301 by a unit-gain positive feedback loop. At each operating cycle k of the sigma-delta converter, summing circuit 301 adds the signal received at cycle k at the input of integrator Ia i and a signal internal to integrator Ia i corresponding to the output signal of operator 301 , that is, to the output value of integrator Ia i at the previous cycle.

Sub-modulator MOD 2 has a conventional topology of order 1 of the type described in relation with FIG. 1 . It comprises an analog integration circuit 101 comprising a first input A 1 receiving an analog signal equal to the difference between output signal Y 1 of analog-to-digital converter 103 of sub-modulator MOD 1 and output signal S 1 of analog integration circuit 101 of sub-modulator MOD 1 , that is, equal to the quantization error E 1 introduced by analog-to-digital converter 103 of sub-modulator MOD 1 . To achieve this, the sigma-delta modulator of FIG. 3 comprises, between sub-modulators MOD 1 and MOD 2 , a subtractor 305 having its positive input coupled to output A 2 of sub-modulator MOD 1 , having its negative input coupled to output A 3 of analog integration circuit 101 of sub-modulator MOD 1 , and having its output coupled to input A 1 of analog integration circuit 101 of sub-modulator MOD 2 . Sub-modulator MOD 2 further comprises a 1-bit analog-to-digital converter 103 having its input connected to an output terminal A 3 of its analog integration circuit 101 , and a feedback loop coupling output A 2 of its analog-to-digital converter 103 to a second input A 4 of its analog integration circuit 101 . In this example, analog integration circuit 101 of sub-modulator MOD 2 comprises a subtractor 107 and an analog integrator Ia 1 . The positive input of subtractor 107 is coupled to input A 1 of circuit 101 , and the negative input of subtractor 107 is coupled to input A 4 of circuit 101 . The output of subtractor 107 is coupled to the input of analog integrator Ia 1 . The output of analog integrator Ia 1 forms output A 3 of analog integration circuit 101 , and is coupled to the input of analog-to-digital converter 103 . Analog integrator Ia 1 of sub-modulator MOD 2 is for example identical or similar to integrator Ia 1 of sub-modulator MOD 1 . In the example of FIG. 3 , 1-bit analog-to-digital converter 103 of sub-modulator MOD 2 is shown in the form of a summing circuit adding to output signal (terminal A 3 ) of analog integration circuit 101 of sub-modulator MOD 2 a quantization noise E 2 .

In the example of FIG. 3 , the sigma-delta modulator further comprises a unit-gain delay operator 307 , noted Z −1 , and a subtractor 309 . The input of operator 307 is coupled to output A 2 of sub-modulator MOD 1 . The positive input of subtractor 309 is coupled to the output of operator 307 . The negative input of subtractor 309 is coupled to output A 2 of sub-modulator MOD 2 . In this example, the output of subtractor 309 forms the output of the sigma-delta modulator. The circuit formed by delay operator 307 and subtractor 309 recombines output bit trains Y 1 of sub-modulator MOD 2 and Y 2 of sub-modulator MOD 2 into an output bit train Y of the sigma-delta modulator, applied to the input of the digital filter (not shown) of the sigma-delta converter.

In the shown example, the feedback loop of sub-modulator MOD 2 is a direct feedback loop, that is, directly coupling (or possibly via a 1-bit digital-to-analog converter) output A 2 of sub-modulator MOD 2 to input A 4 of analog integration circuit 101 of sub-modulator MOD 2 . Conversely, the feedback loop of sub-modulator MOD 1 is an indirect feedback loop, comprising the recombination circuit formed by elements 307 and 309 . In other words, the feedback loop of sub-modulator MOD 1 does not directly couple output A 2 of sub-modulator MOD 1 to input A 4 of analog integration circuit 101 of sub-modulator MOD 1 , but it couples the output of the sigma-delta modulator (that is, the output of subtractor 309 supplying signal Y) to input A 4 of analog integration circuit 101 of sub-modulator MOD 1 (possibly via an analog-to-digital converter, not shown).

The following equations describe the response of the sigma-delta modulator of FIG. 3 :

Y 2= z −1 E 1+(1− z −1 ) E 2

Y ⁢ ⁢ 1 = E ⁢ ⁢ 1 - dY + c ⁢ ⁢ 3 ⁢ z - 1 1 - z - 1 ⁢ ( U - Y ) + c ⁢ ⁢ 1 ⁢ z - 1 ( 1 - z - 1 ) 2 ⁢ ( U - Y ) Y=z −1 Y 1− Y 2

FIG. 4 is a detailed electric diagram of an embodiment of the sigma-delta modulator of FIG. 3 .

In the example of FIG. 4 , each of integrators Ia 1 , respectively Ia 2 , of sub-modulator MOD 1 comprises an operational amplifier AO having its input coupled to the output by an integration capacitor Ci 1 , respectively Ci 2 . The input and the output of the operational amplifier respectively form the input and the output of the integrator. Similarly, integrator Ia 1 of sub-modulator MOD 2 comprises an operational amplifier AO having its input coupled to its output by an integration capacitor Ci 3 . Each integrator further comprises, in parallel with its integration capacitor, a reset switch controlled by a signal Φr. In the present description, for simplification, the switches of the modulator are designated with the same reference numerals as their respective control signals. Thus, although the switches switching the different capacitors of the modulator are different, same designations are used for simultaneously controlled switches.

In this example, each of sub-modulators MOD 1 and MOD 2 comprises an analog integration circuit 101 and a 1-bit analog-to-digital converter 103 formed by a comparator having its input connected to an output terminal A 3 of analog integration circuit 101 of the sub-modulator, and having its output connected to an output terminal A 2 of the sub-modulator. In operation, an internal signal of each comparator switches from a high state to a low state according to whether the input signal of the comparator is higher or lower than a threshold, for example, equal to a reference potential applied to a reference node R of the circuit. The internal signal of the comparator is copied on its output terminal A 2 at each rising or falling edge of a control signal Φcomp.

In sub-modulator MOD 1 , the analog integration circuit 101 is formed as follows. The output of integrator Ia 1 is coupled to a first electrode of a capacitor C 2 by a first switch Φ 1 d , and the output of integrator Ia 2 is coupled to a first electrode of a capacitor C 3 by a first switch Φ 2 d . The second electrode of capacitor C 2 is coupled to the input of integrator Ia 2 by a first switch Φ 2 , and the second electrode of capacitor C 3 is coupled to output terminal A 3 of circuit 101 by a second switch Φ 2 . The first and second electrodes of capacitor C 2 are further coupled to a node R of application of a reference potential, respectively via a second switch Φ 2 d and via a first switch Φ 1 . Further, the first and second electrodes of capacitor C 3 are coupled to node R respectively via a second switch Φ 1 d and via a second switch Φ 1 . Analog integration circuit 101 of sub-modulator MOD 1 further comprises a capacitor C 1 having a first electrode coupled to input terminal A 1 of the sub-modulator by a third switch Φ 1 d and having its second electrode coupled to the input of integrator Ia 1 by a third switch Φ 2 . The first and second electrodes of capacitor C 1 are further respectively coupled to a node N 1 receiving output signal Y of the modulator by a third switch Φ 2 d and to node R by a third switch Φ 1 . Analog integration circuit 101 of sub-modulator MOD 1 further comprises a capacitor C 4 having a first electrode coupled to the output of integrator Ia 1 by a fourth switch Φ 2 d and having its second electrode coupled to output terminal A 3 of circuit 101 by a fourth switch Φ 2 . The first and second electrodes of capacitor C 4 are further coupled to node R respectively by a fourth switch Φ 1 d and by a fourth switch Φ 1 . Analog integration circuit 101 of sub-modulator MOD 1 further comprises a capacitor C 5 having a first electrode coupled to node N 2 receiving output signal Y 2 of sub-modulator MOD 2 via a fifth switch Φ 2 d and having a second electrode coupled to output terminal A 3 of circuit 101 by a fifth switch Φ 2 . The first and second electrodes of capacitor C 5 are further respectively coupled to a node N 3 receiving output signal Y 1 of sub-modulator MOD 1 via a fifth switch Φ 1 d and to node R via a fifth switch Φ 1 .

The circuit formed by capacitors C 4 , C 3 , and C 5 and by the switches Φ 2 d , Φ 1 d , Φ 1 , Φ 2 associated with these capacitors is duplicated at the input of the analog integrator Ia 1 of sub-modulator MOD 2 . In other words, in addition to its analog integrator Ia 1 , analog integration circuit 101 of sub-modulator MOD 2 comprises: a capacitor C 3 ′ substantially identical to capacitor C 3 (to within manufacturing dispersions) having a first electrode coupled to the output of integrator Ia 2 of sub-modulator MOD 1 by a sixth switch Φ 2 d and having its second electrode coupled to the input of integrator Ia 1 of sub-modulator MOD 2 by a sixth switch Φ 2 , the first and second electrodes of capacitor C 3 ′ being further coupled to node R respectively by a sixth switch Φ 1 d and by a sixth switch Φ 1 ; a capacitor C 4 ′ substantially identical to capacitor C 4 (to within manufacturing dispersions) having a first electrode coupled to the output of integrator Ia 1 of sub-modulator MOD 1 by a seventh switch Φ 2 d and having its second electrode coupled to the input of integrator Ia 1 of sub-modulator MOD 2 by a seventh switch Φ 2 , the first and second electrodes of capacitor C 4 ′ being further coupled to node R respectively by a seventh switch Φ 1 d and by a seventh switch Φ 1 ; and a capacitor C 5 ′ substantially identical to capacitor C 5 (to within manufacturing dispersions) having a first electrode coupled to node N 2 by an eighth switch Φ 2 d and having its second electrode coupled to the input of integrator Ia 1 of sub-modulator MOD 2 by an eighth switch Φ 2 , the first and second electrodes of capacitor C 5 ′ being further respectively coupled to node N 3 by an eighth switch Φ 1 d and to node R by an eighth switch Φ 1 .

Analog integration circuit 101 of sub-modulator MOD 2 further comprises a capacitor C 6 having a first electrode coupled to a node N 4 receiving a signal Y 1 complementary to output signal Y 1 of sub-modulator MOD 1 via a ninth switch Φ 1 d (node N 4 is for example coupled to node N 3 by an inverter) and having its second electrode coupled to the input of integrator Ia 1 of sub-modulator MOD 2 by a ninth switch Φ 1 . The first and second electrodes of capacitor C 6 are further respectively coupled to a node N 5 receiving a signal Y 2 complementary to output signal Y 2 of sub-modulator MOD 2 via a ninth switch Φ 2 d (node N 5 is for example coupled to node N 2 by an inverter) and to node R by a ninth switch Φ 2 .

In this example, the output of integrator Ia 1 of sub-modulator MOD 2 is connected to output terminal A 3 of analog integration circuit 101 of sub-modulator MOD 2 .

The sigma-delta modulator of FIG. 4 further comprises a logic circuit 401 (LOGIC) comprising two binary inputs respectively coupled to output terminal A 2 of 1-bit analog-to-digital converter 103 of sub-modulator MOD 1 and to output terminal A 2 of 1-bit analog-to-digital converter 103 of sub-modulator MOD 2 , and three binary outputs respectively coupled to nodes N 1 , N 2 , and N 3 and supplying binary output signal Y 1 of sub-modulator MOD 1 , binary output signal Y 2 of sub-modulator MOD 2 , and the binary output signal Y of the modulator.

A timing diagram is shown in FIG. 4 to show the chaining in a cycle of two successive switching phases P 1 and P 2 of the modulator switches. During phase P 1 , switches Φ 2 and Φ 2 d are turned on (made conductive), switches Φ 1 and Φ 1 d being kept off (non-conductive). At the end of phase P 1 , switches Φ 2 and Φ 2 d are turned off. During phase P 2 , switches Φ 1 and Φ 1 d are turned on (made conductive), switches Φ 2 and Φ 2 d being kept off (non-conductive). At the end of phase P 2 , switches Φ 1 and Φ 1 d are turned off. At the end of each of phases P 1 and P 2 , the internal signal of comparators 103 of sub-modulators MOD 1 and MOD 2 is sampled (rising edges of signal Φcomp) to generate signals Y 1 and Y 2 .

In the embodiment of FIG. 4 , the function of summing circuit 109 of FIG. 3 is implemented on the one hand by capacitors C 4 , C 3 , and C 5 and the switches connected to these capacitors, and on the other hand by capacitors C 4 ′, C 3 ′, and C 5 ′ and the switches connected to these capacitors.

At each cycle k of a phase of conversion of analog input signal U into a digital value, during phase P 1 , a signal S 1 resulting from the weighted sum of output signal O 1 of integrator Ia 1 , of output signal O 2 of integrator Ia 2 , and of output signal Y of the sigma-delta modulator, is generated on input node A 3 of analog-to-digital converter 103 of sub-modulator MOD 1 , with S 1 =−(O 2 +c 3 *O 1 −d*Y), coefficients c 3 and d being respectively set by the ratio of capacitances C 3 and C 4 and the ratio of capacitances C 5 and C 3 . It should be noted that in this example, signal Y(k)=Y 1 ( k −1)−Y 2 ( k ) is not directly applied to the input of the summing circuit, but is generated again by the latter in capacitor C 5 , based on signals Y 1 and Y 2 . At the end of phase P 1 , signal S 1 is quantized by comparator 103 of sub-modulator MOD 1 to generate signal Y 1 . In parallel, during phase P 1 , signal S 1 is further generated on the input node of integrator Ia 1 of sub-modulator MOD 2 by the duplicated summing circuit comprising capacitors C 4 ′, C 3 ′, and C 5 ′ and the switches connected to these capacitors. The value of signal S 1 thus adds to the output value of integrator Ia 1 of sub-modulator MOD 2 .

During phase P 2 following phase P 1 , signal Y 1 is applied to the input of integrator Ia 1 of sub-modulator MOD 2 . Thus, at the end of the cycle, the output value of integrator Ia 1 of sub-modulator MOD 2 has effectively been increased by a value corresponding to quantization noise E 1 of analog-to-digital converter 103 of sub-modulator MOD 1 (from which feedback signal Y 2 of sub-modulator MOD 2 due to the precharging of capacitor C 6 to potential − Y 2 during phase P 1 is subtracted).

In the example of FIG. 4 , the function of subtractor circuit 107 of sub-modulator MOD 1 of FIG. 3 is implemented by capacitor C 1 and the switches associated with this capacitor, and the function of subtractor circuit 107 of sub-modulator MOD 2 of FIG. 3 is implemented by capacitor C 6 and the switches associated with this capacitor.

A disadvantage of the architecture of FIG. 4 is the hardware cost due to the duplicating, at the input of sub-modulator MOD 2 , of the capacitors of the summing circuit used in sub-modulator MOD 1 to generate output signal S 1 of analog integration circuit 101 of sub-modulator MOD 1 . Another disadvantage is due to the matching, which is inevitably imperfect, of the duplicated capacitors, which results in introducing an additional component of quantization noise E 1 in the expression of output signal Y of the modulator.

FIG. 5 is a detailed electric diagram illustrating an embodiment of a multistage noise shaping sigma-delta modulator.

Functionally, the sigma-delta modulator of FIG. 5 is a MASH 2-I-type modulator identical or similar to the modulator of FIG. 3 .

Structurally, the sigma-delta modulator of FIG. 5 comprises elements common with the sigma-delta modulator of FIG. 4 . Only the differences between the two embodiments will be detailed hereafter.

Analog integration circuit 101 of sub-modulator MOD 1 of the modulator of FIG. 5 is identical or similar to analog integration circuit 101 of sub-modulator MOD 1 described in relation with FIG. 4 .

Analog integration circuit 101 of sub-modulator MOD 2 of FIG. 5 differs from analog integration circuit 101 of sub-modulator MOD 2 of FIG. 4 essentially in that it comprises no replication of the output summing circuit of analog integration circuit 101 of sub-modulator MOD 1 . In other words, analog integration circuit 101 of sub-modulator MOD 2 of FIG. 5 differs from analog integration circuit 101 of sub-modulator MOD 2 of FIG. 4 essentially in that it does not comprise capacitors C 4 ′, C 3 ′ and C 5 ′ and the switches associated with these capacitors.

In the example of FIG. 5 , the analog integration circuits 101 of sub-modulators MOD 1 and MOD 2 are directly series-coupled, that is, output terminal A 3 of analog integration circuit 101 of sub-modulator MOD 1 is connected to input terminal A 1 of analog integration circuit 101 of sub-modulator MOD 2 (corresponding to the input node of integrator Ia 1 of sub-modulator MOD 2 ).

In the embodiment of FIG. 5 , the sigma-delta modulator comprises a single 1-bit analog-to-digital converter 103 , for example, a comparator identical or similar to comparators 103 of sub-modulators MOD 1 and MOD 2 of FIG. 4 , shared by sub-modulators MOD 1 and MOD 2 . The input of converter 103 is coupled to the output of analog integration circuit 101 of sub-modulator MOD 2 . More particularly, in the shown example, the sigma-delta modulator comprises a capacitor Cc having a first electrode connected to output node A 3 of analog integration circuit 101 of sub-modulator MOD 2 (corresponding to the output node of integrator Ia 1 of sub-modulator MOD 2 ), and having its second electrode coupled to the input of analog-to-digital converter 103 by a switch Φ 2 d . The first electrode of capacitor Cc is further coupled to the input of converter 103 by a switch Φ 1 d . Further, the second electrode of capacitor Cc is coupled to node R by a switch Φ 1 .

The sigma-delta modulator of FIG. 5 further comprises a logic circuit 501 (LOGIC) comprising a binary input coupled to the output terminal of 1-bit analog-to-digital converter 103 , and three binary outputs respectively coupled to nodes N 1 , N 2 , and N 3 and supplying binary output signal Y 1 of sub-modulator MOD 1 , binary output signal Y 2 of sub-modulator MOD 2 , and binary output signal Y of the modulator.

A timing diagram is shown in FIG. 5 to show the chaining in a cycle of two successive switching phases P 1 and P 2 of the modulator switches. As in the example of FIG. 4 , during phase P 1 , switches Φ 2 and Φ 2 d are turned on, switches Φ 1 and Φ 1 d being kept off (non-conductive). At the end of phase P 1 , switches Φ 2 and Φ 2 d are turned off. During phase P 2 , switches Φ 1 and Φ 1 d are turned on (made conductive), switches Φ 2 and Φ 2 d being kept off (non-conductive). At the end of phase P 2 , switches Φ 1 and Φ 1 d are turned off. At the end of each of phases P 1 and P 2 , the internal signal of comparator 103 is sampled (rising edges of signal Φcomp) to generate signals Y 1 and Y 2 .

In the implementation of FIG. 5 , the function of summing circuit 109 of FIG. 3 is implemented by capacitors C 4 , C 3 , and C 5 and the switches connected to these capacitors. At each cycle k of a phase of conversion of analog input signal U into a digital value, during phase P 1 , a signal S 1 resulting from the weighted sum of output signal O 1 of integrator Ia 1 of sub-modulator MOD 1 , of output signal O 2 of integrator Ia 2 of sub-modulator MOD 1 , and of output signal Y of the sigma-delta modulator is generated on output node A 3 of analog integration circuit 101 of sub-modulator MOD 1 , with S 1 =−(O 2 +c 3 *O 1 −d*Y). Signal S 1 is applied to input node A 1 of analog integration circuit 101 of the downstream sub-modulator MOD 2 , that is, in the shown example, to the input of integrator Ia 1 of sub-modulator MOD 2 . Signal S 1 is thus integrated by integrator Ia 1 of sub-modulator MOD 2 , that is, during phase P 1 , the value of integrator Ia 1 is incremented by value S 1 . Prior thereto, during phase P 2 of the previous cycle during which switches Φ 1 are conductive, capacitor Cc is charged to the output value of integrator Ia 1 . Thus, during the next phase P 1 (Φ 1 off), output coupling capacitor Cc introduces at the input of comparator 103 a voltage shift with respect to the current output value of integrator Ia 1 equal to the output value of integrator Ia 1 at the end of the previous cycle. In other words, during phase P 1 , the voltage variation observed at the input of comparator 103 due to coupling capacitor Cc corresponds to quantity S 1 . At the end of phase P 1 , the value S 1 observed on the second electrode of capacitor Cc is quantized by comparator 103 to generate signal Y 1 .

During phase P 2 following phase P 1 , signal Y 1 is applied to the input of integrator Ia 1 of sub-modulator MOD 2 (node N 4 ). Thus, during phase P 2 , the output value of integrator Ia 1 of sub-modulator MOD 2 is incremented by a value corresponding to the quantization noise E 1 introduced by analog-to-digital converter 103 during the quantization of signal S 1 , from which feedback Y 2 is subtracted (node N 5 ). At the end of phase P 2 , the output signal of integrator Ia 1 of sub-modulator MOD 2 is directly quantized by comparator 103 (without passing through coupling capacitor Cc) to obtain signal Y 2 .

Thus, functionally, the circuit of FIG. 5 behaves substantially in the same way as the circuit of FIG. 3 . However, in the implementation of FIG. 5 , rather than duplicating the circuit for generating signal S 1 at the input of sub-modulator MOD 2 as in the implementation of FIG. 4 , it is provided to reconstruct signal S 1 by diverting the output signal of integrator Ia 1 of downstream modulator MOD 2 through coupling capacitor Cc.

An advantage of the embodiment of FIG. 5 is that signal S 1 is not duplicated, which, in addition to the advantage in terms of hardware cost due to the suppressing of capacitors C 4 ′, C 3 ′, C 5 ′ and of their switches, enables, during the generation of quantization error signal E 1 =Y 1 −S 1 , to avoid risks of lack of integrity of signal S 1 due to a mismatch of the duplicated capacitors.

Another advantage of the implementation of FIG. 5 is that it enables to spare a 1-bit analog-to-digital converter with respect to the implementation of FIG. 4 .

Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, the described embodiments are not limited to the example of MASH 2-I-type sigma-delta modulator architecture described in relation with FIGS. 3 and 5 . More generally, the provided solution, implementing an analog circuit for diverting the output signal of an analog integration circuit 101 of a downstream sub-modulator to reconstruct an output signal of an analog integration circuit 101 of an upstream sub-modulator may be used in any type of sigma-delta modulator, comprising at least two cascaded sub-modulators.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.