Single-stage CMOS-based voltage quadrupler circuit

The present invention relates to a single-stage charge pump circuit configured to perform a quadrupling of an input voltage Vin (i.e., produce an output voltage Vout≈4*Vin).

A positive voltage charge-pump is a DC-DC voltage converter that operates to convert an input voltage to an output voltage having a magnitude that is higher than the input voltage. The input is, in many instances, a supply voltage for a circuit. Such charge pump circuits typically use capacitors as energy storage devices. The capacitors are switched in such a way that the desired voltage conversion occurs.

Charge pumps are useful in many different types of circuits, including low-voltage circuits, dynamic random access memory circuits, switched-capacitor circuits, EEPROM's and transceivers. In non-volatile memories, for example, charge-pumps are critical because they are used to generate the high voltages necessary to perform program and erase operations.

A charge pump circuit typically includes a basic building block referred to as a “voltage doubler” circuit. The voltage doubler circuit takes a DC input voltage (VIN) and generates an output voltage VOUT that is substantially equal to double the input voltage (i.e., 2*VIN), where “substantially equal” means at or nearly the same voltage within a tolerance range (generally less than a few percent) that is dependent voltage drop (or charge loss) across parasitic capacitances and output current load. By cascading N such voltage doubler circuit stages in series, a final output voltage that can be produced that is substantially equal to (N+1)*VIN.

An example of a prior art voltage doubler circuit 10 stage is shown in FIG. 1 . This circuit 10 is commonly referred to in the art as a CMOS latch-based voltage doubler. The circuit 10 includes a latch circuit formed by two cross-coupled CMOS inverter circuits 12 and 14 . The source terminals of the n-channel MOS transistors of the latch circuit are connected to an input node A (receiving the input voltage VIN) and the source terminals of the p-channel MOS transistors of the latch circuit are connected to an output node B (generating the output voltage VOUT). A capacitor C is coupled to each pair of connected drain terminals of the CMOS transistors of the latch circuit. A first capacitor coupled to inverter circuit 12 is configured to receive a clock signal CK and a second capacitor coupled to inverter circuit 14 is configured to receive a clock signal CKN (which is a logical inversion of the clock signal CK). Operation of this circuit 10 in response to the clock signals CK and CKN to double the input voltage is well known to those skilled in the art.

A voltage quadrupler circuit can be made by cascading three such voltage doubler circuit 10 stages in series as shown in FIG. 2 to produce a final output voltage VOUT that is substantially equal to 4*VIN. In comparison to other prior art cascaded circuits, the circuit of FIG. 2 advantageously does not exhibit a threshold voltage drop across the connected stages of the charge pump. Furthermore, the circuit requires just the two clock phases (CK and CKN) as applied to all stages. However, there are a number of known drawbacks including:

1) As N increases, for example when N=3 for a voltage quadrupler as in FIG. 2 , the three cascaded circuit 10 stages occupy a significantly large amount of circuit area, especially due to the presence of six capacitors C whose occupied area is significant and dominates the overall area occupied by the circuit. The capacitance of each capacitor C is selected dependent on a number of different parameters including operating frequency, output current load, output capacitive load and ramp-up time of the charge pump. In general, the capacitance of each capacitor C included in the circuit is the same, and thus the overall occupied capacitor area is six times the area required for one capacitor.

2) Also, there is some charge loss across the CMOS transistor switches from one circuit stage to another circuit stage during the charge pumping operation. As an example, with an input voltage VIN=2V, the output voltages at the first, second and third voltage doubler circuit 10 stages may equal 3.96V, 5.92V and 7.89V, respectively, with the difference of 0.11V in the substantially equal output voltage representing a percentage or offset of 1.4% from the ideal 8V output voltage.

There is accordingly a need in the art for a voltage quadrupler circuit that can be used to generate an output voltage substantially equal to four times the input voltage and which occupies a reduced circuit area in comparison to prior art multi-stage cascaded charge pumps.

In an embodiment, a circuit comprises: a first transistor having a source-drain path coupled between a voltage input node and a first node; a first boost capacitor having a first plate coupled to the first node and a second plate coupled to receive a first clock signal; a first level shifting circuit configured to receive the first clock signal and output a level shifted first clock signal; a second level shifting circuit configured to receive a second clock signal that is a logical invert of the first clock signal and output a level shifted second clock signal; a second transistor having a source-drain path coupled between the voltage input node and a second node; a first bootstrapping capacitor having a first plate coupled to the second node and a second plate coupled to receive the level shifted first clock signal; a third transistor having a source-drain path coupled between the first node and a third node, said third transistor having a gate controlled by a first control signal at the second node; and a second boost capacitor having a first plate coupled to the third node and a second plate coupled to receive the level shifted second clock signal.

In an embodiment, a circuit comprises: a first level shifting circuit configured to receive a first clock signal and output a level shifted first clock signal; a second level shifting circuit configured to receive a second clock signal and output a level shifted second clock signal, wherein the second clock signal is a logical invert of the first clock signal; a first voltage boosting circuit including a first capacitor having a first plate directly connected to a first node and a second plate coupled to receive the first clock signal, said first voltage boosting circuit configured to boost a voltage at the first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially equal to two times the first voltage level; a first pass transistor configured to selectively pass the boosted voltage at the first node to a second node in response to a first control signal generated in response to the level shifted first clock signal; and a second voltage boosting circuit including a second capacitor having a first plate directly connected to the second node and a second plate coupled to receive the level shifted second clock signal, said second voltage boosting circuit configured to boost a voltage at the second node in response to the level shifted second clock signal from the second voltage level to a third voltage level that is substantially equal to two times the second voltage level.

For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:

FIG. 1 is a circuit diagram of a prior art CMOS latch-based voltage doubler circuit;

FIG. 2 is a circuit of a prior art voltage quadrupler circuit using three cascaded CMOS latch-based voltage doubler circuits;

FIG. 3 is a circuit of a single stage voltage quadrupler circuit; and

FIGS. 4-8 show signal waveforms for clocks and nodes of the FIG. 3 circuit.

Reference is now made to FIG. 3 showing a circuit diagram for a voltage quadrupler circuit 100 . The circuit 100 includes an n-channel MOS transistor MN 1 having a source terminal coupled to a supply voltage node VDD and a drain terminal coupled to node NA 1 (i.e., the source-drain path of the transistor is coupled between VDD and NA 1 ) and an n-channel MOS transistor MN 2 having a source terminal coupled to the supply voltage node VDD and a drain terminal coupled to node NA 2 . The transistors MN 1 and MN 2 are cross-coupled with the gate terminal of transistor MN 1 coupled to the drain terminal of transistor MN 2 at node NA 2 and the gate terminal of transistor MN 2 coupled to the drain terminal of transistor MN 1 at node NA 1 .

The circuit 100 further includes an n-channel MOS transistor MN 3 having a source terminal coupled to the supply voltage node VDD and a drain terminal coupled to node NB 2 and an n-channel MOS transistor MN 4 having a source terminal coupled to the supply voltage node VDD and a drain terminal coupled to node NB 1 . The gate terminal of transistor MN 3 is coupled to node NA 1 and the gate terminal of transistor MN 4 is coupled to node NA 2 .

The circuit 100 further includes an n-channel MOS transistor MN 7 having a source terminal coupled to node NA 1 and a drain terminal coupled to node NC 1 and an n-channel MOS transistor MN 8 having a source terminal coupled to node NA 2 and a drain terminal coupled to node NC 2 . The gate terminal of transistor MN 7 is coupled to node NB 1 and the gate terminal of transistor MN 8 is coupled to node NB 2 .

The circuit 100 further includes a p-channel MOS transistor MP 3 having a drain terminal coupled to node NC 1 and a source terminal coupled to a voltage output node VOUT and a p-channel MOS transistor MP 4 having a drain terminal coupled to node NC 2 and a source terminal coupled to the voltage output node VOUT. The transistors MP 3 and MP 4 are cross-coupled with the gate terminal of transistor MP 3 coupled to the drain terminal of transistor MP 4 at node NC 2 and the gate terminal of transistor MP 4 coupled to the drain terminal of transistor MP 3 at node NC 1 .

The voltage output node VOUT may be coupled to a circuit load that is equivalently represented in FIG. 3 by a load capacitance Cload and a load current Iload coupled between the voltage output node VOUT and ground. The magnitude of the voltage generated at the voltage output node VOUT is substantially equal to four times voltage at the supply voltage node VDD.

A capacitor C 1 has one terminal coupled to node NA 1 and another terminal coupled to receive a clock signal CK. A capacitor C 2 has one terminal coupled to node NA 2 and another terminal coupled to receive a clock signal CKN (which is a logical inversion of the clock signal CK). The voltage waveforms for the clock signals CK and CKN are shown in FIG. 4 .

A bootstrapped capacitor Cbs 1 has one terminal coupled to node NB 2 and another terminal coupled to receive a clock signal CKHN. A bootstrapped capacitor Cbs 2 has one terminal coupled to node NB 1 and another terminal coupled to receive a clock signal CKH (which is a logical inversion of the clock signal CKHN). A capacitor C 3 has one terminal coupled to node NC 1 and another terminal coupled to receive a clock signal CKHN. A capacitor C 4 has one terminal coupled to node NC 2 and another terminal coupled to receive a clock signal CKH. The voltage waveforms for the clock signals CKH and CKHN are shown in FIG. 5 .

The bootstrapped capacitors Cbs 1 and Cbs 2 are comparatively much smaller than the capacitors C 1 -C 4 , having capacitance values large enough to generate signals of sufficient magnitude to drive the gates of transistors MN 7 and MN 8 . As an example, each of the bootstrapped capacitors Cbs 1 and Cbs 2 may have a capacitance value of about 10% of the capacitance value of each of the capacitors C 1 -C 4 . Thus, each of the bootstrapped capacitors Cbs 1 and Cbs 2 occupies a substantially smaller circuit area than each of the capacitors C 1 -C 4 . Generally speaking, the circuit area occupied by the capacitors C 1 -C 4 dominates and the overall area occupied by capacitors for the circuit is slightly larger than four times the area occupied by one of the capacitors C 1 -C 4 , and thus is substantially less than the total occupied area of the six capacitors of the prior art cascade circuit of FIG. 2 .

A CMOS inverter 102 has an input coupled to the supply voltage node VDD and an output generating the clock signal CKH. A source terminal of the p-channel MOS transistor in inverter 102 is coupled to the node NA 1 and a source terminal of the n-channel MOS transistor in inverter 102 is coupled to receive the clock signal CK.

A CMOS inverter 104 has an input coupled to the supply voltage node VDD and an output generating the clock signal CKHN. A source terminal of the p-channel MOS transistor in inverter 104 is coupled to the node NA 2 and a source terminal of the n-channel MOS transistor in inverter 104 is coupled to receive the clock signal CKN.

The CMOS inverters 102 and 104 function as a clock level shifting circuit. FIG. 4 shows the waveforms for the clock signals CK and CKN. FIG. 5 shows the waveforms for the clock signals CKH and CKHN. It will be noted that the high voltage level of the clock signals CKH and CKHN is substantially equal to 2*VDD, with the high voltage level of the clock signals CK and CKN being VDD. The clock signals CKH and CKHN have a same phase as the clock signals CK and CKN, respectively.

The voltage quadrupler circuit 100 advantageously operates from just two clocks (CK/CKH and CKN/CKNH) and is implemented as a single operating stage.

In this configuration, the capacitor C 1 and transistor MN 1 form a voltage boosting circuit operable to boost a voltage at node NA 1 from VDD to 2*VDD in response to the clock signal CK and a control signal at the gate of transistor MN 1 which is dependent on the clock signal CKN (and a boosted voltage at node NA 2 ). Similarly, the capacitor C 2 and transistor MN 2 form a voltage boosting circuit operable to boost a voltage at node NA 2 from VDD to 2*VDD in response to the clock signal CKN and a control signal at the gate of transistor MN 2 which is dependent on the clock signal CK (and a boosted voltage at node NA 1 ).

The transistor MN 7 functions as a pass transistor device that selectively passes the boosted voltage at node NA 1 to node NC 1 in response to a control signal generated at node NB 1 . A control circuit formed by transistor MN 4 and bootstrapping capacitor Cbs 2 generates the control signal at node NB 1 in response to clock signal CKH and the control signal at node NA 2 . This control circuit is also a voltage boosting circuit which boosts the voltage at node NB 1 from VDD to 2*VDD in response to the clock signal CKH in order to generate sufficient drive to turn on pass transistor MN 7 .

Similarly, the transistor MN 8 functions as a pass transistor device that selectively passes the boosted voltage at node NA 2 to node NC 2 in response to a control signal generated at node NB 2 . A control circuit formed by transistor MN 3 and bootstrapping capacitor Cbs 1 generates the control signal at node NB 2 in response to clock signal CKHN and the control signal at node NA 1 . This control circuit is also a voltage boosting circuit which boosts the voltage at node NB 2 from VDD to 2*VDD in response to the clock signal CKHN in order to generate sufficient drive to turn on pass transistor MN 8 .

The capacitor C 3 forms another voltage boosting circuit operable to boost a voltage at node NC 1 from 2*VDD to 4*VDD in response to the clock signal CKHN. This boost operation occurs when the control signal at node NB 1 turns off pass transistor MN 7 to isolate node NC 1 from node NA 1 . The transistor MP 3 functions as another pass transistor device to pass the boosted voltage at node NC 1 to the output voltage node VOUT.

The capacitor C 4 forms another voltage boosting circuit operable to boost a voltage at node NC 2 from 2*VDD to 4*VDD in response to the clock signal CKH. This boost operation occurs when the control signal at node NB 2 turns off pass transistor MN 8 to isolate node NC 2 from node NA 2 . The transistor MP 4 functions as another pass transistor device to pass the boosted voltage at node NC 2 to the output voltage node VOUT.

The voltage quadrupler circuit 100 operates as follows:

To begin, assume that the clocks are not running, and so the nodes NA 1 and NA 2 will be charged to substantially the VDD voltage level. Now, assume the clock signals CK and CKN are applied. With the clock signal CK at the 0 (ground GND) voltage level and the clock signal CKN at the VDD voltage level, the voltage at node NA 1 remains at the VDD voltage level and the voltage at node NA 2 is boosted to the 2*VDD voltage level through capacitor C 2 . The boosted voltage at node NA 2 is sufficient to cause transistor MN 1 to turn on and NA 1 remains charged to the VDD voltage level. When the logic states of the clock signals CK and CKN change, the clock signal CK transitions to the VDD voltage level and the voltage at node NA 1 is boosted through capacitor C 1 to the 2*VDD voltage level. The boosted voltage at node NA 1 is sufficient to cause transistor MN 2 to turn on and node NA 2 transitions to the VDD voltage. The voltage waveforms for the signals at nodes NA 1 and NA 2 are shown in FIG. 6 .

When node NA 1 is boosted to the 2*VDD voltage level, the transistor MP 1 of inverter 102 turns on and the clock signal CKH transitions from the ground voltage level to the 2*VDD voltage level. At the same time, with the clock signal CKN at the ground voltage level, the transistor MN 6 of the inverter 104 turns on and the clock signal CKHN transitions from the 2*VDD voltage level to the ground voltage level. When the logic states of the clock signals CK and CKN change, node NA 2 is boosted to the 2*VDD voltage level and the transistor MP 2 of inverter 104 turns on to drive the clock signal CKHN to the 2*VDD voltage level. At the same time, the clock signal CK is at the ground voltage level and transistor MN 5 of the inverter 102 drive the clock signal CKH to the ground voltage level. The voltage waveforms for the clock signals are shown in FIGS. 4 and 5 .

The transition of node NA 2 towards the 2*VDD voltage level causes the transistor MN 3 to turn on and charge node NB 2 and capacitor Cbs 1 to the VDD voltage level (the clock signal CKHN being at the ground voltage level). With the previous logic state of the clock signal CKH at the ground voltage level, the node NB 1 and capacitor Cbs 2 were charged to the VDD voltage level. When the clock signal CKH now transitions to the 2*VDD voltage level, the node NB 1 is boosted to the 3*VDD voltage level through the capacitor Cbs 2 . The transition of node NB 1 towards the 3*VDD voltage level causes the transistor MN 7 to turn on and charge node NC 1 and capacitor C 3 to the 2*VDD voltage level (the node NA 1 being at the 2*VDD voltage level and the clock signal CKHN being at the ground voltage level). When the logic states of the clock signals CK and CKN change, the clock signal CKHN transitions to the 2*VDD voltage level and the node NB 2 is boosted to the 3*VDD voltage level through the capacitor Cbs 1 and transistor MN 8 turns on to charge node NC 2 and capacitor C 4 to the 2*VDD voltage level (the node NA 2 being at the 2*VDD voltage level and the clock signal CKH being at the ground voltage level). The voltage waveforms for the signals at nodes NB 1 and NB 2 are shown in FIG. 7 .

In the next clock cycle, when the clock CK transitions from the VDD voltage level to the ground voltage level, and thus the clock CKN transitions from the ground voltage level to the VDD voltage level, the clock signal CKHN will transition from the ground voltage level to the 2*VDD voltage level. The voltage at node NC 1 is thus boosted to the 4*VDD voltage level through the capacitor C 3 . The 2*VDD voltage level at node NC 2 turns on transistor MP 3 and the 4*VDD voltage level is passed from node NC 1 to the voltage output node VOUT. When the logic states of the clock signals CK and CKN change, the voltage at node NC 2 is boosted to the 4*VDD voltage level through the capacitor C 3 and transistor MP 4 turns on to pass the 4*VDD voltage level from node NC 2 to the voltage output node VOUT. The voltage waveforms for the signals at nodes NC 1 and NC 2 are shown in FIG. 8 .

The voltage levels for the signals shown in FIGS. 4-8 are ideal voltage levels during operation of the circuit 100 . It will be understood that the actual voltage levels of the signals shown in FIGS. 4-8 will not necessarily equal the ideal voltage levels. A simulation of the circuit of FIG. 3 reveals: a logic high voltage level for the clock signals CKH and CKHN of 3.95V with VDD at 2V; a logic high voltage level for the signals at nodes NA 1 and NA 2 of 3.95V; a logic high voltage level for the signals at nodes NB 1 and NB 2 of 5.91V; a logic high voltage level for the signals at nodes NC 1 and NC 2 of 7.87V; and a voltage at the voltage output node VOUT of 7.86V. It will be noted that the voltage at the voltage output node VOUT of 7.86V is substantially equal to the 7.89V produced by the prior art FIG. 2 circuit with a 2V input.

The circuit 100 of FIG. 3 possesses at least the following advantages over the prior art FIG. 2 circuit: a) occupied area of the circuit is substantially less because only four large capacitors (as opposed to six in the prior art) are needed; and b) the need for a separate clock buffer for each stage is obviated because the FIG. 3 circuit needs only a single clock buffer to drive the CK and CKN clock signals.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.