Multiphase power factor improvement circuit

This application is a continuation application of International Application No. PCT/JP2015/070155, filed on Jul. 14, 2015, entitled “MULTIPHASE POWER FACTOR IMPROVEMENT CIRCUIT”, the entire contents of which are incorporated herein by reference.

The disclosure relates to a multiphase power factor improvement circuit such as an interleaved converter.

Japanese Patent Application Publication No. 2013-192340 discloses a continuous conduction mode power factor correction (CCMPFC) circuit. This circuit detects an inputted current and performs power factor correction control based on the detected inputted current.

Japanese Patent Application Publication No. 2014-68424 discloses a CCMPFC circuit. This circuit detects a switch current flowing through a switch and performs overcurrent protection for the switch based on the switch current.

FIG. 6 illustrates a single-phase CCMPFC circuit. In this circuit, a ground current detected by current sensor S 3 is equal to an inputted current (current flowing through reactor L 1 ) necessary for CCMPFC control. Besides, while switching circuit Q 1 is ON, the ground current is equal to the current of switching circuit Q 1 . For this reason, it is possible to perform both overcurrent protection and CCMPFC control for switching circuit Q 1 with only single current sensor S 3 .

FIG. 7 illustrates a parallel converter including: a first converter made up of reactor L 1 , switching circuit Q 1 , and diode D 1 ; and a second converter made up of reactor L 2 , switching circuit Q 2 , and diode D 2 , which are connected in parallel. This parallel converter is a multi-phased version of a PFC.

One or more embodiments of a multiphase power factor improvement circuit include: a rectification circuit that rectifies an alternating current voltage of an alternating current power supply; a parallel converter comprising converters that correspond to phases and that are connected in parallel to an output terminal of the rectification circuit, each converter comprising a reactor; a switching circuit that is connected in series to the reactor; and a diode that is connected in series to the reactor; a smoothing capacitor that is connected to an output terminal of the parallel converter; a control circuit that generates pulse signals corresponding to phases based on an error voltage between an output voltage of the smoothing capacitor and a reference voltage and on an output voltage of the rectification circuit, and that switches the switching circuits in the converters using the pulse signals; and current detection circuits that are provided corresponding to the converters and that detect currents flowing through the switching circuits.

FIG. 1 is a circuit configuration diagram of a continuous conduction mode multiphase power factor improvement circuit according to one or more embodiments;

FIG. 2 is a diagram illustrating a configuration of a first current reproduction circuit inside a current reproduction circuit provided in a controller of the continuous conduction mode multiphase power factor improvement circuit;

FIG. 3 is a diagram illustrating a configuration of a second current reproduction circuit inside the current reproduction circuit provided in a controller of the continuous conduction mode multiphase power factor improvement circuit;

FIGS. 4A and 4B are timing charts for explaining operations of the current reproduction circuit of the continuous conduction mode multiphase power factor improvement circuit;

FIG. 5 is a circuit configuration diagram of one or more continuous conduction mode multiphase power factor improvement circuits;

FIG. 6 is a circuit configuration diagram of a continuous conduction mode single-phase power factor improvement circuit according to related art; and

FIG. 7 is a circuit configuration diagram of a continuous conduction mode multiphase power factor improvement circuit according to related art.

Embodiments of a multiphase power factor improvement circuit are hereinafter described with reference to the drawings.

FIG. 1 is a circuit configuration diagram of a continuous conduction mode multiphase power factor improvement circuit according to one or more embodiments. As a continuous conduction mode multiphase power factor improvement circuit, FIG. 1 provides an explanation illustrating a continuous conduction mode two-phase power factor improvement circuit, that is, a continuous conduction mode interleaved power factor improvement circuit.

Note that the invention is applicable to a two- or higher-phase power factor improvement circuit of a three- or higher-phase in a continuous conduction mode, and is also applicable to a power factor improvement circuit in a discontinuous conduction mode or a critical conduction mode as the continuous conduction mode multiphase power factor improvement circuit.

The continuous conduction mode two-phase power factor improvement circuit is a power conversion apparatus, which reduces the current ripple and the current inputted to two converters by connecting the converters in parallel and shifting the phases of the converters relative to each other.

In FIG. 1 , full-wave rectifier 2 may correspond to a rectification circuit. Full-wave rectifier 2 inputs an alternating current voltage from alternating current power supply 1 , full-wave-rectifies the inputted alternating current voltage, and outputs the rectified voltage to capacitor Ci.

Capacitor Ci is connected in parallel to an output end of full-wave rectifier 2 , and a first series circuit made up of step-up reactor L 1 , primary coil P 1 of transformer T 1 , and switching circuit Q 1 including a MOSFET is connected to the output end of full-wave rectifier 2 . An anode of diode D 1 is connected at a connection point of step-up reactor L 1 and primary coil P 1 of transformer T 1 , while a cathode of diode D 1 is connected to the ground via smoothing capacitor Co.

A second series circuit made up of reactor L 2 , primary coil P 2 of transformer T 2 , and switching circuit Q 2 including a MOSFET is connected to the output end of full-wave rectifier 2 . An anode of diode D 2 is connected at a connection point of step-up reactor L 2 and primary coil P 2 of transformer T 2 , while a cathode of diode D 2 is connected to the ground via smoothing capacitor Co.

A first converter includes step-up reactor L 1 , switching circuit Q 1 , and diode D 1 . A second converter includes step-up reactor L 2 , switching circuit Q 2 , and diode D 2 . A parallel converter includes the first converter and the second converter, and the input ends of these first converter and second converter are connected to each other, and so are the output ends.

As a dividing resistor, a series circuit of resistor R 1 and resistor R 2 is connected to the output end of full-wave rectifier 2 . As a dividing resistor, a series circuit of resistor R 3 and resistor R 4 is connected to both ends of smoothing capacitor Co.

Control circuit 3 inputs input voltage VAC based on a dividing ratio between resistor R 1 and resistor R 2 , and feedback voltage VFB based on a dividing ratio between resistor R 3 and resistor R 4 . Control circuit 3 generates a drive signal based on input voltage VAC and feedback voltage VFB, and outputs the drive signal to gates of switching circuits Q 1 , Q 2 including MOSFETs. The dividing ratios for obtaining input voltage VAC and feedback voltage VFB are preferably set equal to each other.

Transformer T 1 includes primary coil P 1 and secondary coil S 1 . A turns ratio of primary coil P 1 to secondary coil S 1 is 1:N. A series circuit of diode D 3 and resistor R 5 is connected to both ends of primary coil P 1 . Voltage CS 1 at a connection point of diode D 3 and resistor R 5 is inputted to first controller 31 of control circuit 3 . The first current detector includes transformer T 1 , diode D 3 , and resistor R 5 . The first current detector detects a current through switching circuit Q 1 and outputs voltage CS 1 proportional to the detected current.

Transformer T 2 includes primary coil P 2 and secondary coil S 2 . A turns ratio of primary coil P 2 to secondary coil S 2 is 1:N. A series circuit of diode D 4 and resistor R 6 is connected to both ends of primary coil P 2 . Voltage CS 2 at a connection point of diode D 4 and resistor R 6 is inputted to second controller 32 of control circuit 3 . The second current detector includes transformer T 2 , diode D 4 , and resistor R 6 . The second current detector detects a current through switching circuit Q 2 and outputs voltage CS 2 proportional to the detected current. The first current detector and the second current detector may correspond to current detectors.

Control circuit 3 includes error amplifier Amp, first controller 31 , second controller 32 , arithmetic unit 33 , V/I conversion circuit 34 , and current mirror circuit 35 .

Error amplifier Amp amplifies an error between feedback voltage VFB and reference voltage Vref 1 to output an error amplification signal. Arithmetic unit 33 calculates input voltage VAC and error amplification signal from error amplifier Amp, and outputs target values of currents flowing through switching circuits Q, Q 2 to V/I conversion circuit 34 .

V/I conversion circuit 34 converts voltages based on the current target values from arithmetic unit 33 to currents IREF 1 , IREF 2 . Current mirror circuit 35 outputs current IREF 1 to first controller 31 and outputs current IREF 2 to second controller 32 , the currents having been converted by V/I conversion circuit 34 .

First controller 31 includes adder 36 , comparator CMP 3 , current reproduction circuit 37 , V/I conversion circuit 38 , comparator CMP 2 , logic circuit 39 , and buffer BF. Note that since second controller 32 may have the same configuration as that of first controller 31 , details of the configurations of the elements are described only for first controller 31 here.

Current reproduction circuit 37 reproduces a current flowing through reactor L 1 based on voltage CS 1 obtained by rectifying a voltage generated in secondary coil S 1 of transformer T 1 and on current Ia proportional to a voltage difference between input voltage VAC and feedback voltage VFB. Current reproduction circuit 37 outputs voltage VIL corresponding to the reproduced voltage to V/I conversion circuit 38 . Note that detailed circuit configuration of current reproduction circuit 37 is described later.

V/I conversion circuit 38 converts voltage VIL to current I. Adder 36 performs subtraction on current IREF 1 from current mirror circuit 35 and current I converted by V/I conversion circuit 38 , and outputs the obtained current to an inverting input terminal of comparator CMP 2 .

Comparator CMP 2 compares the current from adder 36 and a triangle wave signal to generate pulse signal PWM 1 , and outputs pulse signal PWM 1 to logic circuit 39 . Second controller 32 generates pulse signal PWM 2 . Here, an ON-OFF duty cycle of pulse signal PWM 2 is the same as an ON-OFF duty cycle of pulse row signal PWM 1 , and phases of pulse signal PWM 2 and pulse signal PWM 1 are shifted by 180°, that is, by half a period.

Comparator CMP 3 compares voltage CS 1 and reference voltage Vref 2 . If voltage CS 1 is less than reference voltage Vref 2 , comparator CMP 3 outputs a L voltage to logic circuit 39 , and if voltage CS 1 reaches reference voltage Vref 2 or higher, comparator CMP 3 outputs a H voltage, that is, an overcurrent protection signal to logic circuit 39 .

If a L voltage is inputted from comparator CMP 3 , logic circuit 39 outputs pulse signal PWM 1 from comparator CMP 2 to buffer BF. Buffer BF turns switching circuit Q 1 ON and OFF by applying pulse signal PWM 1 from comparator CMP 2 to the gate of switching circuit Q 1 .

If a H voltage is inputted from comparator CMP 3 , logic circuit 39 does not output pulse signal PWM 1 from comparator CMP 2 to buffer BF. In other words, it is possible to perform overcurrent protection for switching circuit Q 1 by turning switching circuit Q 1 OFF.

Next, a detailed circuit configuration of current reproduction circuit 37 is illustrated in FIG. 2 and FIG. 3 . Current reproduction circuit 37 includes first current reproduction circuit 37 a illustrated in FIG. 2 and second current reproduction circuit 37 b illustrated in FIG. 3 . First current reproduction circuit 37 a generates current Ia proportional to the voltage difference between input voltage VAC and feedback voltage VFB, and includes buffers 40 a , 40 b , resistors R 7 to R 9 , operational amplifiers 41 , 42 , MOSFET Q 5 , and current mirror circuits 43 , 44 .

Buffer 40 a outputs feedback voltage VFB to a non-inverting terminal of operational amplifier 41 via resistor R 7 . Buffer 40 b outputs input voltage VAC to an inverting terminal of operational amplifier 41 via resistor R 8 .

One end of resistor R 7 and one end of resistor R 10 are connected to the non-inverting terminal of operational amplifier 41 , and the other terminal of resistor R 10 is connected to the ground. One end of resistor R 8 and one end of resistor R 9 are connected to the inverting terminal of operational amplifier 41 , and the other terminal of resistor R 9 is connected to an output terminal of operational amplifier 41 . Operational amplifier 41 outputs the voltage difference between feedback voltage VFB and input voltage VAC.

The other end of resistor R 9 and the output terminal of operational amplifier 41 are connected to a non-inverting terminal of operational amplifier 42 , and a source of MOSFET Q 5 and one end of resistor R are connected to an inverting terminal of operational amplifier 42 . The other end of resistor R is connected to the ground.

A gate of MOSFET Q 5 is connected to the output terminal of operational amplifier 42 , and a drain of MOSFET Q 5 is connected to current mirror circuit 43 . Operational amplifier 42 and MOSFET Q 5 convert the voltage difference from operational amplifier 41 between feedback voltage VFB and input voltage VAC to current I 1 corresponding to the voltage difference between feedback voltage VFB and input voltage VAC, and cause converted current I 1 to flow through MOSFET Q 5 and resistor R.

Current mirror circuit 43 causes current I 1 to flow through MOSFET Q 5 and resistor R, and thereby causes current I 2 , proportional to current I 1 , to flow through current mirror circuit 44 . Current mirror circuit 44 causes current Ia, proportional to current I 2 from current mirror circuit 43 , to flow. For this reason, current Ia is a current which is proportional to the voltage difference between feedback voltage VFB and input voltage VAC. Also, current Ia is a current dependent on gradients of the currents flowing through reactors L 1 , L 2 while switching circuits Q 1 , Q 2 are turned OFF. Current Ia is a current that flows through current source Ia provided in second current reproduction circuit 37 b.

Next, a configuration of second current reproduction circuit 37 b is described. Second current reproduction circuit 37 b includes PNP bipolar transistor Q 3 , resistor R 10 , NPN bipolar transistor Q 4 , capacitor C, and current source Ia.

One end of resistor R 10 is connected to power supply Vcc, and the other end of resistor R 10 is connected to an emitter of bipolar transistor Q 3 . Voltage CS is applied to a base of bipolar transistor Q 3 being a control electrode, and a collector of bipolar transistor Q 3 is connected to the ground. A collector of bipolar transistor Q 4 is connected to power supply Vcc. In other words, bipolar transistors Q 3 , Q 4 are configured as an emitter follower.

A base of bipolar transistor Q 4 being a control electrode is connected to the emitter of bipolar transistor Q 3 and the other end of resistor R 10 . An emitter of bipolar transistor Q 4 is connected to one end of capacitor C, one end of current source Ia, and an input terminal of buffer 45 . The other end of capacitor C and the other end of current source Ia are connected to the ground.

Next, description is provided for operations of second current reproduction circuit 37 b having such a configuration with reference to FIG. 3 and FIGS. 4A and 4B . FIGS. 4A and 4B are timing charts for explaining operations of current reproduction circuit 37 of the continuous conduction mode multiphase power factor improvement circuit of Embodiment 1. FIG. 4A illustrates the case where current Ia is relatively large, and FIG. 4B illustrates the case where current Ia is relatively small.

In FIGS. 4A and 4B , CS represents voltage CS to be inputted to the base of bipolar transistor Q 3 , an V 1 is a base voltage of bipolar transistor Q 4 . Q 4 is bipolar transistor Q 4 , and Vc is a voltage of capacitor C.

Here, operations when switching circuit Q 1 is turned ON and OFF are described. An ON-OFF operation of switching circuit Q 2 is performed while being shifted by half a period relative to an ON-OFF operation of switching circuit Q 1 .

To begin with, when switching circuit Q 1 is turned ON, voltage CS, which is obtained by converting the switch current of switching circuit Q 1 detected at transformer T 1 , increases linearly during the time interval from t 1 to t 2 illustrated in FIG. 4A , and is applied to the base of transistor Q 3 . Base voltage V 1 increases accordingly, and transistor Q 4 is turned ON. At this moment, base voltage V 1 of transistor Q 4 is higher than voltage CS by forward voltage VF between the emitter and the base of transistor Q 3 . Thus, voltage Vc of capacitor C is the same as voltage CS because voltage Vc is lower than base voltage V 1 by forward voltage VF between the base and the emitter of transistor Q 4 .

During the time interval from t 1 to t 2 , since power is supplied from power supply Vcc to capacitor C via resistor R 10 and bipolar transistor Q 4 , capacitor C is charged and voltage Vc increases linearly. Voltage Vc is sent as voltage VIL to V/I conversion circuit 38 via buffer 45 .

Next, when switching circuit Q 1 is turned OFF during the time interval from t 2 to t 3 , voltage CS becomes zero. If voltage CS is zero, transistor Q 4 is turned OFF because the voltage obtained by subtracting voltage Vc from voltage V 1 is smaller than forward voltage VF. Thus, capacitor C discharges since current source Ia drains electric charge, and voltage Vc of capacitor C decreases as a result. Here, voltage Vc of capacitor C has a voltage waveform with gradient Ia/C.

Since current Ia is large In FIG. 4A , the gradient of voltage Vc while switching circuit Q 1 is turned OFF is relatively large. Conversely, since current Ia is small in FIG. 4B , the gradient of voltage Vc while switching circuit Q 1 is turned OFF is relatively small.

Gradient Ia/C corresponds to the current of reactor L 1 . The reason for this is explained below.

For input voltage VIN and output voltage VOUT illustrated in FIG. 1 , the gradient of the current of reactor L 1 while switching circuit Q 1 is turned OFF is expressed by Equation (1):

dI L /dT OFF =( V OUT− V IN)/ L   (1),

where I L is the current flowing through reactor L 1 .

In the case of the current detector of Embodiment 1, the current while switching circuit Q 1 is turned ON is expressed by Equation (2):

CS=R 5· I L /N   (2),

where N is the ratio of primary coil P 1 to secondary coil S 1 .

The voltage gradient of capacitor C is expressed by Equation (3):

Ia/C=dVc/dt=R 5( V OUT− V IN)/ N·L   (3),

where L is an inductance value of reactor L 1 .

Equation (4) is obtained with reference to FIG. 1 and FIG. 2 :

Ia =( R 1 +R 2)( V OUT− V IN)/( R 2 ·R )  (4).

Referring to Equation (3) and Equation (4), resistor R of first current reproduction circuit 37 a is set to a value expressed by Equation (5):

R =( R 2 ·N·L )/{( R 1 +R 2)· R 5· C}   (5).

This makes it possible to reproduce in capacitor C a signal corresponding to the current flowing through reactor L 1 . This thus means that the current of switching circuit Q 1 is detected by the first current detector and the current flowing through reactor L 1 is detected thanks to voltage Vc corresponding to the detected current. This also means that the current of switching circuit Q 2 is detected by the second current detector and the current flowing through reactor L 2 is detected thanks to voltage Vc corresponding to the detected current. Here, since the dividing ratios for obtaining input voltage VAC and feedback voltage VFB are equal to each other, the currents flowing through the reactors can be obtained accurately using the equations written above.

In other words, for each current detector, when the current detector detects the current flowing through the switching circuit, control circuit 3 improves the power factor based on the current detected by that current detector and protects switching circuit Q 1 or Q 2 . Hence, it is possible to perform protection and CCMPFC control of switching circuits Q 1 , Q 2 by detecting a current at one location in each phase.

Additionally, it is possible to perform protection and CCMPFC control of switching circuits Q 1 , Q 2 with two current detectors, which can reduce the number of current detectors by one compared to the conventional configuration illustrated in FIG. 7 .

FIG. 5 is a circuit configuration diagram of a continuous conduction mode multiphase power factor improvement circuit representing one or more embodiments. FIG. 5 connects resistor Rcs 1 (Rcs 2 ) to the source of switching circuit Q 1 (Q 2 ) in place of transformers T 1 , T 2 , diodes D 3 , D 4 , and resistors R 5 , R 6 of Embodiment 1 illustrated in FIG. 1 .

Resistors Rcs 1 , Rcs 2 may correspond to current detectors. Resistor Rcs 1 detects the current flowing through switching circuit Q 1 and outputs the voltage, voltage CS 1 , which corresponds to the detected current to first controller 31 . Resistor Rcs 2 detects the current flowing through switching circuit Q 2 and outputs the voltage, voltage CS 2 , which corresponds to the detected current to second controller 32 .

Since the operations of first controller 31 and second controller 32 illustrated in FIG. 5 may be the same as those of first controller 31 and second controller 32 illustrated in FIG. 1 , their description is omitted.

The continuous conduction mode multiphase power factor improvement circuit of Embodiment 2 as described above also has the same effects as those of the continuous conduction mode multiphase power factor improvement circuit of Embodiment 1. Besides, since resistors Rcs 1 , Rcs 2 are used, it is possible to simplify the circuit.

Since the power factor improvement circuit in the discontinuous conduction mode or the critical conduction mode can remove the current detector conventionally provided, it is possible to obtain the same effects as those of the continuous conduction mode multiphase power factor improvement circuit of Embodiment 1.

One or more embodiments described above are applicable to an interleaved power factor improvement circuit.

In the circuit of the above-described related art, a multi-phased PFC circuit has a ground current that is equal to the inputted current, but is different from both the current of switching circuit Q 1 and the current of switching circuit Q 2 . For this reason, current sensors S 1 , S 2 are used to detect the current in each phase for the purpose of overcurrent protection of switching circuit Q 1 and switching circuit Q 2 , and current sensor S 3 is used to detect a current for the purpose of CCMPFC control. Thus, three current sensors S 1 to S 3 are necessary. In addition, also in a discontinuous conduction mode power factor improvement circuit (DCMPFC) or a critical conduction mode power factor improvement circuit (CRMPFC), it is sometimes necessary to detect the inputted current for the purpose of PFC control. Due to this, the multiphase power factor improvement circuit has a problem of complex configuration and expensive costs.

According to one or more embodiments described above, since the control circuit improves the power factor based on the currents flowing through the switching circuits and protects the switching circuits, it is possible to reduce the number of current detectors and to perform protection and PFC control of the switching circuits with a simple configuration.

The invention includes other embodiments in addition to the above-described embodiments without departing from the spirit of the invention. The embodiments are to be considered in all respects as illustrative, and not restrictive. The scope of the invention is indicated by the appended claims rather than by the foregoing description. Hence, all configurations including the meaning and range within equivalent arrangements of the claims are intended to be embraced in the invention.