Flip-flop and semiconductor system including the same

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0143420, filed on Oct. 31, 2016 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

The present disclosure relates to a flip-flop. More particularly, the present disclosure relates to a semiconductor system including a flip-flop.

Along with the development of an integrated circuit (IC), there is a prominent trend of producing ultrasmall, highly-reliable, high-speed, and low-power electronics including computers. In addition, due to the improvement in degree of integration, the complexity of an integrated circuit gradually increases. For example, 100,000 or more transistors may be integrated into one chip of a very large scale integrated circuit (VLSI). Thus, the design of such a complex integrated circuit is considered an important factor affecting the performance of the integrated circuit.

In particular, standard cells are used as pre-made logic devices to improve the efficiency in the design of application specific integrated circuits (ASICs). A standard cell includes multiple transistors and provides a logic function (AND, OR, XOR, XNOR, or the like) or a storage function (flip-flop, latch, or the like). In addition, a standard cell library may be configured by collecting individual standard cells that perform different functions.

Here, a flip-flop that performs a storage function is a basic circuit capable of maintaining one-bit information in two stable states using a structure of feeding delayed output for input back to the input. Basically, there are various flip-flops such as a D flip-flop, an RS flip-flop, a JK flip-flop, a T flip-flop, and the like.

The present disclosure provides a flip-flop capable of reducing power consumption upon latching an input data signal depending upon a clock signal, and a semiconductor system including the flip-flop.

According to an aspect of the present disclosure, a flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit, and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.

According to another aspect of the present disclosure, a flip-flop is connected to a power supply and a ground and generates a second data signal by receiving a first data signal and a clock signal from outside of the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit, and a third stage circuit. The first stage circuit generates a first internal signal through a first node using the first data signal and the clock signal. The second stage circuit generates a second internal signal through a second node using the first internal signal, the clock signal, and a feedback signal that is generated using the first internal signal. The third stage circuit generates the second data signal by latching the second internal signal using the second internal signal and the clock signal. The first stage circuit receives the feedback signal and prevents the first node from floating by grounding the first node or connecting the first node to the power supply, based on the feedback signal.

Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1A is a block diagram of a flip-flop according to an embodiment;

FIG. 1B is a block diagram of a flip-flop according to another embodiment;

FIG. 2A is a circuit diagram which illustrates a general flip-flop, and FIGS. 2B to 2C are tables which illustrate characteristics of the general flip-flop in FIG. 2A ;

FIG. 3A is a table illustrating operations of a flip-flop capable of effectively reducing power consumption, according to an embodiment;

FIG. 3B is a Karnaugh map illustrating the relationship between signals relating to a second stage circuit of a flip-flop according to an embodiment;

FIGS. 3C to 3E are block diagrams of flip-flops capable of performing the operations shown in the table of FIG. 3A , according to an embodiment;

FIGS. 4A and 4C are circuit diagrams which each illustrate a flip-flop, and FIG. 4B is a graph which illustrates operations of a flip-flop according to an embodiment in order to solve the problem described with reference to FIG. 2B ;

FIG. 5 is a block diagram of a flip-flop according to an embodiment in order to solve the problem described with reference to FIG. 2C ;

FIG. 6 is a circuit diagram illustrating a first stage circuit of FIG. 5 , according to an embodiment, in detail;

FIG. 7 is a circuit diagram illustrating a flip-flop according to an embodiment in detail;

FIGS. 8A to 8D are diagrams illustrating various modifications of a second stage circuit of FIG. 7 ;

FIG. 9 is a block diagram of a flip-flop according to a further embodiment;

FIGS. 10A to 10F are circuit diagrams illustrating various embodiments of the flip-flop shown in FIG. 9 ;

FIG. 11A shows Karnaugh maps illustrating the relationship between signals relating to a second stage circuit of a flip-flop according to an embodiment, and FIG. 11B shows relational expressions for a second internal signal derived from the Karnaugh maps of FIG. 11A ; and

FIG. 12 is a schematic block diagram of a semiconductor system including a flip-flop according to an embodiment.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 1A is a block diagram of a flip-flop according to an embodiment.

Referring to FIG. 1A , a flip-flop 100 a may include a first stage circuit 110 a, a second stage circuit 120 a, and a third stage circuit 130 a. The first stage circuit 110 a may include a first pull-up circuit (pull-up circuit 1 , PUC 1 ) 112 a and a first pull-down circuit (pull-down circuit 1 , PDC 1 ) 114 a. The first pull-up circuit 112 a may be connected between a power supply V DD and a first node ND 1 . The first pull-down circuit 114 a may be connected between the first node ND 1 and a ground GND.

In an embodiment, the first pull-up circuit 112 a and the first pull-down circuit 114 a may generate a first internal signal NET 1 through the first node ND 1 . The first pull-up circuit 112 a may receive a first data signal D and a clock signal CK. The first data signal D may be referred to as an input data signal received by the flip-flop 100 a. The first pull-up circuit 112 a may precharge the first node ND 1 with the power supply V DD by forming at least one current path between the power supply V DD and the first node ND 1 , based on the first data signal D and the clock signal CK. The first stage circuit 110 a may provide the first internal signal NET 1 at a high level to the second stage circuit 120 a through the precharged first node ND 1 . The first pull-down circuit 114 a may receive the first data signal D and the clock signal CK. The first pull-down circuit 114 a may discharge the first node ND 1 by forming at least one current path between the first node ND 1 and the ground GND, based on the first data signal D and the clock signal CK. The first stage circuit 110 a may provide the first internal signal NET 1 at a low level to the second stage circuit 120 a through the discharged first node ND 1 .

In an embodiment, the second stage circuit 120 a may include a second pull-up circuit 122 a and a second pull-down circuit 124 a. The second pull-up circuit 122 a may be connected between the power supply V DD and a second node ND 2 . The second pull-down circuit 124 a may be connected between the second node ND 2 and the ground GND. The second pull-up circuit 122 a and the second pull-down circuit 124 a may generate a second internal signal NET 2 through the second node ND 2 . The second pull-up circuit 122 a may receive the first internal signal NET 1 , the clock signal CK, and a first feedback signal FB 1 . The second pull-up circuit 122 a may precharge the second node ND 2 with the power supply V DD by forming at least one current path between the power supply V DD and the second node ND 2 , based on the first internal signal NET 1 , the clock signal CK, and the first feedback signal FB 1 . The second stage circuit 120 a may provide the second internal signal NET 2 at the high level to the third stage circuit 130 a through the precharged second node ND 2 . The second pull-down circuit 124 a may discharge the second node ND 2 by forming at least one current path between the second node ND 2 and the ground GND, based on the first internal signal NET 1 , the clock signal CK, and the first feedback signal FB 1 . The second stage circuit 120 a may provide the second internal signal NET 2 at the low level to the third stage circuit 130 a through the discharged second node ND 2 .

In addition, in an embodiment, to reduce power consumption when the second stage circuit 120 a generates the second internal signal NET 2 , the second pull-up circuit 122 a may cut off the at least one current path between the power supply V DD and the second node ND 2 , based on the first feedback signal FB 1 . Specifically, the second pull-up circuit 122 a may include a switch device controlled to be turned on/off by the first feedback signal FB 1 . The second pull-up circuit 122 a may turn off the switch device to cut off the at least one current path between the power supply V DD and the second node ND 2 . That is, the second pull-up circuit 122 a allows the second node ND 2 not to be electrically connected to the power supply V DD , based on the first feedback signal FB 1 , thereby preventing an unnecessary precharge operation. This may lead to an effect of reducing the power consumption of the flip-flop 100 a. In an embodiment, the first feedback signal FB 1 may include a signal generated using an output signal NET 2 of the second stage circuit 120 a . Further, the first feedback signal FB 1 may further include a signal generated using an output signal Q of the third stage circuit 130 a.

In another embodiment, when the second stage circuit 120 a generates the second internal signal NET 2 , for the second node ND 2 not to float, the second pull-up circuit 122 a may form the at least one current path between the power supply V DD and the second node ND 2 , based on the first internal signal NET 1 and the first feedback signal FB 1 . When the second internal signal NET 2 is at the high level, the second node ND 2 may always be electrically connected to the power supply V DD . In addition, the second pull-down circuit 124 a may form the at least one current path between the second node ND 2 and the ground GND, based on the clock signal CK and the first feedback signal FB 1 . When the second internal signal NET 2 is at the low level, the second node ND 2 may always be electrically connected to the ground GND. That is, when the second stage circuit 120 a generates the second internal signal NET 2 , the second node ND 2 may always be connected to the power supply V DD or the ground GND, thereby preventing the second node ND 2 from floating. As a result, the flip-flop 100 a may be made resistant to noise.

The third stage circuit 130 a may include a latch circuit 132 a. The latch circuit 132 a may receive the second internal signal NET 2 and the clock signal CK. The latch circuit 132 a may generate a second data signal Q by latching the second internal signal NET 2 depending upon the clock signal CK. The second data signal Q may be referred to as an output data signal that is output by the flip-flop 100 a. In an embodiment, the latch circuit 132 a may latch the second internal signal NET 2 when the clock signal CK is at the high level. The second stage circuit 120 a may cut off the at least one current path between the power supply V DD and the second node ND 2 , based on the first feedback signal FB 1 , when the clock signal CK is at the low level. The latch circuit 132 a may output the latched second internal signal NET 2 as the second data signal Q. Although the third stage circuit 130 a is schematically shown as including the latch circuit 132 a for convenience in FIG. 1A , the third stage circuit is not limited thereto. Like the first stage circuit 110 a and the second stage circuit 120 a, the third stage circuit 130 a may be variously realized to include a pull-up circuit and a pull-down circuit.

FIG. 1B is a block diagram of a flip-flop according to another embodiment.

Referring to FIG. 1B , a flip-flop 100 b may include a first stage circuit 110 b, a second stage circuit 120 b, and a third stage circuit 130 b. Among components shown in FIG. 1B , the first stage circuit 110 b and the third stage circuit 130 b, which are different from those in FIG. 1A , will be mainly described hereinafter.

The first stage circuit 110 b may include a first pull-up circuit 112 b and a first pull-down circuit 114 b. The first pull-up circuit 112 b and the first pull-down circuit 114 b may generate the first internal signal NET 1 through the first node ND 1 . The first pull-up circuit 112 b may receive the first data signal D, the clock signal CK, and a second feedback signal FB 2 . In an embodiment, when the first internal signal NET 1 is at the high level, for the first node ND 1 to always be electrically connected to the power supply V DD , the first pull-up circuit 112 b may form at least one current path between the power supply V DD and the first node ND 1 , based on the first data signal D and the second feedback signal FB 2 . When the first internal signal NET 1 is at the high level, the first node ND 1 may always be electrically connected to the power supply V DD . In addition, when the first internal signal NET 1 is at the low level, for the first node ND 1 to always be electrically connected to the ground GND, the first pull-down circuit 114 b may form at least one current path between the first node ND 1 and the ground GND, based on the clock signal CK and the second feedback signal FB 2 . When the first internal signal NET 1 is at the low level, the first node ND 1 may always be electrically connected to the ground GND. By this configuration, when the first stage circuit 110 b generates the first internal signal NET 1 , the first node ND 1 may always be connected to the power supply V DD or the ground GND, thereby preventing the first node ND 1 from floating. As a result, the flip-flop 100 b may be made resistant to noise. In an embodiment, the second feedback signal FB 2 may include a signal generated using an output signal NET 1 of the first stage circuit 110 b.

The third stage circuit 130 b may include a latch circuit 132 b and an inverter 134 b. The latch circuit 132 b may receive the second internal signal NET 2 and the clock signal CK. The latch circuit 132 b may generate a third internal signal NET 3 by latching the second internal signal NET 2 depending upon the clock signal CK. The inverter 134 b may generate the second data signal Q by inverting the third internal signal NET 3 . However, a configuration shown in FIG. 1B is merely an example, and the third stage circuit 130 b may include multiple buffers to improve driving capabilities of the third stage circuit 130 b with respect to the second data signal Q.

FIG. 2A is a circuit diagram which illustrates a general flip-flop, and FIGS. 2B to 2C are tables which illustrate characteristics of the general flip-flop in FIG. 2A .

Referring to FIG. 2A , a general flip-flop 200 may include a first stage circuit 210 , a second stage circuit 220 , and a third stage circuit 230 . The first stage circuit 210 may include a transistor P 1 , a transistor P 2 , and a transistor N 1 . The first stage circuit 210 may receive the first data signal D and the clock signal CK and generate the first internal signal NET 1 through the first node ND 1 between the transistor P 2 and the transistor N 1 , based on the first data signal D and the clock signal CK. The second stage circuit 220 may include a transistor P 3 , a transistor N 2 , and a transistor N 3 . The second stage circuit 220 may receive the first internal signal NET 1 and the clock signal CK and generate the second internal signal NET 2 through the second node ND 2 between the transistor P 3 and the transistor N 2 , based on the first internal signal NET 1 and the clock signal CK. The third stage circuit 230 may include a transistor P 4 , a transistor N 4 , and a transistor N 5 . The third stage circuit 230 may receive the second internal signal NET 2 and the clock signal CK and generate the second data signal Q through a third node ND 3 between the transistor P 4 and the transistor N 4 , based on the second internal signal NET 2 and the clock signal CK.

Referring to FIGS. 2A and 2B , Table 1 shows the relationship between levels of the first internal signal NET 1 , the clock signal CK, the second internal signal NET 2 , and the second data signal Q of FIG. 2A .

First, the case that an unnecessary precharge operation occurs at the second node ND 2 in the second stage circuit 220 will be described with reference to Case 1 . When the first internal signal NET 1 is at the high level and the clock signal CK is at the high level, the transistor P 3 of the second stage circuit 220 is turned off, and the transistor N 2 and the transistor N 3 are turned on, whereby a current path CP may be formed between the second node ND 2 and the ground GND. Thus, the second node ND 2 is discharged, whereby the second stage circuit 220 may generate the second internal NET 2 at the low level through the second node ND 2 . When the second internal signal NET 2 is at the low level and the clock signal CK is at the high level, the transistor P 4 of the third stage circuit 230 is turned on, and the transistor N 4 and the transistor N 5 are turned off, whereby a current path may be formed between the third node ND 3 and the power supply V DD . Thus, the third node ND 3 is precharged, whereby the third stage circuit 230 may generate the second data signal Q at the high level through the third node ND 3 .

Next, when the first internal signal NET 1 maintains the high level and the clock signal CK transits from the high level to the low level, the transistor P 3 of the second stage circuit 220 is turned on, and the transistor N 2 and the transistor N 3 are turned off, whereby a current path CP′ may be formed between the power supply V DD and the second node ND 2 . Thus, the second node ND 2 is precharged, whereby the second stage circuit 220 may generate the second internal signal NET 2 at the high level through the second node ND 2 . When the second internal signal NET 2 is at the high level and the clock signal is at the low level, since the transistor P 4 and the transistor N 4 of the third stage circuit 230 are turned off, the third node ND 3 may maintain a previous precharge state. Thus, the third stage circuit 230 may output the second data signal Q maintaining the high level through the third node ND 3 even when the clock signal CK transits from the high level to the low level.

Next, when the first internal signal NET 1 maintains the high level and the clock signal CK transits from the low level to the high level, the current path CP is formed again between the second node ND 2 and the ground GND in the second stage circuit 220 , whereby the second node ND 2 may be discharged. Even in this case, the second data signal Q output by the third stage circuit 230 may still maintain the high level.

As such, upon the operation of the general flip-flop 200 , even though the second data signal Q is maintained at a constant level, since unnecessary precharge operations and/or discharge operations are repeated, there is a problem of an increase in the power consumption of the flip-flop 200 .

The case that the second node ND 2 of the second stage circuit 220 floats will be described with reference to Case 2 . When the first internal signal NET 1 is at the low level and the clock signal CK is at the high level, the transistor P 3 and the transistor N 2 of the second stage circuit 220 are turned off, whereby the second node ND 2 may float.

The case that the first node ND 1 of the first stage circuit 210 floats will be described with reference to FIGS. 2A and 2C . In Case 3 where the first data signal D is at the low level and the clock signal CK is at the high level, the transistor P 2 and the transistor N 1 of the first stage circuit 210 are turned off, whereby the first node ND 1 may float.

In Case 2 and Case 3 , the first node ND 1 or the second node ND 2 may float. In the general flip-flop 200 , when the first node ND 1 or the second node ND 2 floats, a voltage level state of the first node ND 1 or the second node ND 2 may be changed by noise external or internal to the general flip-flop 200 due to the floating of the first node ND 1 or the second node ND 2 . This results in a problem of the deterioration in the reliability of the operation of the flip-flop 200 .

FIG. 3A is a table illustrating operations of a flip-flop capable of effectively reducing power consumption, according to an embodiment. FIG. 3B is a Karnaugh map illustrating the relationship between signals relating to a second stage circuit of a flip-flop according to an embodiment. FIGS. 3C to 3E are block diagrams of flip-flops capable of performing operations shown in the table of FIG. 3A , according to an embodiment.

Referring to FIG. 3A , when the first internal signal NET 1 is at the high level and the clock signal CK is at the low level, a second stage circuit according to an embodiment may generate the second internal signal NET 2 having a previous value, as compared with FIG. 2B . Thus, when the first internal signal NET 1 and the clock signal CK are at the same level, the second stage circuit may output a signal corresponding to the first internal signal NET 1 as the second internal signal NET 2 . For example, the second internal signal NET 2 may be a signal obtained by inverting the first internal signal NET 1 . In addition, when the first internal signal NET 1 and the clock signal CK are at different levels, the second stage circuit may output the second internal signal NET 2 having the previous value. However, this is merely an example, and the output of the second stage circuit is not limited thereto. When the first internal signal NET 1 and the clock signal CK are at different levels, the second stage circuit may output the signal corresponding to the first internal signal NET 1 as the second internal signal NET 2 . When the first internal signal NET 1 and the clock signal CK are at the same level, the second stage circuit may output the second internal signal NET 2 having the previous value.

The second stage circuit according to an embodiment may cut off the current path CP′ of FIG. 2A , which is formed when the first internal signal NET 1 is at the high level and the clock signal CK is at the low level, thereby preventing an unnecessary precharge operation.

Referring to FIG. 3B , to satisfy operations of the second stage circuit, the relationship between signals NET 1 , CK, and NET 2 N relating to the second stage circuit may be established, like in a logic function in the form of a truth table shown in a Karnaugh map M. However, the Karnaugh map M shown in FIG. 3B is merely an example, without being limited thereto, and may vary depending upon a configuration of the second stage circuit. In an embodiment, as a result of minimizing the logic function of the Karnaugh map M of FIG. 3B , the relationship between the first internal signal NET 1 , the clock signal CK, and the second internal signal NET 2 may be represented as follows.

NET2= (NET1 |CK )&(NET1|NET2 N )&(CK|NET2 N )

Referring to FIG. 3C , a flip-flop 300 a according to an embodiment may include a first stage circuit 310 a, a second stage circuit 320 a, and a third stage circuit 330 a. To generate the second internal signal NET 2 satisfying the above relationship, the second stage circuit 320 a may include a first OR gate 331 a, a second OR gate 332 a, a third OR gate 333 a, an AND gate 334 a , and an inverter 335 a. The first OR gate 331 a may receive the first internal signal NET 1 and the clock signal CK. The second OR gate 332 a may receive the first internal signal NET 1 and a feedback signal NET 2 N. The third OR gate 333 a may receive the clock signal CK and the feedback signal NET 2 N. The AND gate 334 a may receive an output signal of the first OR gate 331 a, an output signal of the second OR gate 332 a, and an output signal of the third OR gate 333 a. The inverter 335 a may receive the second internal signal NET 2 from the AND gate 334 a . The inverter 335 a may generate the feedback signal NET 2 N by inverting the second internal signal NET 2 . The second stage circuit 320 a may prevent an unnecessary precharge operation when generating the second internal signal NET 2 , based on the feedback signal NET 2 N, as described above.

Referring to FIG. 3D , a second stage circuit 320 b may further include an XOR gate 336 b compared to the second stage circuit 320 a of FIG. 3C . The XOR gate 336 b may receive an output signal of an AND gate 334 b and receive a reset signal Reset from outside of the second stage circuit 320 b. In an embodiment, the XOR gate 336 b may output the second internal signal NET 2 that is reset, when receiving the reset signal Reset at the high level.

Referring to FIG. 3E , a latch circuit 332 c of a third stage circuit 330 c may further receive a set signal Set, unlike a latch circuit of a third stage circuit 330 a of FIG. 3C . In an embodiment, the latch circuit 332 c may output the second data signal Q at a preset level, when receiving the set signal Set at the high level.

FIGS. 4A and 4C are circuit diagrams which each illustrate a flip-flop, and FIG. 4B is a graph which illustrates operations of a flip-flop according to an embodiment in order to solve the problem described with reference to FIG. 2B .

Referring to FIG. 4A , a flip-flop 400 may include a first stage circuit 410 , a second stage circuit 420 , and a third stage circuit 430 . Since the first stage circuit 410 and the third stage circuit 430 respectively correspond to the first stage circuit 110 a and the third stage circuit 130 a , which have been described with reference to FIG. 1A , descriptions thereof will be omitted. The second stage circuit 420 may include a second pull-up circuit 422 , a second pull-down circuit 424 , and an inverter 426 . The second pull-up circuit 422 may be connected between the power supply V DD and the second node ND 2 . The second pull-down circuit 424 may be connected between the second node ND 2 and the ground GND. The second pull-up circuit 422 may include multiple PMOS transistors P 3 to P 8 . The second pull-up circuit 422 may form multiple current paths CP 1 to CP 3 between the power supply V DD and the second node ND 2 using the PMOS transistors P 3 to P 8 . The second pull-down circuit 424 may include multiple NMOS transistors N 2 to N 7 . The second pull-down circuit 424 may form multiple current paths using the NMOS transistors N 2 to N 7 . However, this is merely an example, and the second pull-up circuit 422 and the second pull-down circuit 424 may include various kinds of transistors.

The second pull-up circuit 422 and the second pull-down circuit 424 may generate the second internal signal NET 2 through the second node ND 2 . The inverter 426 may receive the second internal signal NET 2 and generate the feedback signal NET 2 N.

In an embodiment, the transistor N 5 and the transistor N 6 of the second pull-down circuit 424 may be controlled to be turned on/off by the clock signal CK. The transistor N 2 and the transistor N 7 may be controlled to be turned on/off by the first internal signal NET 1 . The transistor N 3 and the transistor N 4 may be controlled to be turned on/off by the feedback signal NET 2 N. The transistor P 3 and the transistor P 5 of the second pull-up circuit 422 may be controlled to be turned on/off by the clock signal CK. The transistor P 4 and the transistor P 7 may be controlled to be turned on/off by the first internal signal NET 1 . The transistor P 6 and the transistor P 8 may be controlled to be turned on/off by the feedback signal NET 2 N. That is, a first current path CP 1 and a second current path CP 2 , which are formed by the second pull-up circuit 422 , may be cut off by the feedback signal NET 2 N.

Referring again to FIG. 3A , when the first internal signal NET 1 is at the high level and the clock signal CK is at the high level, the second internal signal NET 2 may be at the low level. Next, when the first internal signal NET 1 maintains the high level and the clock signal CK transits from the high level to the low level, the second pull-up circuit 420 may cut off a current path, based on the feedback signal NET 2 N, thereby preventing an unnecessary precharge operation for the second node ND 2 . For example, since the feedback signal NET 2 N is at the high level although the transistor P 5 is turned on by the clock signal CK that is at the low level, the transistor P 6 is turned off, whereby the second current path CP 2 may be cut off. By this configuration of the second pull-up circuit 422 , the problem described with reference to Case 1 of FIG. 2B may be solved.

In addition, under the condition of the first internal signal NET 1 at the low level, the clock signal CK at the high level, and the second internal signal NET 2 at the low level, when the first internal signal NET 1 maintains the low level and the clock signal CK transits to the low level, the transistor P 3 and the transistor P 4 are turned on, whereby a third current path CP 3 may be formed. The second node ND 2 may be precharged through the third current path CP 3 , and the second internal signal NET 2 at the high level may be generated through the second node ND 2 .

Referring to FIG. 4B , when a first data signal D and the first internal signal NET 1 are respectively at the low level and the high level and the clock signal CK cyclically transits between the high level and the low level, the second internal signal NET 2 may be kept constant at the low level. That is, as described with reference to FIG. 4A , the second pull-up circuit 422 may cut off the second current path CP 2 to prevent the second node ND 2 from being unnecessarily precharged.

Referring to FIG. 4C , the second pull-up circuit 422 and the second pull-down circuit 424 , according to an embodiment, may prevent the second node ND 2 from floating. Referring again to FIG. 3A , when the first internal signal NET 1 , the clock signal CK, and the second internal signal NET 2 are respectively at the low level, the high level, and the high level and the second node ND 2 is precharged, the transistor P 7 of the second pull-up circuit 422 is turned on by the first internal signal NET 1 , and the transistor P 8 is turned on by the feedback signal NET 2 N that is at the low level, whereby the first current path CP 1 may be formed between the power supply V DD and the second node ND 2 . Thus, the second node ND 2 may be stably kept precharged by the second pull-up circuit 422 .

In addition, when the first internal signal NET 1 , the clock signal CK, and the second internal signal NET 2 are respectively at the low level, the high level, and the low level and the second node ND 2 is discharged, the transistor N 5 and the transistor N 6 of the second pull-down circuit 424 are turned on by the clock signal CK, and the transistor N 3 and the transistor N 4 are turned on by the feedback signal NET 2 N that is at the high level, whereby a fourth current path CP 4 and a fifth current path CP 5 may be formed. Thus, the second node ND 2 may be stably kept discharged by the second pull-down circuit 424 .

By this configuration of the second pull-up circuit 422 and the second pull-down circuit 424 , the problem described with reference to Case 2 of FIG. 2B may be solved.

FIG. 5 is a block diagram of a flip-flop according to an embodiment in order to solve the problem described with reference to FIG. 2C .

Referring to FIG. 5 , a flip-flop 500 a may include a first stage circuit 510 a, a second stage circuit 520 a, and a third stage circuit 530 a. As described with reference to FIG. 2C , for the first node ND 1 not to float, the first stage circuit 510 a according to an embodiment may include an AND gate 511 a, a NOR gate 513 a, and an inverter 515 a. The AND gate 511 a may receive the clock signal CK and a feedback signal NET 1 N. The NOR gate 513 a may receive an output signal of the AND gate 511 a and the first data signal D. The inverter 515 a may receive the first internal signal NET 1 from the NOR gate 513 a. The inverter 515 a may generate the feedback signal NET 1 N by inverting the first internal signal NET 1 .

FIG. 6 is a circuit diagram illustrating the first stage circuit of FIG. 5 , according to an embodiment, in detail.

Referring to FIG. 6 , a first stage circuit 510 b according to an embodiment may include a first pull-up circuit 512 b, a first pull-down circuit 514 a, and an inverter 515 b. The first pull-up circuit 512 b may include multiple PMOS transistors P 1 to P 3 , and may generate multiple current paths between the power supply V DD and the first node ND 1 using the PMOS transistors P 1 to P 3 . The first pull-down circuit 514 a may include multiple NMOS transistors N 1 to N 3 . The first pull-down circuit 514 a may generate multiple current paths between the first node ND 1 and the ground GND using the NMOS transistors N 1 to N 3 . However, this is merely an example, and the first pull-up circuit 512 b and the first pull-down circuit 514 a may include various kinds of transistors.

The first pull-up circuit 512 b and the first pull-down circuit 514 a may generate the first internal signal NET 1 through the first node ND 1 . The inverter 515 b may receive the first internal signal NET 1 and generate the feedback signal NET 1 N.

In an embodiment, the transistor P 1 of the first pull-up circuit 512 b may be controlled to be turned on/off by the first data signal D. The transistor P 2 may be controlled to be turned on/off by the clock signal CK. The transistor P 3 may be controlled to be turned on/off by the feedback signal NET 1 N. The transistor N 1 of the first pull-down circuit 514 a may be controlled to be turned on/off by the first data signal D. The transistor N 2 may be controlled to be turned on/off by the feedback signal NET 1 N. The transistor N 3 may be controlled to be turned on/off by the clock signal CK.

Referring again to FIG. 2C , when the first data signal D, the clock signal CK, and the first internal signal NET 1 are respectively at the low level, the high level, and the high level and the first node ND 1 is precharged, the transistor P 1 of the first pull-up circuit 512 b is turned on by the first data signal D, and the transistor P 3 is turned on by the feedback signal NET 1 N that is at the low level, whereby a current path may be formed between the power supply V DD and the first node ND 1 . Thus, the first node ND 1 may be stably kept precharged by the first pull-up circuit 512 b.

In addition, when the first data signal D, the clock signal CK, and the first internal signal NET 1 are respectively at the low level, the high level, and the low level and the first node ND 1 is discharged, the transistor N 2 of the first pull-down circuit 514 b is turned on by the feedback signal NET 1 N that is at the low level, and the transistor N 3 is turned on by the clock signal CK, whereby a current path may be formed between the first node ND 1 and the ground GND. Thus, the first node ND 1 may be stably kept discharged by the first pull-down circuit 514 b.

FIG. 7 is a circuit diagram illustrating a flip-flop according to an embodiment in detail.

Referring to FIG. 7 , a flip-flop 600 may include a first stage circuit 610 , a second stage circuit 620 , and a third stage circuit 630 . The first stage circuit 610 may correspond to the first stage circuit 510 b of FIG. 6 , and the second stage circuit 620 may correspond to the second stage circuit 420 of FIG. 4A .

By this configuration, when performing a latch operation for the first data signal D, the flip-flop 600 may prevent the first node ND 1 and the second node ND 2 from floating and prevent an unnecessary precharge operation for the second node ND 2 , thereby reducing the power consumption of the flip-flop 600 .

FIGS. 8A to 8D are diagrams illustrating various modifications of the second stage circuit of FIG. 7 .

Referring to FIG. 8A , a flip-flop 700 a may include a first stage circuit 710 a, a second stage circuit 720 a, and a third stage circuit 730 a. Hereinafter, components different from those of the flip-flop 600 shown in FIG. 7 will be mainly described. A second pull-down circuit 724 a of the second stage circuit 720 a may include: a transistor N 4 _ a and a transistor N 9 _ a , which are controlled to be turned on/off by the first internal signal NET 1 ; a transistor N 6 _ a and a transistor N 8 _ a , which are controlled to be turned on/off by the clock signal CK; and a transistor N 5 _ a and a transistor N 7 _ a , which are controlled to be turned on/off by the feedback signal NET 2 N. In this way, the second pull-down circuit 724 a may form a current path between the second node ND 2 and the ground GND using the transistor N 4 _ a and the transistor N 5 _ a , form a current path between the second node ND 2 and the ground GND using the transistor N 6 _ a and the transistor N 7 _ a , and form a current path between the second node ND 2 and the ground GND using the transistor N 8 _ a and the transistor N 9 _ a.

Referring to FIG. 8B , a second pull-up circuit 722 b and a second pull-down circuit 724 b of a second stage circuit 720 b may include transistors that are less in number compared to the transistors included in the second pull-up circuit 722 a and the second pull-down circuit 724 a of FIG. 8A , and may form various current paths through these transistors.

The second pull-up circuit 722 b may include: a transistor P 4 _ b and a transistor P 7 _ b , which are controlled to be turned on/off by the first internal signal NET 1 ; a transistor P 5 _ b controlled to be turned on/off by the clock signal CK; and a transistor P 6 _ b and a transistor P 8 _ b , which are controlled to be turned on/off by the feedback signal NET 2 N. In addition, a source of the transistor P 6 _ b may be connected to a drain of the transistor P 5 _ b.

The second pull-down circuit 724 b may include: a transistor N 5 _ b and a transistor N 8 _ b , which are controlled to be turned on/off by the first internal signal NET 1 ; a transistor N 4 _ b controlled to be turned on/off by the clock signal CK; and a transistor N 6 _ b and a transistor N 7 _ b , which are controlled to be turned on/off by the feedback signal NET 2 N. In addition, a source of the transistor N 4 _ b may be connected to a drain of the transistor N 6 _ b.

Referring to FIG. 8C , a second pull-up circuit 722 c of a second stage circuit 720 c may have a different connection configuration from the second pull-up circuits 722 a and 722 b of FIGS. 8A and 8B , thereby forming various current paths. The second pull-up circuit 722 c may include: a transistor P 6 _ c and a transistor P 7 _ c , which are controlled to be turned on/off by the first internal signal NET 1 ; a transistor P 4 _ c and a transistor P 5 _ c , which are controlled to be turned on/off by the clock signal CK; and a transistor P 8 _ c and a transistor P 9 _ c , which are controlled to be turned on/off by the feedback signal NET 2 N. A source of the transistor P 7 _ c may be connected to a drain of the transistor P 5 _ c , and a source of the transistor P 4 _ c may be connected to a drain of the transistor P 8 _ c . A source of the transistor P 5 _ c may be connected to a drain of the transistor P 9 _ c . A source of the transistor P 8 _ c may be connected to a drain of the transistor P 6 _ c.

Referring to FIG. 8D , a second pull-up circuit 722 d and a second pull-down circuit 724 d of a second stage circuit 720 d may include transistors that are less in number compared to the transistors included in the second pull-up circuit 722 c and the second pull-down circuit 724 c of FIG. 8C , respectively. The second pull-up circuit 722 d and the second pull-down circuit 724 d may form various current paths through these transistors. The second pull-up circuit 722 d may include: a transistor P 5 _ d and a transistor P 6 _ d , which are controlled to be turned on/off by the first internal signal NET 1 ; a transistor P 4 _ d controlled to be turned on/off by the clock signal CK; and a transistor P 7 _ d and a transistor P 8 _ d , which are controlled to be turned on/off by the feedback signal NET 2 N. A source of the transistor P 7 _ d may be connected to a drain of the transistor P 5 _ d , and a source of the transistor P 4 _ d may be connected to a drain of the transistor P 8 _ d.

The second pull-down circuit 724 d may include: a transistor N 4 _ d and a transistor N 8 _ d , which are controlled to be turned on/off by the first internal signal NET 1 ; a transistor N 7 _ d controlled to be turned on/off by the clock signal CK; and a transistor N 5 _ d and a transistor N 6 _ d , which are controlled to be turned on/off by the feedback signal NET 2 N. A source of the transistor N 7 _ d may be connected to a drain of the transistor N 6 _ d , and a source of the transistor N 5 _ d may be connected to a drain of the transistor N 8 _ d.

FIG. 9 is a block diagram of a flip-flop according to a further embodiment.

Referring to FIG. 9 , a flip-flop 800 may include a first stage circuit 810 , a second stage circuit 820 , and a third stage circuit 830 . Hereinafter, a difference of the flip-flop 800 from the flip-flop 100 b of FIG. 1B will be mainly described. The second stage circuit 820 of the flip-flop 800 of FIG. 9 may include a second pull-up circuit 822 and a second pull-down circuit 824 . The second pull-up circuit 822 and the second pull-down circuit 824 may receive the first internal signal NET 1 , the clock signal CK, and the first feedback signal FB 1 . The first feedback signal FB 1 may be generated based on a signal generated from the second stage circuit 820 and a signal generated from the third stage circuit 830 . In an embodiment, the first feedback signal FB 1 may include a signal NET 2 N, which is generated based on the second internal signal NET 2 generated through the second node ND 2 of the second stage circuit 820 , and the third internal signal NET 3 generated from a latch circuit 832 of the third stage circuit 830 . However, this is merely an example, and the first feedback signal is not limited thereto. The first feedback signal FB 1 may be generated based only on a signal generated from the third stage circuit 830 . The second pull-up circuit 822 may prevent an unnecessary precharge operation for the second node ND 2 when generating the second internal signal NET 2 , based on the first feedback signal FB 1 . In addition, the second pull-up circuit 822 and the second pull-down circuit 824 may prevent the second node ND 2 from floating, based on the feedback signal FB 1 . Descriptions regarding this have been made above and thus will be omitted.

FIGS. 10A to 10F are circuit diagrams illustrating various embodiments of the flip-flop shown in FIG. 9 .

Referring to FIG. 10A , a configuration of a flip-flop 900 a may correspond to the configuration of the flip-flop 700 b of FIG. 8B . However, unlike the second pull-up circuit 722 b of FIG. 8B , a second pull-up circuit 922 a may not include a transistor receiving an inverted second internal signal NET 2 N. In an embodiment, a transistor P 6 _ b ′ and a transistor P 8 _ b ′ of the second pull-up circuit 922 a may receive the third internal signal NET 3 and be controlled to be turned on/off by the third internal signal NET 3 . In addition, unlike in the second pull-down circuit 724 b of FIG. 8B , a transistor N 7 _ b ′ of a second pull-down circuit 924 a may receive the third internal signal NET 3 and be controlled to be turned on/off by the third internal signal NET 3 .

Referring to FIG. 10B , a configuration of a flip-flop 900 b may correspond to the configuration of the flip-flop 900 a of FIG. 10A . However, unlike the second pull-up circuit 922 a of FIG. 10A , a second pull-up circuit 922 b may include a transistor receiving the inverted second internal signal NET 2 N, and a transistor receiving the third internal signal NET 3 . In an embodiment, a transistor P 6 _ b ′ of the second pull-up circuit 922 b may receive the inverted second internal signal NET 2 N and be controlled to be turned on/off by the inverted second internal signal NET 2 N. A transistor P 8 _ b ′ of the second pull-up circuit 922 b may receive the third internal signal NET 3 and be controlled to be turned on/off by the third internal signal NET 3 .

Referring to FIG. 10C , a configuration of a flip-flop 900 c may correspond to the configuration of the flip-flop 700 c of FIG. 8C . However, unlike the second pull-up circuit 722 c of FIG. 8C , a second pull-up circuit 922 c may not include a transistor receiving the inverted second internal signal NET 2 N. In an embodiment, a transistor P 8 _ c ′ and a transistor P 9 _ c ′ of the second pull-up circuit 922 c may receive the third internal signal NET 3 and be controlled to be turned on/off by the third internal signal NET 3 . In addition, unlike in the second pull-down circuit 724 c of FIG. 8C , a transistor N 5 _ c ′ of a second pull-down circuit 924 c may receive the third internal signal NET 3 and be controlled to be turned on/off by the third internal signal NET 3 .

Referring to FIG. 10D , a configuration of a flip-flop 900 d may correspond to the configuration of the flip-flop 700 d of FIG. 8D . However, unlike the second pull-up circuit 722 d of FIG. 8D , a second pull-up circuit 922 d may not include a transistor receiving the inverted second internal signal NET 2 N. In an embodiment, a transistor P 7 _ d ′ and a transistor P 8 _ d ′ of the second pull-up circuit 922 d may receive the third internal signal NET 3 and be controlled to be turned on/off by the third internal signal NET 3 . In addition, unlike in the second pull-down circuit 724 d of FIG. 8D , a transistor N 5 _ d ′ of a second pull-down circuit 924 d may receive the third internal signal NET 3 and be controlled to be turned on/off by the third internal signal NET 3 .

Referring to FIG. 10E , a configuration of a flip-flop 900 e may correspond to the configuration of the flip-flop 900 d of FIG. 10D . However, unlike the second pull-up circuit 922 d of FIG. 10D , a second pull-up circuit 922 e may include a transistor receiving the inverted second internal signal NET 2 N and a transistor receiving the third internal signal NET 3 . In an embodiment, a transistor P 7 _ d ′ of the second pull-up circuit 922 e may receive the inverted second internal signal NET 2 N and be controlled to be turned on/off by the inverted second internal signal NET 2 N. A transistor P 8 _ d ′ of the second pull-up circuit 922 e may receive the third internal signal NET 3 and be controlled to be turned on/off by the third internal signal NET 3 .

Referring to FIG. 10F , a configuration of a flip-flop 900 f may correspond to the configuration of the flip-flop 900 a of FIG. 10A . However, unlike the second pull-down circuit 924 d of FIG. 10D , a second pull-down circuit 924 f may include: a transistor N 5 _ f and a transistor N 9 _ f , which are controlled to be turned on/off by the first internal signal NET 1 ; a transistor N 4 _ f controlled to be turned on/off by the clock signal CK; a transistor N 6 _ f controlled to be turned on/off by the inverted second internal signal NET 2 N; and a transistor N 7 _ f and a transistor N 8 _ f , which are controlled to be turned on/off by the third internal signal NET 3 . A source of the transistor N 4 _ f may be connected to a drain of the transistor N 6 _ f.

FIG. 11A shows Karnaugh maps illustrating the relationship between signals relating to a second stage circuit of a flip-flop according to an embodiment, and FIG. 11B shows relational expressions for a second internal signal derived from the Karnaugh maps of FIG. 11A .

As described above, a second stage circuit may include a second pull-up circuit PUC 2 and a second pull-down circuit PDC 2 . The second pull-up circuit PUC 2 may form a current path between a power supply and a second node, based on the first internal signal NET 1 , the clock signal CK, and the feedback signals NET 2 N and NET 3 , thereby generating the second internal signal NET 2 at the high level. The second pull-down circuit PDC 2 may form a current path between the second node and a ground, based on the first internal signal NET 1 , the clock signal CK, and the feedback signals NET 2 N and NET 3 , thereby generating the second internal signal NET 2 at the low level.

Referring to FIG. 11A , to satisfy operations of the second pull-up circuit PUC 2 and the second pull-down circuit PDC 2 of the second stage circuit, the relationship between signals NET 1 , CK, NET 2 N, and NET 3 relating to the second pull-up circuit PUC 2 may be established, like in a logic function in the form of a truth table shown in a first Karnaugh map M_PUC 2 . In addition, the relationship between the signals NET 1 , CK, NET 2 N, and NET 3 relating to the second pull-down circuit PDC 2 may be established, like in a logic function in the form of a truth table shown in a second Karnaugh map M_PDC 2 . However, the Karnaugh maps M_PUC 2 and M_PDC 2 shown in FIG. 11A are merely examples, without being limited thereto, and may vary depending upon a configuration of the second stage circuit.

Referring to FIG. 11B , in an embodiment, as a result of minimizing the logic function of the first Karnaugh map M_PUC 2 of FIG. 11A , the second pull-up circuit PUC 2 may be realized into a circuit diagram corresponding to a first expression {circle around ( 1 )}, and furthermore, may be realized into a circuit diagram corresponding to an expression including the first expression {circle around ( 1 )} and at least one of second to fourth expressions {circle around ( 2 )} to {circle around ( 4 )}.

In addition, as a result of minimizing the logic function of the second Karnaugh map M_PDC 2 of FIG. 11A , the second pull-down circuit PDC 2 may be realized into a circuit diagram corresponding to a fifth expression {circle around ( 5 )}, and furthermore, may be realized into a circuit diagram corresponding to an expression including the fifth expression {circle around ( 5 )} and at least one of sixth to ninth expressions {circle around ( 6 )} to {circle around ( 9 )}.

FIG. 12 is a schematic block diagram of a semiconductor system including a flip-flop according to an embodiment.

A semiconductor system 1000 may be realized as a PC, a portable computer, a smart phone, a digital TV, or a home automation device.

The semiconductor system 1000 may include a CPU 1100 and memory 1200 , which are connected to each other through a system bus 1500 . The CPU 1100 may control overall operations of the memory 1200 . The CPU 1100 may include a flip-flop FF latching a signal processed by the CPU 1100 , and a logic circuit controlling the flip-flop FF. The memory 1200 may be realized as non-volatile memory, for example, ROM, which may store a program code capable of controlling operations of the CPU 1100 , or may be realized as volatile memory, for example, DRAM, which may store data. The memory 1200 includes a flip-flop FF latching data accessed by the memory 1200 , and a logic circuit (not shown) controlling the flip-flop FF. According to an embodiment, the semiconductor system 1000 may further include a first interface 1300 . The first interface 1300 may be an input/output interface. The input/output interface may be an output device such as a monitor or a printer, a pointing device such as a touchpad or a computer mouse, or an input device such as a keypad or a keyboard.

The first interface 1300 includes a flip-flop latching data, which is input and output by the first interface 1300 , and a logic circuit controlling the flip-flop. According to an embodiment, the semiconductor system 1000 may further include a second interface 1400 . The second interface 1400 may be a communication interface for communicating with the outside of the semiconductor system 1000 . For example, the communication interface may be an RF chip. The second interface 1400 includes a flip-flop latching data, which is transmitted and received by the second interface 1400 , and a logic circuit controlling the flip-flop.

The flip-flops according to the present disclosure, which have been described with reference to FIGS. 1 to 11 , may be applied to the flip-flops included in the CPU 1100 , the memory 1200 , and the first and second interfaces 1300 and 1400 .

While the concepts described herein have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.