Fast encoding method and device for Reed-Solomon codes with a small number of redundancies

The present invention relates to the field of encoding technique(s), in particular to a fast encoding method and device suitable for the Reed-Solomon codes with a small number of redundancies.

Reed-Solomon code (referred to as RS code hereinafter) is a type of maximum distance separable code, which now has been widely used in storage and communication systems. The current methods for encoding RS codes generally include polynomial division, matrix-vector multiplication-based and fast Fourier transform-based algorithms.

Wherein, with respect to the RS encoding based on the polynomial division, the generator polynomial is defined as: g(X)=(X−a)(X−a 2 ) . . . (X−a 3 ), where g(X) is the generator polynomial, a is the primitive element of the finite field GF(2 m ), and s is the number of redundant symbols. Let o=[o 1 , o 2 . . . o k ] denote k message symbols, and then the polynomial for message symbols is defined as o(X)=o 1 o 2 X+. . . +o k X k−1 , and the redundant symbol polynomial r(X) can be obtained by the formula: r(X)=o(X)X s (mod g(X)), where r(X) is the remainder polynomial. However, the encoding based on polynomial division requires around sk finite field additions and sk finite field multiplications, and thus, the computational complexity is O(sk×M q ), where M q is the complexity of a multiplication/addition in a finite field.

For RS encoding based on matrix-vector multiplication, it requires a given generator matrix G=[P I] where I is a k×k identity matrix, P is a given k×s matrix, s denotes the number of redundant symbols, and k denotes the number of message symbols. The codeword is defined as c=oG=o[P I]=[oP o]. In the formula, c is the codeword, o is the message symbol, and oP is a vector-matrix multiplication, the result vector of which consists of s check bits. The complexity of computing oP is the same as that of the polynomial division described above, and both of them are large.

For the RS encoding based on the fast Fourier transform, the constant term of such algorithms is relatively large, so it is not suitable for short RS codes.

For short RS codes, some researchers proposed the method of optimizing matrix-vector multiplication. For example, the Cauchy matrix is used to replace the Vandermonde matrix, and the finite field multiplication in the encoding process can be converted into exclusive OR (XOR) operations. However, these techniques do not change the structure of the matrix-vector multiplication, so the degree of optimization is limited and the computational complexity is still huge.

In order to reduce the amount of computation, some researchers proposed some other codes. These other codes are not RS codes, but both those codes and the RS codes belong to MDS codes. For example, when the number of redundant symbols s=2, there are EvenOdd, X-Code, RDP (Row-Diagonal Parity), P-Code, and so on. When s=3, there are Star Code, RTP (RAID triple parity), and so on. However, such methods can only correspond to the codes with a small number of redundant symbols, such as s=2, 3, and when s=3, those codes require at least three finite field additions.

It can be seen that, in the prior art, although there are encoding methods for reducing RS codes with a small number of redundancies (i.e., the short RS codes), the reduction of the computational complexity is limited and the computation speed is very slow.

The object of the invention is to provide a fast Reed-Solomon encoding method and device for Reed-Solomon codes with a small number of redundancies in order to reduce the amount of computation.

The object of the invention is also to provide a computer-readable storage medium.

In order to achieve the above objects, an embodiment of the present invention provides a fast encoding method suitable for Reed-Solomon codes with a small number of redundancies, the method including:

a step of setting parity-check matrix comprising:

presetting parity-check matrices H 2 and H 3 ; where the number of redundant symbols s in the Reed-Solomon codes is 2 or 3, and when s is 3, the preset parity-check matrix is:

when s is 2, the preset parity-check matrix is:

a step of constructing shortened Reed-Solomon codes comprising:

constructing (k, s) RS codes over a finite field GF(2 m ) that conform to the preset parity-check matrix; using k points {o i } i=1 k in the R-points input {o i } i=0 R−1 as message symbols, and setting the remaining points to zero; setting the remaining points of the R points to zero, i.e. o 0 =0 and o k+1 =. . . =o R−1 =0;

wherein m denotes the number of bits for each symbol, R=2 r , r=┌ log 2 (k+1)┐, k is the number of message symbols, and s is the number of redundant symbols. For i=0,1, . . . ,R−1, o i is the the message symbol:

a step of encoding comprising:

calculating s redundant symbols according to the R-points input and the base vector of the finite field to achieve the encoding of Reed-Solomon codes with a small number of redundancies.

An embodiment of the present invention also provides an electronic device suitable for fast encoding of Reed-Solomon codes with a small number of redundancies, the electronic device including a processor, a communication interface, a memory and a communication bus, among them, the processor, the communication interface and the memory communicating with each other through the communication bus;

the memory being used for storing computer programs;

the processor, when executing the programs stored in the memory, being used to implement the steps of the method described above.

An embodiment of the invention also provides a computer-readable storage medium, the computer-readable storage medium storing a computer program, the computer program being executed by the processor to implement the steps of the method described above.

Compared with the prior art, the present invention has the following technical effects: the invention performs fast encoding on a (k, s=2, 3) shortened RS code conforming to a particular parity-check matrix constructed over a finite field. The main idea is to convert the input of the shortened RS codes into the R-points input, where R is a multiple of 2; k message symbols are specified and the remaining points in the R points are set to 0, and then the R-points input is processed recursively; the R-points input is successively converted into R/2-points input, R/4-points input, until 2-points input; finally, calculate the redundant symbols of the shortened RS codes according to its 2-points input. Compared with the encoding method mentioned above, when the fast encoding method of the invention is applied to this class of shortened RS codes, the computational amount approximates two finite field additions, greatly reducing the computational amount; when this class of RS codes and the fast encoding method is applied in various communication systems or storage systems, it can effectively improve the performance and reduce the energy consumption.

These and other features, aspects and advantages of the present invention are better understood when the following detailed description of the invention is read with reference to the accompanying drawings, in which:

FIG. 1 is a schematic flow diagram of a fast encoding method for Reed-Solomon codes with a small number of redundancies provided by an embodiment of the present invention;

FIG. 2 is a schematic flow diagram of subdivision steps of step S3 in an embodiment of the invention;

FIG. 3 is a schematic diagram of a recursive process for the R-points input of the RS codes in an embodiment of the invention ;

FIG. 4 is a schematic diagram of a recursive process for R=2-points input of the RS codes in an embodiment of the present invention;

FIG. 5 is a schematic diagram of a recursive process for R=8-points input of the RS codes in an embodiment of the present invention;

FIG. 6 is a schematic structure diagram of a fast encoding system suitable for Reed-Solomon codes with a small number of redundancies provided by an embodiment of the invention;

FIG. 7 is a schematic flow diagram of a fast encoding method for Reed-Solomon codes with a small number of redundancies provided by an embodiment of the present invention; and

FIG. 8 is a schematic structure diagram of an electronic device provided by an embodiment of the invention.

The present invention will now be described in further detail with reference to FIGS. 1 to 6 .

As shown in FIG. 1 , this embodiment discloses a fast encoding method for Reed-Solomon codes with a small number of redundancies, and the method includes the following steps S 1 to S 3 :

S 1 , the (k, s) Reed-Solomon codes conforming to the preset parity-check matrix constructed over the finite field GF(2 m ) is converted into R-points input {o i } i=0 R−1 by the shortening code technique, where m denotes the number of binary bits per symbol in the code, for example, m=8 means that each symbol in the code has 8 binary bits, R=2 r , r=┌ log 2 (k+1)┐, k is the number of message symbols, s is the number of redundant symbols; in the present embodiment, s is chosen as 2 or 3: for i=0,1 , . . . , R−1, o i is the message symbol. Let {w i |i=0,1, . . . , 2 m −1} denote the 2 m elements of GF(2 m ).

Wherein, when s is 3, the preset parity-check matrix H 3 is specifically:

when s is 2, the preset parity-check matrix is specifically:

wherein, {w i |i=1,2 , . . . , k} is k mutually different non-zero elements of GF(2 m ).

It is noted that, the above-mentioned H 2 and H 3 are provided as required by the present embodiment, but are not existing parity-check matrices. The fast encoding method disclosed in this embodiment is applicable to the (k≥1, s=2,3) shortened RS codes constructed over the finite field GF(2 m )=F 2 [X]/p(X), where F 2 [X] is the set of binary polynomials, and p(X) is the primitive polynomial. The number of message symbols is k, the number of redundant symbols is s, the code length is k+s, and k≤2 m −1.

Specifically, the RS codes conforming to the preset parity-check matrix in the present embodiment means that the codewords at certain positions in the original RS codes are replaced by 0, in order to shorten the length of the RS codes; the aforementioned “certain positions” may be any positions on the codewords, but in general, will be filled after the message symbols, and the number of “0” is R-k. And when the parity-check matrix of the shortened RS codes conforms to the preset parity-check matrix, it is possible to fast encode the shortened RS codes by using the fast encoding method disclosed in the present embodiment.

S 2 , shortening RS code: k points {o i } i=1 k in the R-points input {o i } i=0 R−1 are used as message symbols, and the remaining points are set to zero; here, the conventional RS code shortening technology can be applied.

Wherein, the remaining points in the R points are set to zero, i.e. o 0 =0 and o k+1 =. . . =o R−1 =0.

S 3 , the R-points input is processed recursively to obtain s redundant symbols.

Further, as shown in FIG. 2 , step S 3 specifically includes the following subdivision steps S 31 to S 32 :

S 31 , when R is 2, the s redundant symbols are calculated according to the R-points input and the base vector v 0 of GF(2 m ).

S 32 , when R is greater than 2, the R-points input is converted into R/2-points input, and then is recursively processed according to the R-points input and the base vector v 0 of GF(2 m ) until R=2, in order to obtain s redundant symbols;

specifically, perform pairwise XOR operations on the points

{ o i } i = 0 R 2 - 1 ⁢ ⁢ and ⁢ ⁢ { o i } i = R 2 R - 1

of the R-points input in order, to convert the R-points input into R/2-points input; according to the same process, perforin the recursive process on the R/2-points input to convert the R/2-points input into the R/2 2 -points input, in such a way, until the R-points input are converted to 2-points input.

Further, in step S 1 :

let {v i } i=0 m−1 denote a base of the finite field GF(2 m ). That is, for different i, different {v i } i=0 m−1 are mutually independent in GF(2 m ). The 2 m elements of the finite field GF(2 m ) are denoted by GF(2 m )={w i |i=0,1, . . . ,2 m −1}, and each element is defined as w i =i 0 v 0 +i 1 v i +. . . +i m−1 v m−1 . Among them, (i m−1 . . . i 0 ) 2 is the binary representation of i, that is, for 0≤i≤2 m−1 , the binary representation of i is: i=i 0 +i 1 2+. . . +i m−1 2 m−1 , and i 0 , i 1 , . . . , i m−1 ∈{0,1}.

When s is 2, the codeword of the RS code is c=[p 0 p 1 o 1 . . . o k ], and when s is 3, the codeword of the RS code is c=[p 0 p 1 p 2 o 1 . . . o k ].

Wherein, {o i ∈GF(2 m )|i=1 , . . . , k} are message symbols, and {p 0 , p 1 , p 2 } are redundant symbols.

In particular, due to Hc T =0, where H is the preset parity-check matrix, c is the codeword, c T is the transpose of the codeword, and according to the specific form of the preset parity-check matrix (i.e., the above-mentioned H 3 ), three redundant symbols can be calculated as:

p 0 =Σ i=1 k o i ;

p 1 =Σ i=1 k w i o i ;

p 2 =Σ i=1 k w i 2 o i .

Step S 3 gives out a recursive algorithm to calculate p 0 , p 1 , p 2 . Specifically, as shown in FIG. 3 , the specific process for calculating the redundant symbols is as follows:

the above three formulas for redundant symbols are converted into:

p 0 =Σ i=0 R−1 o i   (1);

p 1 =Σ i=0 R−1 w i o i   (2);

p 2 =Σ i=0 R−1 w i 2 o i   (3).

Wherein R=2 r , r=┌ log 2 (k+1)┐, and o 0 =0, o k+1 =o k+2 =. . . =o R−1 =0. Let

o i ′ = o i + o i + R 2 ,

where

i = 0 , … ⁢ , R 2 - 1 ;

let

o _ r - 1 = ∑ j = 0 R 2 - 1 ⁢ o R 2 + j ,

where

o R 2 + j

is the message symbol for the index (R/2)+j, ō r−1 is the summation of all the symbols in the second half (i.e., starting from the index R/2) of the message symbols.

For p 0 , according to the formulas

o i ′ = o i + o i + R 2 ⁢ ⁢ and ⁢ ⁢ o _ r - 1 = ∑ j = 0 R 2 - 1 ⁢ o R 2 + j ,

the p 0 is calculated as:

for p 1 , according to the formula w i =i 0 v 0 +i 1 v 1 +. . . +i m−1 v m−1 , it is obtained:

w R 2 + i = w i + v r - 1 ,

and p 1 is:

p 1 = ⁢ ∑ i = 0 R - 1 ⁢ w i ⁢ o i = ∑ i = 0 R 2 - 1 ⁢ w i ⁢ o i + ∑ i = 0 R 2 - 1 ⁢ w R 2 + i ⁢ o R 2 + i = ⁢ ∑ i = 0 R 2 - 1 ⁢ w i ⁢ o i + ∑ i = 0 R 2 - 1 ⁢ ( w i + v r - 1 ) ⁢ o R 2 + i = ⁢ ∑ i = 0 R 2 - 1 ⁢ w i ⁡ ( o i + o R 2 + i ) + v r - 1 ⁢ ∑ i = 0 R 2 - 1 ⁢ o R 2 + i = ⁢ ∑ i = 0 R 2 - 1 ⁢ w i ⁢ o i ′ + v r - 1 ⁢ o _ r - 1 ; ( 5 )

for p 2 :

Based on the above formulas, the input sequence {o i } i=0 R−1 whose size is R is converted into {o′ i } i=0 R/2−1 of size R/2. Then process it recursively, until the size of the input is 2. Then, p 0 =o 0 o 1 , p 1 =w 1 o 1 , p 2 =w 2 o 1 .

In addition, when s=2, the RS code has only 2 redundant symbols, and thus, one can directly calculate p 0 , p 1 .

The encoding of RS codes is to calculate the remainder of the message symbol polynomial divided by the check code generator polynomial. In the embodiment of the present application, through fast encoding the shortened RS codes (this class of shortened RS codes is k, s=2, 3) conforming to a particular parity-check matrix constructed over a finite field, the input of the shortened RS codes is converted into R-points input, where R is a multiple of 2, k message symbols are specified and the remaining points in R points are set to 0, and then the R-points input are processed recursively; the R-points input is then successively converted to R/2-points input, R/4-points input, until 2-points input; finally, the redundant symbols of the shortened RS codes are calculated based on the 2-points input. In particular, the fast encoding of Reed-Solomon codes with a small number of redundancies in the embodiment of the present invention comprises the following steps :

presetting parity-check matrices H 2 and H 3 ; wherein the number of redundant symbols s in Reed-Solomon codes is 2 or 3, and when s is 3, the preset parity-check matrix is specifically:

when s is 2, the preset parity-check matrix is specifically:

constructing the (k, s) RS codes conforming to the preset parity-check matrix over a finite field GF(2 m ); k points {o i } i=1 k in R-points input {o i } i=0 R−1 are treated as message symbols, and the remaining points are set to zero, i.e., o 0 =0 and o k+1 =. . . =o R−1 =0;

wherein m denotes the number of binary bits for each symbol, R=2 r , r=┌ log 2 (k+1)┐, k is the number of message symbols, s is the number of redundant symbols; for i=0,1 , . . . , R−1o i is the message symbol;

calculating s redundant symbols according to the R-points input and the base vector of the finite field, in order to perform the encoding of RS codes with a small number of redundancies.

For the above encoding step, it specifically includes the following steps:

let RS v (o 0 , . . . , o R−1 ) denote the encoding of RS codes, where V={v i } i=0 m−1 is a base of the finite field GF(2 m ), and its output is s redundant symbols;

when R is 2, calculating s redundant symbols according to the R-points input, i.e. 2-points input, and the base vector v 0 of GF(2 m ).

Specifically, let {v i } i=0 m−1 denote a base of the finite field GF(2 m ), and the 2 m elements of the finite field GF(2 m ) are denoted as GF(2 m )={w i |i=0,1, . . . , 2 m −1}, where each element is defined as w i =i 0 v 0 +i 1 v 1 +. . . +i m−1 v m−1 , and (i m−1 . . . i 0 ) 2 is the binary representation of i; for 0≤i≤2 m−1 , the binary representation of i is; i=i 0 +i 1 2+. . . +i m−1 2 m−1 , and i 0 , i 1 , . . . , i m−1 ∈{0,1};

calculating RS v (o 0 ,o 1 ) according to the 2-points input and the base vector v 0 , and output the s redundant symbols.

When R is greater than 2, the R-points input is converted into R/2-points input, and then recursively processing according to the R-points input and the base vector v o of GF(2 m ), until R=2, in order to obtain s redundant symbols;

wherein converting R-points input into R/2-points input is specifically: performing pairwise XOR operations on the points

{ o i } i = 0 R 2 - 1 ⁢ ⁢ and ⁢ ⁢ { o i } i = R 2 R - 1

of the R-points input in order, to convert the R-points input into the R/2-points input.

Wherein the recursive processing is recursively calculating RS V (o′ 0 , . . . , o′ R/2−1 ); during the recursive calculation, first calculating RS V (o′ 0 , . . . , o′ R/2−1 ), where the R/2-points input {o′ i } i=0 R/2−1 is calculated based on {o i } i=0 R , then calculating the outputs of RS V (o′ 0 , . . . , o′ R/2−1 ), the value Σ i=R/2 R−1 o i and the base vector v r−1 until R=2 for the input, to obtain s redundant symbols. The specific recursive calculation process can be found in FIG. 3 .

When s is 2, the codeword of the RS codes is c=[p 0 p 1 o 1 . . . o k ], where {p 0 , p 1 } is the redundant symbol.

When s is 3, the codeword of the RS codes is c=[p 0 p 1 p 2 o 1 . . . o k ], where {p 0 , p 1 , p 2 } denotes the rududant symbol.

Let Hc T =0, where H denotes the preset parity-check matrix, c is the codeword, c T is the transpose of the codeword, and the formulas for redundant symbol are:

p 0 =Σ i=0 R−1 o i ;

p 1 =Σ i=0 R−1 w i o i ;

p 2 =Σ i=0 R−1 w i 2 o i ;

where R=2 r , r=┌ log 2 (k+1)┐ and o 0 =0, o k+1 =o k+2 =. . . =o R−1 =0; let

o i ′ = o i + o i + R 2 ,

where

i = 0 , … ⁢ , R 2 - 1 ;

let

o _ r - 1 = ∑ j = 0 R 2 - 1 ⁢ o R 2 + j ,

where

o R 2 + j

is the message symbol of the index (R/2)+j, and ō r−1 is the summation of all the message symbols starting from R/2.

Then the above three formulas for calculating redundant symbols are converted into formulas (1)-(3), and thereby obtain formulas (4)-(6), achieving the encoding of RS codes with a small number of redundancies.

Compared with the existing encoding methods, when the fast encoding method of the present invention is applied to this class of shortened RS codes, the computational amount approximates two finite field additions, greatly reducing the computational amount; when applied in various communication systems or storage systems, it can effectively improve the performance and reduce the energy consumption.

A specific implementation example will now be described with reference to the accompanying drawings.

Specifically, when R=2, its recursive structure is as shown in FIG. 4 : wherein p 0 is obtained by adding o 0 , o 1 in finite fields, p 1 is obtained by multiplying o 1 with v 0 , and p 2 is obtained by multiplying o 1 with v 0 2 . That is, when R=2, only one finite field addition is required in the case that the redundant symbols s=3, and this greatly reduces the computational amount.

Specifically, when R=8, its recursive structure is as shown in FIG. 5 : the 8-points input is recursively processed to obtain the 2-points input, and p 0 is obtained by adding a certain point (as shown in FIG. 5 ) and ō 0 in the finite field; ō 0 is multiplied by v o in finite field, ō 1 is multiplied by v 1 in finite field, ō 2 is multiplied by v 2 in finite field, and the results of the above three multiplications in finite field are performed additions in finite field to obtain p 1 ; ō 0 is multiplied by v 0 2 in finite field, ō 1 is multiplied by v 1 2 in finite field, ō 2 is multiplied by v 2 2 , and the results of the above three multiplications in finite field are performed additions in finite field to obtain p 2 . That is, when R=8, only 14 additions in finite field and 6 multiplications in finite field are required in the case that redundant symbols s=3, greatly reducing the computational amount.

It is further noted that in this embodiment, the value of o 0 is zero.

It is noted that in the present embodiment, R=2 and R=8 are exemplified only, and the present embodiment does not limit the specific value of R. It is possible for the person skilled in the art to encode it according to the actual situation of the R value by using the fast encoding idea disclosed in the present embodiment.

As shown in FIG. 6 , the present embodiment discloses a fast encoding system suitable for Reed-Solomon codes with a small number of redundancies, which comprises:

an input point conversion module 10 used to convert the (k, s) RS codes conforming to the preset parity-check matrix constructed over the finite field GF(2 m ) into the R-points input {o i } i=0 R−1 by code shortening technique, where R=2 r , r=┌ log 2 (k+1)┐, and s is 2 or 3; wherein , when s is 3, the preset parity-check matrix is specifically:

when s is 2, the preset parity-check matrix is specifically:

a setting module 20 connected to the input point conversion module 10 to set k points of the R-points input {o i } i=1 k as message symbols and set the remaining points to zero;

an recursive module 30 connected to the setting module 20 to perform recursive process on the R-points input to obtain s redundant symbols.

Further, the recursive module 30 is specifically used to:

when R is 2, calculate the s redundant symbols according to the R-points input and the base vector v 0 of GF(2 m ); when R is greater than 2, convert the R-points input into R/2-points input, and then recursively process it according to the R-points input and the base vector v 0 of GF(2 m ), until R=2, in order to obtain s redundant symbols.

It is noted that the fast encoding system for the Reed-Solomon codes with a small number redundancies disclosed in this embodiment and the fast encoding method for Reed-Solomon codes with a small number redundancies disclosed in the above embodiments possess the same or corresponding technical points, which will not be repeat here.

An embodiment of the present invention also provides an electronic device suitable for fast encoding of Reed-Solomon codes with a small number of redundancies, as shown in FIG. 8 , including a processor 801 , a communication interface 802 , a memory 803 and a communication bus 804 , wherein the processor 801 , the communication interface 802 and the memory 803 are communicated with each other through the communication bus 804 ;

the memory 803 used to store computer programs;

the processor 801 used to, when executing the programs stored in the memory 803 , implement the following steps:

a step of setting the parity-check matrix comprising:

presetting parity-check matrices H 2 and H 3 ; wherein the number of redundant symbols s in Reed-Solomon code is 2 or 3, and when s is 3, the preset parity-check matrix is specifically:

when s is 2, the preset parity-check matrix is specifically:

a step of constructing the shortened RS codes comprising:

constructing the (k, s) RS codes conforming to the preset parity-check matrix over a finite field GF(2 m ); the k points {o i } i=1 k in R-points input {o i } i=0 R−1 are used as message symbols, and the remaining points are set to zero; setting the remaining points of R points to zero, that is o 0 =0 and o k+1 =. . . =o R−1 =0;

wherein m denotes the number of binary bits for each symbol, R=2 r , r=┌ log 2 (k+1)┐, k is the number of message symbols, s is the number of redundant symbols, i=0,1 , . . . , R−1, and o i is the message symbol;

a step of encoding comprising:

calculating s redundant symbols according to the R-points input and the base vector over the finite field, in order to perforin encoding of RS codes with a small number of redundancies.

The communication bus of the above-mentioned electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus and so on. The communication bus can be divided into address bus, data bus, control bus and so on. For ease of representation, it is only represented by one thick line in the figures, but does not mean that there is only one bus or one type of bus.

The communication interface is used for communication between the above-mentioned electronic device and other devices.

The memory may include a random access memory (RAM), and may also include non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

The above-mentioned processor may be a general processor including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate transistor logic devices or discrete hardware components.

As compared with the conventional encoding methods, when performing encoding of the shortened RS codes (the class of RS codes are k, s=2,3) by the above-mentioned device, the computational amount approximates two finite field additions, which greatly reduces the computational amount; when the device is used in various communication systems or storage systems, it can effectively improve performance and reduce energy consumption.

The embodiment of the invention also provides a computer-readable storage medium storing a computer program executed by the processor to implement the steps of the method described in FIG. 7 .

Specifically, the RS codes with a small number of redundancies, such as 2 or 3, is mainly used in storage systems. For example, disk array RAID-6 is a storage technology based on RS codes with two redundancies, and further in some distributed storage systems, RS code is used to encode data to ensure data reliability and durability. On the other hand, RS code is also the base code for some erasure correcting codes. However, the encoding process of the general RS code requires a large amount of computation, so that the storage system requires greater energy consumption, higher hardware requirements and lower data throughput.

The fast encoding method and system for Reed-Solomon codes with a small number of redundancies disclosed by the invention can be used in various communication or storage systems to improve the efficiency of communication or storage systems and reduce energy consumption. For example, it can be used in a storage system with two or three redundant erasure codes to improve encoding speed.

The complexity of the fast encoding process disclosed by the embodiment is analyzed as follows:

let A(R) denote the number of required finite field additions for R-points algorithm, and M(R) denote the number of required finite field multiplications for R-points algorithm, and the following recursive formulas can be obtained according to the fast encoding procedure of this embodiment:

the solutions for the two recursive formulas are:

A ( R )=2 R+log 2 ( R )−4;

M ( R )=2 log 2 ( R ).

Therefore, each input message symbol needs around A(R)/R≈2 finite field additions and M(R)/R≈0 finite field multiplications, in which the finite field addition is mainly implemented by XORs. Therefore, the fast encoding method in this embodiment requires around 2 XORs per input bit, as compared with the current MDS codes that requires at least 3 XORs, each input bit saving at least one XOR and increasing encoding speed of RS codes with a small number of redundancies.

It is noted that the term “includes”, “contains” or any other variant of it is intended to encompass inclusive inclusion, so that the process, method, article or device that include a range of elements include not only those elements, but also other elements not explicitly listed, or elements inherent in the process, method, article or device. In the absence of more restrictions, the elements defined by the statement “including a . . . ” do not preclude the existence of an additional same element in the process, method, article or device that include the elements.

Each embodiment in this specification is described in a related way, the same or similar parts between the various embodiments may be referred to each other, and each embodiment is focused on the difference from other embodiments. In particular, for the device embodiment, because it is basically similar to the method embodiment, the description is relatively simple, and the relevant part can be found in the partial description of the method embodiment.

The foregoing is intended only as a preferred embodiment of the invention, but is not used to restrict the invention, and any modification, equivalent substitution, improvement, etc., within the spirit and principle of the invention, shall be included in the scope of protection of the invention.