Power supply device and control method thereof

This application claims priority to Taiwan Application Serial Number 105132039, filed Oct. 4, 2016, which is herein incorporated by reference.

The present disclosure relates to a power supply device, and in particular, to a power supply device with ac backup ability.

For power supply device nowadays, when switching the power supply side to execute the ac backup function, additional semiconductor switches are required to control the electricity supply between the input power source and the output power, in order to prevent large inrush current. However, the switching operation time required for the power supply increases due to characteristic of the semiconductor switches, such that large capacitor are required to be arranged in the power supply to maintain the normal operation, which causes the size of the power supply increased.

In addition, additional arranged semiconductor switches also causes the loss of the power, and affect the overall conversion efficiency of the device. Therefore, an important area of research in the field involves ways in which to simplify the ac backup control method for power supply, reduce the size of the power supply and increase the conversion efficiency.

One aspect of the present disclosure is a power supply device. The power supply device includes a power factor correction circuit, a power switching circuit, and a control circuit. The power factor correction circuit includes an energy storage capacitor, and is configured to convert an input voltage to a bus voltage between two terminals of the energy storage capacitor according to a control signal so as to supply power to a later stage circuit. The power switching circuit is configured to selectively switch to conduct a first source or a second source to the power factor correction circuit, in order to provide the input voltage to the power factor correction circuit. The control circuit is configured to output the control signal to the power factor correction circuit. When the control circuit detects a first voltage of the first source connecting to the power factor correction circuit is abnormal, the control circuit determines whether a second voltage of the second source is smaller than the bus voltage, and controls the power switching circuit to switch when the second voltage is smaller than the bus voltage to conduct the second source to the power factor correction circuit.

Another aspect of the present disclosure is a control method for a power supply device. The control method includes: conducting, by a power switching circuit, a first source to a power factor correction circuit to provide an input voltage to the power factor correction circuit; converting, by the power factor correction circuit, the input voltage to a bus voltage between two terminals of an energy storage capacitor according to a control signal; detecting, by a control circuit, a first voltage of the first source conducting to the power factor correction circuit; determining, by the control circuit, whether a second voltage of a second source is smaller than the bus voltage when detecting the first voltage is abnormal; and controlling, by the control circuit, the power switching circuit to switch when the second voltage is smaller than the bus voltage to conduct the second source to the power factor correction circuit.

The disclosure can be more fully understood by reading the following detailed description of the embodiments, with reference made to the accompanying drawings as follows:

FIG. 1 is a diagram illustrating a backup power supply device according to some embodiments of the present disclosure.

FIG. 2 is a diagram illustrating the power supply device according to some embodiments of the present disclosure.

FIG. 3 is a wave diagram depicting the signals according to some embodiments of the present disclosure.

FIG. 4 is a flowchart diagram depicting a control method for the power supply device according to some embodiments of the present disclosure.

FIG. 5 is a diagram depicting the operation of the power supply device according to some embodiments of the present disclosure.

FIG. 6 is a diagram depicting the operation of the power supply device according to some embodiments of the present disclosure.

The embodiments herein described are by examples, and are not intended to be limiting. Alternatives, modifications and equivalents may be included within the spirit and scope of the disclosure as defined by the appended claims. Drawings are not drawn to scale and not meant to limit the actual embodiments of the present disclosure. Wherever possible, same reference numbers are used in the drawings and the description to refer to the same or like parts for better understanding. While method steps are disclosed herein as a series of acts or events, some may occur in different orders and/or concurrently with other acts or events apart from those described herein. The term “coupled” and “connected” may be used to indicate that two or more elements cooperate or interact with each other, and may also be termed electrically coupled/connected. The terms “first,” “second,” etc., are used to distinguish one element from another.

Reference is made to FIG. 1 . FIG. 1 is a diagram illustrating a backup power supply device 100 according to some embodiments of the present disclosure. As shown in FIG. 1 , in some embodiments, the power supply device 100 may selectively receive one of the voltages V 1 , V 2 as the ac input voltage Vin from a plurality of sources 220 , 240 , and perform voltage conversion to provide a bus voltage Vbus so as to supply power to a later stage circuit.

Specifically, in some embodiments, the power supply device 100 includes a power switching circuit 120 , a power factor correction circuit 140 and a control circuit 160 . The input side of the power switching circuit 120 is electrically coupled to each of the sources 220 , 240 , and the output side of the power switching circuit 120 is electrically coupled to the input side of the power factor correction circuit 140 . The output side of the power factor correction circuit 140 is configured to be electrically coupled to the later stage circuit so as to supply power to the later stage circuit.

In some embodiments, the control circuit 160 is electrically coupled to the power switching circuit 120 and the power factor correction circuit 140 . In addition, the control circuit 160 may also detect the voltage signal of the lines respectively with the voltage detecting unit of each of the lines. For example, the control circuit 160 may respectively detect the voltages V 1 , V 2 , the ac input voltage Vin, and the bus voltage Vbus with corresponding voltage detecting unit, so as to perform control accordingly. Specifically, the control circuit 160 is configured to output the switching signal SS 1 , SS 2 to the power switching circuit 120 to control the power switching circuit 120 to conduct one of the sources 220 , 240 to the power factor correction circuit 140 , and output the control signal CS 1 to the power factor correction circuit 140 to control the operation of the power factor correction circuit 140 , in which the specific operating method will be explained in accompanied with the corresponding drawings in the following paragraphs.

Furthermore, the control circuit 160 is respectively electrically coupled to the sources 220 , 240 via the isolating units 132 , 134 , and electrically coupled to the power factor correction unit 140 via the isolating unit 136 . For example, as shown in FIG. 1 , in some embodiments, the first side of the isolating unit 132 is electrically coupled to the source 220 , and the second side of the isolating unit 132 is electrically coupled to the control circuit 160 via the diode unit D 1 . Similarly, the first side of the isolating unit 134 is electrically coupled to the source 240 , and the second side of the isolating unit 134 is electrically coupled to the control circuit 160 via the diode unit D 2 . The first side of the isolating unit 136 is electrically coupled to the power factor correction unit 140 , and the second side of the isolating unit 136 is electrically coupled to the control circuit 160 via the diode unit D 3 .

Accordingly, in different operating stages, the power required by the control circuit 160 may be provided from the sources 220 , 240 or from the power factor correction unit 140 . Specifically, at the initial stage, the power factor correction unit 140 is not activated yet. At the time, the control circuit 160 may receive an activating operation voltage VDD 1 and/or VDD 2 from the source 220 and/or the source 240 via the isolating unit 132 and/or the isolating unit 134 during the activation, so as to activate the operation of the control circuit 160 . On the other hand, when the power supply device 100 is activated, and the power factor correction circuit 140 is in the normal operation, the control circuit 160 may receive an operation voltage VDD 3 from the power factor correction circuit 140 via the isolating unit 136 . Similarly, as depicted in FIG. 1 , in some embodiments, the operation voltage VDD 3 may be supplied from the power factor correction circuit 140 via the isolating unit 136 for the power required by the power switching circuit 120 , when the power factor correction circuit 140 is in the normal operation.

It is noted that, in some embodiments, the isolating units 132 , 134 may be implemented by reinforce isolating devices, and the isolating unit 136 may be implemented by a basic isolating device in order to prevent the damage of the internal elements resulted from erroneous voltages V 1 and V 2 . In addition, in some embodiments, the power required by the control circuit 160 may also be provided by an independent source, and the embodiment shown in FIG. 1 is only a possible example of the present disclosure and not meant to limit the present disclosure.

For the convenience of explanation, the detailed operations of the control circuit 160 outputting the switching signals SS 1 , SS 2 and the control signal CS 1 to control the power switching circuit 120 and the power factor correction circuit 140 will be discussed in relation to the embodiments depicted in the drawings.

Reference is made to FIG. 2 . FIG. 2 is a diagram illustrating the power supply device 100 according to some embodiments of the present disclosure. With respect to the embodiments of FIG. 2 , like elements in FIG. 1 are designated with the same reference numbers for ease of understanding. The specific operations of similar elements, which are already discussed in detail in above paragraphs, are omitted herein for the sake of brevity, unless there is a need to introduce the co-operation relationship with the elements shown in FIG. 2 .

As depicted in FIG. 2 , in some embodiments, the power supply device 100 further includes filter units 152 , 154 and an inrush current limiting circuit 170 . The filter units 152 and 154 are respectively coupled between the input terminals 112 , 114 and the power switching circuit 120 . The inrush current limiting circuit 170 is electrically coupled between the power switching circuit 120 and the power factor correction circuit 140 . In addition, in some embodiments, the filter units 152 , 154 may also be coupled to the latter stage of the power switching circuit 120 . Alternatively stated, the arrangement of the filter units 152 , 154 may be adjusted based on actual needs. Specifically, the arranged location and related configuration of the filter units 152 , 154 are determined based on the acceptable range for the nodes of the power switching circuit 120 . In some embodiments, the filter units 152 , 154 may also be combined as a single filter unit arranged at the latter stage of the power switching circuit 120 to filter out the noise generated in the system of the power supply device 100 .

Specifically, in some embodiments, the filter units 152 , 154 are configured to filter the voltages V 1 , V 2 respectively. For example, the filter units 152 and 154 may include common mode filters so as to reduce the electromagnetic interference in the voltages V 1 , V 2 , in order to prevent the noise generated in the system and high order harmonics in the signal damages the power supply device 100 or the later stage circuit.

As depicted in FIG. 2 , in some embodiments the power switching circuit 120 includes switching units 122 and 124 . For example, the switching units 122 and 124 may respectively include a relay. The switching unit 122 selectively conducts the source 220 and the power factor correction circuit 140 according to the switching signal SS 1 output by the control circuit 160 , so as to transmit the filtered voltage V 1 as the input voltage Vin to the power factor correction circuit 140 . Similarly, the switching unit 124 selectively conducts the source 240 and the power factor correction circuit 140 according to the switching signal SS 2 output by the control circuit 160 , so as to transmit the filtered voltage V 2 as the input voltage Vin to the power factor correction circuit 140 .

In some embodiments, the inrush current limiting circuit 170 includes an inrush current limiting resistor R 1 and an inrush current limiting switch S 1 . As depicted in FIG. 2 , the inrush current limiting resistor R 1 and the inrush current limiting switch S 1 are electrically coupled to each other in parallel. Specifically, when activating the power supply device 100 , the inrush current limiting switch S 1 remains off, such that the inrush current limiting resistor R 1 is used to limit the inrush current and perform RC charging based on the ac input voltage Vin to gradually boost the bus voltage Vbus across two terminals of the energy storage capacitor Cbulk in the power factor correction circuit 140 to a predetermined target value. When the control circuit 160 detects the bus voltage Vbus is boosted to the target value (e.g., about 380 V), the control circuit 160 may output corresponding switching signal to control the inrush current limiting switch S 1 to be on, in order to bypass the inrush current limiting resistor R 1 and complete the pre-charging to the energy storage capacitor Cbulk of the power supply device 100 . Thus, by the corresponding operation of the inrush current limiting circuit 170 , the damage to the circuit of the power supply device 100 resulted from the inrush current during the activation is avoided, so as to realize the soft-start procedure of the power factor correction circuit 140 .

As depicted in FIG. 2 , in some embodiments, the power factor correction circuit 140 includes a voltage clamping unit 142 , a driving unit 144 , boost inductor units L 1 , L 2 , the diode units D 4 , D 5 , the switching units M 1 , M 2 and the energy storage capacitor Cbulk. The voltage clamping unit 142 includes diode units CD 1 , CD 2 , CD 3 , and CD 4 . For example, in some embodiments, the cathode of the diode unit CD 1 is electrically coupled to the positive terminal of the energy storage capacitor Cbulk. The anode of the diode unit CD 1 is electrically coupled to the first terminal receiving the ac input voltage Vin. The cathode of the diode unit CD 2 is electrically coupled to the positive terminal of the energy storage capacitor Cbulk. The anode of the diode unit CD 2 is electrically coupled to the second terminal receiving the ac input voltage Vin. The cathode of the diode unit CD 3 is electrically coupled to the anode of the diode unit CD 1 . The anode of the diode unit CD 3 is electrically coupled to the negative terminal of the energy storage capacitor Cbulk. The cathode of the diode unit CD 4 is electrically coupled to the anode of the diode unit CD 2 . The anode of the diode unit CD 4 is electrically coupled to the negative terminal of the energy storage capacitor Cbulk. Accordingly, the voltage clamping unit 142 may, by the co-operation of the diode units CD 1 -CD 4 , clamp the voltage level input from the ac input voltage Vin to the power factor correction circuit 140 in the range of the bus voltage Vbus.

The cathode of the diode unit D 4 is electrically coupled to the positive terminal of the energy storage capacitor Cbulk. The anode of the diode unit D 4 is electrically coupled to the anode of the diode unit CD 1 via the boost inductor unit L 1 . The cathode of the diode unit D 5 is electrically coupled to the positive terminal of the energy storage capacitor Cbulk. The anode of the diode unit D 5 is electrically coupled to the anode of the diode unit CD 2 via the boost inductor unit L 2 . The first terminal of the switching unit M 1 is electrically coupled to the anode of the diode unit D 4 . The second terminal of the switching unit M 1 is electrically coupled to the negative terminal of the energy storage capacitor Cbulk. The first terminal of the switching unit M 2 is electrically coupled to the anode of the diode unit D 5 . The second terminal of the switching unit M 2 is electrically coupled to the negative terminal of the energy storage capacitor Cbulk. The control terminals of the switching units M 1 and M 2 are electrically coupled to the driving unit 144 , to receive the corresponding driving signals and selectively switch the switching units M 1 and M 2 to be on or off.

As shown in FIG. 2 , in some embodiments, the power factor correction circuit 140 may include bridgeless power factor corrector. In the positive half cycle of the ac input voltage Vin, when the switching unit M 1 is on, the current may flow through the switching unit M 1 and the parasitic diode of the switching unit M 2 to store energy to the boost inductor units L 1 , L 2 . When the switching unit M 1 is off, the current may flow through the conducted diode unit D 4 and the parasitic diode of the switching unit M 2 to supply power to the energy storage capacitor Cbulk and the loads. Similarly, in the negative half cycle of the ac input voltage Vin, when the switching unit M 2 is on, the current may flow through the switching unit M 2 and the parasitic diode of the switching unit M 1 to store energy to the boost inductor units L 2 , L 1 . When the switching unit M 2 is off, the current may flow through the conducted diode unit D 5 and the parasitic diode of the switching unit M 1 to supply power to the energy storage capacitor Cbulk and the loads.

Thus, the driving unit 144 may output corresponding driving signals according to the control signal CS 1 output by the control circuit 160 to selectively turn on or turn off the switching units M 1 , M 2 , to achieve the power factor correction function of the power factor correction circuit 140 . Therefore, the power supply device 100 may provide the bus voltage Vbus across two terminals of the energy storage capacitor Cbulk to supply power to the later stage circuit.

It is noted that, though the power factor correction circuit depicted in FIG. 2 applies the bridgeless power factor corrector structure, but the present disclosure is not limited thereto. In some other embodiments, the power factor correction circuit 140 may also be achieved by applying half-bridge or full-bridge power factor corrector structures.

Reference is made to FIG. 3 and FIG. 4 . FIG. 3 is a wave diagram depicting the signals according to some embodiments of the present disclosure. FIG. 4 is a flowchart diagram depicting a control method 400 for the power supply device 100 according to some embodiments of the present disclosure. In the following paragraphs, the embodiments shown in FIG. 3 and FIG. 4 are discussed to explain how the power supply device 100 supplies power to the later stage circuit continuously and switches to backup powers (e.g., source 240 ) to provide power when the error occurs or the electricity is lost in the currently electricity supply (e.g., source 220 ).

For the convenience and clearance of the discussion, the signal waveforms and the control method 400 depicted in FIG. 4 are discussed in accordance with the power supply device 100 depicted in FIG. 1 and FIG. 2 , but is not limited thereto. As shown in FIG. 4 , the control method 400 includes steps S 410 , S 420 , S 430 , S 440 , S 450 and S 460 .

First, in the step S 410 , the power supply device 100 is activated. Specifically, the operation of activating the power supply device 100 in the step S 410 includes: via an isolating unit 132 or an isolating unit 134 , receiving an activating operation voltage VDD 1 or VDD 2 from the source 220 or the source 240 to activate the control circuit 160 ; charging the energy storage capacitor via the inrush current limiting resistor R 1 in the inrush current limiting circuit 170 , to boost the bus voltage Vbus to a predetermined value; controlling, by the control circuit 160 , the inrush current limiting switch S 1 in the inrush current limiting circuit 170 to be on to bypass the inrush current limiting resistor R 1 when the bus voltage Vbus is boosted to the predetermined value; and receiving an operation voltage VDD 3 via an isolating unit 136 from the power factor correction circuit 140 after the power factor correction circuit 140 is activated, in order to supply power to the control circuit 160 . The above operation of activating the power supply device 100 is described in detailed in the embodiments shown in FIG. 1 and FIG. 2 and further explanation is omitted for the sake of brevity.

Next, in the step S 420 , the power supply device 100 conducts, by the power switching circuit 120 , the source 220 to the power factor correction circuit 140 to provide the input voltage Vin to the power factor correction circuit 140 . Reference is made to FIG. 5 in accompanied. FIG. 5 is a diagram depicting the operation of the power supply device 100 according to some embodiments of the present disclosure. As shown in FIG. 5 , at the time the input voltage Vin received by the power factor correction circuit 140 is from the voltage V 1 provided by the source 220 from the input terminal 112 , and transmitted to the power factor correction circuit 140 via the filter unit 152 , the switching unit 122 in the power switching circuit 120 , and the inrush current limiting switch S 1 in the inrush current limiting circuit 170 .

Next, in the step S 430 , the power supply device 100 converts, by the power factor correction circuit 140 , the input voltage Vin to the bus voltage Vbus between two terminals of the energy storage capacitor Cbulk according to the control signal CS 1 .

As depicted in FIG. 3 , before the time T 0 , the voltages V 1 , V 2 of the source 220 , 240 are normal. The switching signal SS 1 is at an enable level (e.g., a high level), and the switching signal SS 2 is at a disable level (e.g., a low level). Accordingly, the power switching circuit 120 conducts the source 220 and the power factor correction circuit 140 , such that the source 220 provides the voltage V 1 as the input voltage Vin. At the time, the control signal CS 1 is at the enable level such that the power factor correction 140 operates normally and maintains the bus voltage Vbus between two terminals of the energy storage capacitor Cbulk at the predetermined level.

Next, in the step S 440 , the power supply device 100 detects, by the control circuit 160 , the voltage V 1 of the source 220 conducting to the power factor correction circuit 140 .

Next, in the step S 450 , when the control circuit 160 detects the voltage V 1 is abnormal, the control circuit 160 determines whether a voltage V 2 of the source 240 is smaller than the bus voltage Vbus.

Next. In the step S 460 , the power supply device 100 controls, by the control circuit 160 , the power switching circuit 120 to switch when the voltage V 2 is smaller than the bus voltage Vbus to conduct the source 240 to the power factor correction circuit 140 .

As depicted in FIG. 3 , at the time T 0 , a power failure occurs to the voltage V 1 output by the source 220 . At the time, since the power factor correction circuit 140 loses the electricity supply, the power required by the latter stage circuit is provided by the energy storage capacitor Cbulk, and thus the bus voltage Vbus starts to decrease.

When the control circuit 160 detects the voltage V 1 of the source 220 conducting to the power factor correction circuit 140 is abnormal, after a period of hold-on time (e.g., about 9 ms), at the time T 1 , the control circuit 160 determines whether the voltage V 2 of the source 240 for backup is smaller than the current bus voltage Vbus, and activates the ac backup mechanism when the voltage V 2 is smaller than the bus voltage Vbus and controls the power switching circuit 120 to switch. Specifically, if the switching is performed when the voltage V 2 of the source 240 for backup is larger than the bus voltage Vbus, the switching elements in the circuit may be damaged due to the large current stress in a short time. Therefore, before activating the ac backup mechanism, the control circuit 160 detects the voltage V 2 of the source 240 and the bus voltage Vbus first to protect the circuit.

Specifically, the operation of conducting the source 240 to the power factor correction circuit 140 in the step S 460 further includes S 461 , S 462 , S 463 , S 464 and S 465 .

First, in the step S 461 , the control circuit 160 outputs the corresponding control signal CS 1 at the time T 1 after detecting the voltage V 1 is abnormal, in order to turn off the power factor correction circuit 140 .

As depicted in FIG. 3 , at the time T 1 , the control circuit 160 switches the control signal CS 1 from the enable level (e.g., a high level) to the disable level (e.g., the low level). Thus, the power factor correction circuit 140 is turned off correspondingly, and the current flowing through the power switching circuit 120 and the boost inductor units L 1 and L 2 is zero, so as to achieve zero-current switching in the following operation of the switching of the control switches. At the time the power required by the later stage circuit is still provided by the energy storage capacitor Cbulk, and thus the bus voltage Vbus continues to decrease.

Next, in the step S 462 , after a period of waiting time (e.g., about 2 ms), at a time T 2 after the time T 1 , the current flowing through the power switching circuit 120 and the boost inductor units L 1 and L 2 decreases to zero. At the time, the control circuit 160 outputs a corresponding switching signal SS 1 to turn off the switching unit 122 in the power switching circuit 120 in order to disconnect the source 220 and the power factor correction circuit 140 . In the step S 463 , at the time T 2 , the control circuit 160 outputs a corresponding switching signal SS 2 to turn on a switching unit 124 in the power switching circuit 120 in order to connect the source 240 and the power factor correction circuit 140 .

As depicted in FIG. 3 , at the time T 2 , the control circuit 160 switches the switching signal SS 1 from the enable level (e.g., a high level) to the disable level (e.g., the low level), and switches the switching signal SS 2 from the disable level (e.g., a low level) to the enable level (e.g., a high level). Thus, the backup source 240 may be connected to the power factor correction circuit 140 . It is noted that, in the embodiments using relays as the switching units 122 , 124 , since the response time required to open the relay is shorter than the response time required to close the relay, even the switching units 122 and 124 receive the switching signals SS 1 and SS 2 respectively at the same time, the path between the source 220 and the power factor correction circuit 140 will be disconnected first, then the path between the source 240 and the power factor correction circuit 140 will be connected. Alternatively stated, the switching units 122 and 124 will not be on at the same time. At the time the power required by the later stage circuit is still provided by the energy storage capacitor Cbulk, and thus the bus voltage Vbus continues to decrease.

In addition, in some other embodiments, the control circuit 160 may also first switch the switching signal SS 1 from the enable level to the disable level, and then switch the switching signal SS 2 from the disable level to the enable level to prevent the switching units 122 and 124 in the power switching circuit 120 from being on at the same time.

Next, in the step S 464 , after a period of waiting time (e.g., about 9 ms), the control circuit 160 checks the source 220 is disconnected from the power factor correction circuit 140 and the source 240 is connected to the power factor correction circuit 140 at the time T 3 after the time T 2 and outputs the corresponding control signal CS 1 to turn on the power factor correction circuit 140 .

Next, in the step S 465 , the power factor correction circuit 140 executes a soft start after being turned on, so as to supply power to the energy storage capacitor Cbulk according to the source 240 in order to gradually increase the bus voltage Vbus to the predetermined level.

As depicted in FIG. 3 , at the time T 3 , the control circuit 160 switches the control signal CS 1 from the disable level (e.g., a low level) to the enable level (e.g., a high level). Thus, the power factor correction circuit 140 is turned on correspondingly. As the power factor correction circuit 140 executes the soft start to supply power to the energy storage capacitor Cbulk, the trend of the changes of the bus voltage Vbus may be reversed. For example, after a period of soft-start time (e.g., about 3 ms), at the time T 4 , the bus voltage Vbus gradually increases. At the time T 5 , the bus voltage Vbus is recovered to the original predetermined level and the power factor correction circuit 140 may execute the original power factor correction function again.

After the above steps S 461 -S 465 , the control circuit 160 may control the power switching circuit 120 to disconnect the source 220 from the power factor correction circuit 140 and connect the source 240 to the power switching circuit 140 to complete the operation of switching the source terminal to the backup power. Reference is made to FIG. 6 . FIG. 6 is a diagram depicting the operation of the power supply device 100 according to some embodiments of the present disclosure. As depicted in FIG. 6 , at the time the input voltage Vin received by the power factor correction circuit 140 is from the voltage V 2 provided by the backup source 240 from the input terminal 114 , and transmitted to the power factor correction circuit 140 via the filter unit 154 , the switching unit 124 in the power switching circuit 120 , and the inrush current limiting switch S 1 in the inrush current limiting circuit 170 .

In addition, in some embodiments, the control method 400 further includes steps S 470 and S 480 . Specifically, in the step S 470 , when the power supply device 100 detects the voltage V 1 is recovered to a normal state, the power supply device 100 determines, by the control circuit 160 , whether the voltage V 1 is smaller than the bus voltage Vbus. Next, in the step S 480 , when the voltage V 1 is smaller than the bus voltage Vbus, the power supply device 100 controls, by the control circuit 160 , the power switching circuit 120 to switch to conduct the source 220 to the power factor correction circuit 140 again.

As depicted in FIG. 3 , at the time T 6 , the voltage V 1 is recovered to the normal state. When the control circuit 160 detects the voltage V 1 is recovered and maintained for a period of time (e.g., about 1 s), at the time T 7 , the control circuit 160 determines whether the voltage V 1 is smaller than the bus voltage Vbus, and activates the switching mechanism when the voltage V 1 is smaller than the bus voltage Vbus and controls the power switching circuit 120 switch back to the default priority source 220 .

Specifically, the operation of conducting the source 220 to the power factor correction circuit 140 again includes steps S 481 , S 482 , S 483 , S 484 and S 485 .

First, similar to the step S 461 , in the step S 481 , the control circuit 160 outputs the corresponding control signal CS 1 to turn off the power factor correction circuit 140 at the time T 7 after detecting the voltage V 1 is recovered to the normal state, so as to achieve zero-current switching in the following operation of the switching of the control switches.

As depicted in FIG. 3 , at the time T 7 , the control circuit 160 again switches the control signal CS 1 from the enable level (e.g., a high level) to a disable level (e.g., a low level). Thus, the power factor correction circuit 140 is turned off correspondingly. At the time, the power required by the latter stage circuit is provided by the energy storage capacitor Cbulk, and thus the bus voltage Vbus starts to decrease.

Next, similar to the steps S 462 , S 463 , in the step S 482 , after a period of waiting time (e.g., about 2 ms), at a time T 8 after the time T 7 , the current flowing through the power switching circuit 120 and the boost inductor units L 1 and L 2 is zero. At the time, the control circuit 160 outputs the corresponding switching signal SS 1 to turn on the switching unit 122 in the power switching circuit 120 in order to connect the source 220 and the power factor correction circuit 140 . In the step S 483 , at the time T 7 , the control circuit 160 outputs a corresponding switching signal SS 2 to turn off the switching unit 124 in the power switching circuit 120 in order to disconnect the source 240 and the power factor correction circuit 140 .

As depicted in FIG. 3 , at the time T 8 , the control circuit 160 switches the switching signal SS 1 from the disable level (e.g., the low level) to the enable level (e.g., the high level), and switches the switching signal SS 2 from the enable level (e.g., the high level) to the disable level (e.g., the low level). Thus, the default priority source 220 may be connected to the power factor correction circuit 140 . Similarly to the embodiments mentioned above, in the embodiments using relays as the switching units 122 , 124 , since the response time required to open the relay is shorter than the response time required to close the relay, even the switching units 122 and 124 receive the switching signals SS 1 and SS 2 respectively at the same time, the path between the source 240 and the power factor correction circuit 140 will be disconnected first, then the path between the source 220 and the power factor correction circuit 140 will be connected, and the switching units 122 and 124 will not be on at the same time. At the time the power required by the later stage circuit is still provided by the energy storage capacitor Cbulk, and thus the bus voltage Vbus continues to decrease.

In addition, in some other embodiments, the control circuit 160 may also first switch the switching signal SS 2 from the enable level to the disable level, and then switch the switching signal SS 1 from the disable level to the enable level to prevent the switching units 122 and 124 in the power switching circuit 120 from being on at the same time.

Next, similar to the step S 464 , in the step S 484 , after a period of waiting time (e.g., about 9 ms), the control circuit 160 checks the source 220 is connected to the power factor correction circuit 140 and the source 240 is disconnected from the power factor correction circuit 140 at the time T 9 after the time T 8 and outputs the corresponding control signal CS 1 to turn on the power factor correction circuit 140 .

Next, similar to the step S 465 , in the step S 485 , the power factor correction circuit 140 executes the soft start after being turned on, so as to supply power to the energy storage capacitor Cbulk according to the source 220 in order to gradually increase the bus voltage Vbus to the predetermined level.

As depicted in FIG. 3 , at the time T 9 , the control circuit 160 switches the control signal CS 1 from the disable level (e.g., the low level) to the enable level (e.g., the high level). Thus, the power factor correction circuit 140 is turned on correspondingly. As the power factor correction circuit 140 executes the soft start to supply power to the energy storage capacitor Cbulk, the trend of the changes of the bus voltage Vbus may be reversed. For example, after a period of soft-start time (e.g., about 3 ms), at the time T 10 , the bus voltage Vbus gradually increases. At the time T 11 , the bus voltage Vbus is recovered to the original predetermined level and the power factor correction circuit 140 may execute the original power factor correction function again.

After the above steps S 481 -S 485 , the control circuit 160 may control the power switching circuit 120 to disconnect the source 240 from the power factor correction circuit 140 and connect the source 220 to the power switching circuit 140 to complete the operation of switching from the backup power to the default priority power after the priority power is recovered and supplies power normally.

Therefore, by applying the power supply device 100 and control method 400 in the various embodiments mentioned above, the power supply device 100 may choose and switch the input power source when supplying power to the later stage circuit continuously. Thus, the risk that the system fails to supply power continuously under the circumstances of power failure or maintenance for the input source may be avoided. In addition, the power supply device 100 having the ac backup function may also increase the space utilization of the system, and make the maintenance of the power delivery device become more convenient.

In the various embodiments of the present disclosure, by the operation of closing the power factor correction circuit 140 , the power switching circuit 120 is safely operated and configured to perform switching when the input side current is cut off and the energy storage capacitor Cbulk is used to provide the power to the later stage circuit, which improves the reliability. In addition, in various embodiments, there is no need to arrange additional control switch, so the overall conversion efficiency of the power supply device 100 may be improved, and the size of the power supply device 100 may be reduced. Since there is no need to arrange additional control switch, when switching the input sources 220 , 240 , there is no need to ensure the waiting time to cut off the semiconductor switching devices, and thus the switching procedures in the control process may be simplified and the overall switching time for power supply device 100 switching the input sources 220 and 240 is reduced. On the other hand, the circuit structure of the present disclosure may perform control with various power factor correctors such as bridgeless type, half-bridge type, full-bridge type, to meet the actual requirement of different application.

In addition, in the above embodiments, the control circuit 160 may be implemented by various ways such as a microcontroller unit (MCU), a Complex Programmable Logic Device (CPLD) or a Field-programmable gate array (FPGA). The circuit elements such as the switching units 122 , 124 , the isolation units 132 , 134 , 136 , the filter units 152 , 154 , the voltage clamping unit 142 , the driving unit 144 , and the boost inductor units L 1 , L 2 , the diode units CD 1 -CD 4 , D 1 -D 5 , the switching units M 1 , M 2 , the inrush current limiting resistor R 1 , the inrush current limiting switch S 1 , and the energy storage capacitor Cbulk may be implemented by proper power electronic elements.