Digital controlled delay line

In integrated circuits (ICs), internal clock signals are usually generated by a digital controlled delay line (DCDL) of a delay-locked loop (DLL). In general, a DCDL is used to prevent an external clock signal from arriving at an output until a predetermined time has elapsed. The DCDL typically contains several delay cells, with each of the delay cells having a corresponding delay time. The total delay time of the DCDL can be set by increasing or decreasing the number of delay cells that a signal passes through. To achieve finer granularity of delay-time adjustment, the DCDL includes a huge amount of delay cells that can be adjusted.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 shows a delay circuit, in accordance with some embodiments of the disclosure.

FIG. 2 shows the DCDL of FIG. 1 , in accordance with some embodiments of the disclosure.

FIG. 3A shows a propagation mode of the delay cell, in accordance with some embodiments of the disclosure.

FIG. 3B shows a feedback mode of the delay cell, in accordance with some embodiments of the disclosure.

FIG. 3C shows a standby mode of the delay cell, in accordance with some embodiments of the disclosure.

FIG. 3D shows an idle mode of a delay cell, in accordance with some embodiments of the disclosure.

FIG. 4A shows a propagation path Path 1 corresponding to a delay time D 1 in the DCDL, in accordance with some embodiments of the disclosure.

FIG. 4B shows a propagation path Path 2 corresponding to a delay time D 2 in the DCDL, in accordance with some embodiments of the disclosure.

FIG. 4C shows a dual propagation paths Path 1 +Path 2 corresponding to a delay time D 3 in the DCDL, in accordance with some embodiments of the disclosure.

FIG. 5 shows a waveform illustrating the signals in the nodes n 1 and n 2 when the propagation path Path 1 of FIG. 4A is changed to the propagation path Path 2 of FIG. 4B via the dual propagation paths Path 1 +Path 2 of FIG. 4C , in accordance with some embodiments of the disclosure.

FIG. 6A shows a waveform illustrating the signals in the nodes n 1 and n 2 when the dual propagation paths Path 1 +Path 2 of FIG. 4C is changed to the single propagation path Path 2 of FIG. 4B , in accordance with some embodiments of the disclosure.

FIG. 6B shows a waveform illustrating the signals in the nodes n 1 and n 2 when the single propagation path Path 2 of FIG. 4B is changed to the dual propagation paths Path 1 +Path 2 of FIG. 4C , in accordance with some embodiments of the disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In some embodiments, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and/or after a disclosed method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

FIG. 1 shows a delay circuit 100 , in accordance with some embodiments of the disclosure. The delay circuit 100 is capable of delaying an input signal Sin by a specific delay time to provide an output signal Sout. The delay circuit 100 includes a controller 120 and a digital controlled delay line (DCDL) 110 . The controller 120 is capable of providing a control signal Ctrl corresponding to the specific delay time. In response to the control signal Ctrl, the DCDL 110 is capable of providing the output signal Sout by delaying the input signal Sin by the specific delay time.

In some embodiments, the controller 120 provides the control signal Ctrl according to a signal with multi bits from other circuits. In order to decrease routing area for the bits of the signal from the other circuits, a Gray code can be applied to reduce numbers of from 2 n to n. Gray code is a binary numeral system where two successive values differ in only one bit which can prevent spurious output. The controller 120 may include a specific decoder for decoding the Gray code into the control bits (H[n:0], V[n:0], HA[n:0]) of the control signal Ctrl. In some embodiments, the control bits (H[n:0], V[n:0], HA[n:0]) of the control signal Ctrl corresponding to the Gray code are used to control the device-switching operation of the DCDL 110 , so as to switch a single device in the DCDL 110 , and then interference caused by device-switching is decreased. The device-switching operation of the DCDL 110 will be discussed in details later.

In some embodiments, the delay circuit 100 is used to process a clock signal. When the process, supply voltage, or temperature (PVT) varies, the delay circuit 100 is capable of dynamically adjusting the specific delay time, so as to provide a suitable clock for subsequent applications or circuits.

FIG. 2 shows the DCDL 110 of FIG. 1 , in accordance with some embodiments of the disclosure. The DCDL 110 includes multiple delay cells 200 _ 0 to 200 _ n , and the delay cells 200 _ 0 to 200 _ n are connected in a chain. In such embodiments, the delay cells 200 _ 0 to 200 _ n have the same circuits. Each of the delay cells 200 _ 0 to 200 _ n includes three tri-state inverters 210 , 220 and 230 , and each tri-state inverter is controlled by an individual control bit of the control signal Ctrl. When the tri-state inverter is enabled by its control bit, the tri-state inverter is capable of inverting an input signal to provide an output signal, i.e. the output signal is complementary to the input signal for the tri-state inverter. Conversely, when the tri-state inverter is disabled by its control bit, the tri-state inverter is capable of providing a high-impedance (Hi-Z) signal.

In some embodiments, the control signal Ctrl from the controller 120 includes three sets of control bits. A first set of control bits H[ 0 ] to H[n] are used to control the tri-state inverters 210 _ 0 to 210 _ n , respectively, and the tri-state inverters 210 _ 0 to 210 _ n are coupled in series. In some embodiments, the tri-state inverter 210 _ 0 of the delay cell 200 _ 0 (i.e. the first stage of the delay cell in the chain) can be omitted. A second set of control bits HA[ 0 ] to HA[n] are used to control the tri-state inverters 220 _ 0 to 220 _ n , respectively, and the tri-state inverters 220 _ 0 to 220 _ n are coupled in series. A third set of control bits V[ 0 ] to V[n] are used to control the tri-state inverters 230 _ 0 to 230 _ n , respectively.

Taking the delay cell 200 _ 8 as an example, in the chain formed by the delay cells 200 _ 0 to 200 _ n , the delay cell 200 _ 7 is a previous delay cell (e.g., a previous stage of the delay cell) and the delay cell 200 _ 9 is a subsequent (or next) delay cell (e.g., a subsequent stage of the delay cell) for the delay cell 200 _ 8 . The delay cell 200 _ 8 includes the tri-state inverters 210 _ 8 , 220 _ 8 and 230 _ 8 .

The tri-state inverter 210 _ 8 is controlled by the control bit H[ 8 ]. The tri-state inverter 210 _ 8 has an input terminal coupled to the tri-state inverter 210 _ 7 of the delay cell 200 _ 7 , and an output terminal coupled to the tri-state inverter 210 _ 9 of the delay cell 200 _ 9 . When the tri-state inverter 210 _ 8 is enabled by the control bit H[ 8 ], the tri-state inverter 210 _ 8 is capable of inverting a signal from the previous delay cell 200 _ 7 and providing the inverted signal to the subsequent delay cell 200 _ 9 . When the tri-state inverter 210 _ 8 is disabled by the control bit H[ 8 ], the tri-state inverter 210 _ 8 is capable of providing a high-impedance output to the subsequent delay cell 200 _ 9 . In some embodiments, a high-impedance output represents that no current flows at an output terminal of a tri-state inverter. Therefore, when the tri-state inverter 210 _ 8 is enabled, the signal from the previous delay cell 200 _ 7 can be propagated to the subsequent delay cell 200 _ 9 via the tri-state inverter 210 _ 8 . Conversely, when the tri-state inverter 210 _ 8 is disabled, the signal from the previous delay cell 200 _ 7 is blocked from propagating to the following delay cells 200 _ 9 to 200 _ n , and the node between the tri-state inverters 210 _ 8 , 210 _ 9 and 230 _ 8 is floating due to a high-impedance output from the tri-state inverter 210 _ 8 .

The tri-state inverter 220 _ 8 is controlled by the control bit HA[ 8 ]. The tri-state inverter 220 _ 8 has an input terminal coupled to the tri-state inverter 220 _ 9 of the delay cell 200 _ 9 and an output terminal coupled to the tri-state inverter 220 _ 7 of the delay cell 200 _ 7 . When the tri-state inverter 220 _ 8 is enabled by the control bit HA[ 8 ], the tri-state inverter 220 _ 8 is capable of inverting a signal from the delay cell 200 _ 9 and providing the inverted signal to the delay cell 200 _ 7 . When the tri-state inverter 220 _ 8 is disabled by the control bit HA[ 8 ], the tri-state inverter 220 _ 8 is capable of providing a high-impedance output to the previous delay cell 200 _ 7 . Therefore, when the tri-state inverter 220 _ 8 is enabled, the signal from the subsequent delay cell 200 _ 9 can be propagated to the previous delay cell 200 _ 7 via the tri-state inverter 220 _ 8 . Conversely, when the tri-state inverter 220 _ 8 is disabled, the signal from the previous delay cell 200 _ 9 is blocked from propagating to the preceding delay cells 200 _ 7 to 200 _ n.

The tri-state inverter 230 _ 8 is controlled by the control bit V[ 8 ]. The tri-state inverter 230 _ 8 has an input terminal coupled to the tri-state inverter 210 _ 8 and an output terminal coupled to the tri-state inverter 220 _ 8 in the delay cell 200 _ 8 . Furthermore, the input terminal of the tri-state inverter 230 _ 8 is further coupled to an input terminal of the tri-state inverter 210 _ 9 , and the output terminal of the tri-state inverter 230 _ 8 is further coupled to an output terminal of the tri-state inverter 220 _ 9 . When the tri-state inverter 230 _ 8 is enabled by the control bit V[ 8 ], the tri-state inverter 230 _ 8 is capable of inverting a signal from the tri-state inverter 210 _ 8 and providing the inverted signal to the tri-state inverter 220 _ 8 . When the tri-state inverter 230 _ 8 is disabled by the control bit V[ 8 ], the tri-state inverter 230 _ 8 is capable of providing a high-impedance output to the tri-state inverter 220 _ 8 . Therefore, when the tri-state inverter 230 _ 8 is enabled, the signal from the tri-state inverter 210 _ 8 can be propagated to the tri-state inverter 220 _ 8 via the tri-state inverter 230 _ 8 . Conversely, when the tri-state inverter 230 _ 8 is disabled, the signal from the tri-state inverter 210 _ 8 is blocked from propagating to the tri-state inverter 220 _ 8 .

By enabling and disabling the three tri-state inverters 210 , 220 and 230 in the delay cell 200 , each delay cell can operate in different modes.

Taking the delay cell 200 _ 8 as an example, FIG. 3A shows a propagation mode of the delay cell 200 _ 8 , in accordance with some embodiments of the disclosure. In the propagation mode, the tri-state inverter 210 _ 8 is enabled by the control bit H[ 8 ], and a signal S 1 from the delay cell 200 _ 7 is inverted and propagated to the delay cell 200 _ 9 . Furthermore, the tri-state inverter 220 _ 8 is enabled by the control bit HA[ 8 ], and a signal S 2 (e.g., a return signal) from the delay cell 200 _ 9 is inverted and propagated to the delay cell 200 _ 7 . Moreover, the tri-state inverter 230 _ 8 is disabled by the control bit V[ 8 ], and no feedback path is formed in the delay cell 200 _ 8 . Therefore, in the propagation mode for each delay cell, the signal from a previous stage of the delay cell is propagated to a subsequent stage of the delay cell, and the signal from the subsequent stage of the delay cell is propagated to the previous stage of the delay cell.

FIG. 3B shows a feedback mode of the delay cell 200 _ 8 , in accordance with some embodiments of the disclosure. In the feedback mode, the tri-state inverter 210 _ 8 is enabled by the control bit H[ 8 ], and a signal S 1 from the delay cell 200 _ 7 is inverted and propagated to the delay cell 200 _ 9 . Moreover, the tri-state inverter 230 _ 8 is enabled by the control bit V[ 8 ], and the signal propagated by the tri-state inverter 210 _ 8 is inverted and propagated to the tri-state inverter 220 _ 8 , e.g., a signal to be feedback. Furthermore, the tri-state inverter 220 _ 8 is enabled by the control bit HA[ 8 ] and a feedback path is formed via the tri-state inverter 230 _ 8 , and the signal propagated by the tri-state inverter 230 _ 8 is inverted and propagated to the delay cell 200 _ 7 . Therefore, in the feedback mode for each delay cell, the signal from a previous stage of the delay cell is propagated to a subsequent stage of the delay cell and also back to the previous stage of the delay cell. In some embodiments, a signal S 2 from the subsequent delay cell 200 _ 9 is also inverted and propagated to the delay cell 200 _ 7 via the tri-state inverter 220 _ 8 .

FIG. 3C shows a standby mode of the delay cell 200 _ 8 , in accordance with some embodiments of the disclosure. In the standby mode, the tri-state inverter 210 _ 8 is enabled by the control bit H[ 8 ], and the signal S 1 from the delay cell 200 _ 7 is inverted and propagated to the delay cell 200 _ 9 . Moreover, the tri-state inverter 230 _ 8 is enabled by the control bit V[ 8 ], and the signal propagated by the tri-state inverter 210 _ 8 is inverted and propagated to the tri-state inverter 220 _ 8 . Furthermore, the tri-state inverter 220 _ 8 is disabled by the control bit HA[ 8 ], and a high-impedance output is provided to the delay cell 200 _ 7 by the tri-state inverter 220 _ 8 , i.e. the signal propagated by the tri-state inverter 230 _ 8 and the signal S 2 from the delay cell 200 _ 9 will not be propagated to the delay cell 200 _ 7 via the tri-state inverter 220 _ 8 . Therefore, in the standby mode for each delay cell, the signal from a previous stage of the delay cell is propagated to a subsequent stage of the delay cell, and a high-impedance output is provided to the previous stage of the delay cell. Specifically, no return signal or the signal to be feedback is transmitted to the previous stage of the delay cell. Compared with the feedback mode of FIG. 3B , the tri-state inverter 220 _ 8 is disabled, and then the tri-state inverters 210 _ 8 and 230 _ 8 are pre-enabled for propagating the signal S 1 in FIG. 3C .

FIG. 3D shows an idle mode of a delay cell 200 _ 8 , in accordance with some embodiments of the disclosure. In the idle mode, the tri-state inverter 210 _ 8 is disabled by the control bit H[ 8 ], and a high-impedance output is provided to the delay cell 200 _ 9 by the tri-state inverter 210 _ 8 , i.e. the signal S 1 from the delay cell 200 _ 7 will not be propagated to the delay cell 200 _ 9 via the tri-state inverter 210 _ 8 . Moreover, the tri-state inverter 230 _ 8 is disabled by the control bit V[ 8 ], and no feedback path is formed in the delay cell 200 _ 8 . Furthermore, the tri-state inverter 220 _ 8 is disabled by the control bit HA[ 8 ], and a high-impedance output is provided to the delay cell 200 _ 7 by the tri-state inverter 220 _ 8 , i.e. the signal S 2 from the delay cell 200 _ 9 will not be propagated to the delay cell 200 _ 7 via the tri-state inverter 220 _ 8 . Therefore, in the idle mode for each delay cell, no signal is propagated to the previous stage of the delay cell and the subsequent stage of the delay cell, and floating state occurs in the delay cell.

FIG. 4A shows a propagation path Path 1 corresponding to a delay time D 1 in the DCDL 110 , in accordance with some embodiments of the disclosure. In order to simplify the description, the control bits of the tri-state inverters are omitted. Furthermore, the enabled tri-state inverter is shown by a solid line, and the disabled tri-state inverter is shown by a dotted line.

In FIG. 4A , the delay cell 200 _ 0 is operated in a feedback mode, the delay cell 200 _ 1 is operated in a standby mode, and the delay cells 200 _ 2 to 200 _ n are operated in an idle mode. Therefore, the five tri-state inverters 210 _ 0 , 210 _ 1 , 220 _ 0 , 230 _ 0 and 230 _ 1 are enabled in FIG. 4A . It should be noted that a single delay cell is operated in the feedback mode, and a subsequent stage of the delay cell following the single delay cell is operated in the standby mode. Furthermore, the other stages of the delay cells following the subsequent stage of the delay cell operated in the standby mode are operated in the idle mode. Furthermore, the propagation path Path 1 is formed by the three tri-state inverters 210 _ 0 , 230 _ 0 and 220 _ 0 , and a middle point (or a foldback point) of the propagation path Path 1 is in the tri-state inverter 230 _ 0 of the delay cell 200 _ 0 . For example, if a propagation path is formed by the seven tri-state inverters 210 _ 0 - 210 _ 2 , 230 _ 2 and 220 _ 2 - 220 _ 0 , a middle point of the propagation path is in the tri-state inverter 230 _ 2 of the delay cell 200 _ 2 .

In some embodiments, when a single delay cell is operated in the feedback mode, each following stage of the delay cell following the single delay cell is operated in the standby mode. Therefore, no floating state occurs in the DCDL 110 when all delay cells (e.g., 200 _ 1 to 200 _ n ) following the delay cell (e.g., 200 _ 0 ) operated in the feedback mode are operated in the standby mode.

An input signal Sin is propagated and delayed by the delay time D 1 to provide an output signal Sout via the propagation path Path 1 . The propagation path Path 1 is formed by the three tri-state inverters 210 _ 0 , 230 _ 0 and 220 _ 0 , and the delay time D 1 is related to the number of tri-state inverters on the propagation path Path 1 . In such embodiments, the delay time D 1 is equal or proportional to triple the unit delay T INV of a tri-state inverter, e.g., D 1 =3*T INV .

If the delay time D 1 is too small and need to be increased, the controller 120 of FIG. 1 will provide the control signal Ctrl to switch the operation modes of the delay cells 200 _ 0 to 200 _ n , so as to form a new propagation path propagating and delaying the input signal Sin by an increased delay time to provide the output signal Sout.

FIG. 4B shows a propagation path Path 2 corresponding to a delay time D 2 in the DCDL 110 , in accordance with some embodiments of the disclosure. In order to simplify the description, the control bits of the tri-state inverters are omitted. Furthermore, the enabled tri-state inverter is shown by a solid line, and the disabled tri-state inverter is shown by a dotted line.

In FIG. 4B , the delay cell 200 _ 0 is operated in a propagation mode, the delay cell 200 _ 1 is operated in a feedback mode, the delay cell 200 _ 2 is operated in a standby mode, and the delay cells 200 _ 3 to 200 _ n are operated in an idle mode. Therefore, the seven tri-state inverters 210 _ 0 , 210 _ 1 , 210 _ 2 , 220 _ 0 , 220 _ 1 , 230 _ 1 and 230 _ 2 are enabled. It should be noted that a single delay cell is operated in the feedback mode, and a subsequent stage of the delay cell following the single delay cell is operated in the standby mode, and the previous stage of the delay cell prior to the single delay cell is operated in the propagation mode. Furthermore, the other stages of the delay cells following the subsequent stage of the delay cell operated in the standby mode are operated in the idle mode. Furthermore, the propagation path Path 2 is formed by the five tri-state inverters 210 _ 0 , 210 _ 1 , 230 _ 1 , 220 _ 1 and 220 _ 0 , and a middle point (or a foldback point) of the propagation path Path 2 is in the tri-state inverter 230 _ 1 of the delay cell 200 _ 1 .

In some embodiments, when a single delay cell is operated in the feedback mode, each following stage of the delay cell following the single delay cell is operated in the standby mode. Therefore, no floating state occurs in the DCDL 110 when all delay cells (e.g., 200 _ 2 to 200 _ n ) following the delay cell (e.g., 200 _ 1 ) operated in the feedback mode are operated in the standby mode.

An input signal Sin is propagated and delayed by the delay time D 2 to provide an output signal Sout via the propagation path Path 2 . The propagation path Path 2 is formed by the five tri-state inverters 210 _ 0 , 210 _ 1 , 230 _ 1 , 220 _ 1 and 220 _ 0 , and the delay time D 2 is related to the number of tri-state inverters on the propagation path Path 2 . In such embodiments, the delay time D 2 is equal or proportional to five times the unit delay T INV of a tri-state inverter, e.g., D 2 =5*T INV .

Referring to FIG. 4A and FIG. 4B together, the controller 120 of FIG. 1 changes the delay time from D 1 to D 2 with a delay step resolution 2*T INV (e.g., D 2 −D 1 =2*T INV ) by changing the propagation path from Path 1 to Path 2 .

FIG. 4C shows a dual propagation paths Path 1 +Path 2 corresponding to a delay time D 3 in the DCDL 110 , in accordance with some embodiments of the disclosure. In order to simplify the description, the control bits of the tri-state inverters are omitted. Furthermore, the enabled tri-state inverter is shown by a solid line, and the disabled tri-state inverter is shown by a dotted line.

In FIG. 4C , the delay cells 200 _ 0 and 200 _ 1 are both operated in a feedback mode, the delay cell 200 _ 2 is operated in a standby mode, and the delay cells 200 _ 3 to 200 _ n are operated in an idle mode. Therefore, the eight tri-state inverters 210 _ 0 , 210 _ 1 , 210 _ 2 , 220 _ 0 , 220 _ 1 , 230 _ 0 , 230 _ 1 and 230 _ 2 are enabled. It should be noted that a pair of delay cells are operated in the feedback mode, and a subsequent stage of the delay cell following the pair of delay cells is operated in the standby mode. Furthermore, the other stages of the delay cells following the subsequent stage of the delay cell operated in the standby mode are operated in the idle mode, and the previous stages of the delay cells prior to the pair of delay cells are operated in the propagation mode.

In some embodiments, when a pair of delay cells are operated in the feedback mode, each following stage of the delay cell following the pair of delay cells is operated in the standby mode. Therefore, no floating state occurs in the DCDL 110 when all delay cells (e.g., 200 _ 2 to 200 _ n ) following the delay cells (e.g., 200 _ 0 to 200 _ 1 ) operated in the feedback mode are operated in the standby mode.

An input signal Sin is propagated and delayed by a delay time D 3 to provide an output signal Sout via the dual propagation paths Path 1 +Path 2 , simultaneously. As described above, the propagation path Path 1 is formed by the three tri-state inverters 210 _ 0 , 230 _ 0 and 220 _ 0 , and the propagation path Path 2 is formed by the five tri-state inverters 210 _ 0 , 210 _ 1 , 230 _ 1 , 220 _ 1 and 220 _ 0 . The delay time D 3 is related to the number of tri-state inverters on the propagation paths Path 1 and Path 2 . In some embodiments, the delay time D 3 is obtained by averaging or interpolating the delay time D 1 of the propagation path Path 1 and the delay time D 2 of the propagation path Path 2 , e.g., an average number of tri-state inverters on the propagation paths Path 1 and Path 2 . Therefore, the delay time D 3 is equal or proportional to four times the unit delay T INV of a tri-state inverter, e.g., D 3 =(D 1 +D 2 )/2=4*T INV .

Referring to FIG. 4A and FIG. 4C together, when the controller 120 of FIG. 1 switches the single propagation path Path 1 of FIG. 4A to the dual propagation paths Path 1 +Path 2 of FIG. 4C , the delay time is changed from D 1 to D 3 with a delay step resolution 1*T INV (e.g., D 3 −D 1 =1*T INV ). Therefore, a smaller delay step resolution (e.g., 1*T INV ) is provided by propagated input signal Sin to provide the output signal Sout via the dual propagation paths Path 1 +Path 2 . It should be noted that the dual propagation paths Path 1 +Path 2 are two neighboring propagation paths.

Referring to FIG. 4B and FIG. 4C together, when the controller 120 of FIG. 1 switches the dual propagation paths Path 1 +Path 2 of FIG. 4C to the single propagation path Path 2 of FIG. 4B , the delay time is changed from D 3 to D 2 with a delay step resolution 1*T INV (e.g., D 2 −D 3 =1*T INV ).

FIG. 5 shows a waveform illustrating the signals in the nodes n 1 and n 2 when the propagation path Path 1 of FIG. 4A is changed to the propagation path Path 2 of FIG. 4B via the dual propagation paths Path 1 +Path 2 of FIG. 4C , in accordance with some embodiments of the disclosure. In FIG. 5 , “Sn 1 ” represents a signal in the node n 1 of the DCDL 110 , “Ctrl(H,V,HA)” represents the control signal Ctrl from the controller 120 of FIG. 1 , and “Sn 2 ” represents a signal in the node n 2 of the DCDL 110 .

Referring to FIGS. 4A-4C and 5 , for the propagation path Path 1 , the tri-state inverters 210 _ 1 and 230 _ 1 are enabled, and the input signal Sin is pre-propagated to the node n 3 . At the time point t 1 , the control signal Ctrl from the controller 120 of FIG. 1 is changed and the tri-state inverter 220 _ 1 of the delay cell 200 _ 1 is enabled, thereby the propagation path Path 1 is changed to the dual propagation paths Path 1 +Path 2 . Due to the input signal Sin is pre-propagated to the node n 3 via the tri-state inverters 210 _ 1 and 230 _ 1 , the node n 3 is not a floating node, and the signal of the node n 3 is propagated to the node n 2 via the tri-state inverter 220 _ 1 without a glitch 310 occurring when the propagation path Path 1 is changed to the dual propagation paths Path 1 +Path 2 . In general, glitches can occur when an input terminal of a logic cell is coupled to a floating node. Furthermore, by switching a single tri-state inverter (e.g., enabling the tri-state inverter 220 _ 1 of the delay cell 200 _ 1 ) to change the propagation path Path 1 to the dual propagation paths Path 1 +Path 2 , interference caused by device-switching is decreased in the propagation path.

At the time point t 2 of FIG. 5 , the control signal Ctrl from the controller 120 of FIG. 1 is changed and the tri-state inverter 230 _ 0 of the delay cell 200 _ 0 is disabled, thereby the dual propagation paths Path 1 +Path 2 is changed to the propagation path Path 2 . Similarly, the node n 3 is not a floating node, and the signal of the node n 3 is propagated to the node n 2 via the tri-state inverter 220 _ 1 without a glitch 315 occurring when the dual propagation paths Path 1 +Path 2 is changed to the propagation path Path 2 . Furthermore, by switching a single tri-state inverter (e.g., disabling the tri-state inverter 230 _ 0 of the delay cell 200 _ 0 ) to change the dual propagation paths Path 1 +Path 2 to the propagation path Path 2 , interference caused by device-switching is decreased in the propagation path.

FIG. 6A shows a waveform illustrating the signals in the nodes n 1 and n 2 when the dual propagation paths Path 1 +Path 2 of FIG. 4C is changed to the single propagation path Path 2 of FIG. 4B , in accordance with some embodiments of the disclosure. In FIG. 6A , “Sn 1 ” represents a signal in the node n 1 of the DCDL 110 , “Ctrl(H,V,HA)” represents the control signal Ctrl from the controller 120 of FIG. 1 , and “Sn 2 ” represents a signal in the node n 2 the DCDL 110 .

Referring to FIGS. 4B, 4C and 6A , at the time point t 3 , the control signal Ctrl from the controller 120 of FIG. 1 is changed and the tri-state inverter 230 _ 0 of the delay cell 200 _ 0 is disabled, thereby the dual propagation paths Path 1 +Path 2 is changed to the single propagation path Path 2 . Furthermore, the slew rate of the signal Sn 2 in the node n 2 is slowed down due to the degraded driving strength of the tri-state inverter caused by the disabled tri-state inverter 230 _ 0 , as shown in label 320 of FIG. 6A . Similarly, no glitches happen during the step-by-step, successive path-switching with the delay step resolution 1*T INV from a shorter delay (e.g., the dual propagation paths Path 1 +Path 2 ) to a longer delay (e.g., the propagation path Path 2 ). Furthermore, by switching a single tri-state inverter (e.g., disabling the tri-state inverter 230 _ 0 of the delay cell 200 _ 0 ) to change the dual propagation path Path 1 +Path 2 to the single propagation path Path 2 , interference caused by device-switching is decreased in the propagation path. Therefore, even if the path-switching happened exactly at the instant of signal rising (or falling) transient (e.g., the signal Sn 1 at the time point t 3 ), there would be no glitch, and the rising (or falling) transient time will change in response to the path switching.

FIG. 6B shows a waveform illustrating the signals in the nodes n 1 and n 2 when the single propagation path Path 2 of FIG. 4B is changed to the dual propagation paths Path 1 +Path 2 of FIG. 4C , in accordance with some embodiments of the disclosure. In FIG. 6B , “Sn 1 ” represents a signal in the node n 1 of the DCDL 110 , “Ctrl(H,V,HA)” represents the control signal Ctrl from the controller 120 of FIG. 1 , and “Sn 2 ” represents a signal in the node n 2 the DCDL 110 .

Referring to FIGS. 4B, 4C and 6B , at the time point t 4 , the control signal Ctrl from the controller 120 of FIG. 1 is changed and the tri-state inverter 230 _ 0 of the delay cell 200 _ 0 is enabled, thereby the single propagation path Path 2 is changed to the dual propagation paths Path 1 +Path 2 . Furthermore, the slew rate of the signal Sn 2 in the node n 2 is sped up due to the enhanced driving strength of the tri-state inverter caused by the enabled tri-state inverter 230 _ 0 , as shown in label 330 of FIG. 6B . Similarly, there is no glitch that happens during the step-by-step, successive path-switching with the delay step resolution 1*T INV from a longer delay (e.g., the propagation path Path 2 ) to a shorter delay (e.g., the dual propagation paths Path 1 +Path 2 ). Furthermore, by switching a single tri-state inverter (e.g., enabling the tri-state inverter 230 _ 0 of the delay cell 200 _ 0 ), the propagation path is changed from Path 2 to Path 1 +Path 2 , thereby decreasing interference in the propagation path caused by device switching. Therefore, even if the path-switching happened exactly at the instant of signal rising (or falling) transient, there would be no glitch, and the rising (or falling) transient time will change in response to the path switching.

Embodiments for glitch-free digital controlled delay line (DCDL) are provided. The DCDL includes multi delay cells connected in a chain. Each delay cell can operate in a propagation mode, a feedback mode, a standby mode, and an idle mode. By controlling the mode of each delay cell in the DCDL, a propagation path is formed for propagating and delaying an input signal Sin to provide an output signal Sout. When a single delay cell or a pair of delay cells are operated in the feedback mode, a subsequent stage of the delay cell following the single delay cell or the pair of delay cells is operated in the standby mode, to prevent a floating node, and thereby no glitch occurs when the propagation path is changed.

In some embodiments, a digital controlled delay line is provided. The digital controlled delay line includes a plurality of delay cells coupled in a chain. The delay cells form a first propagation path to propagate an input signal and to delay the input signal by a first delay. Each of the delay cells has: a propagation mode for propagating a first signal from a previous stage of the delay cell to a subsequent stage of the delay cell and propagating a second signal from the subsequent stage of the delay cell to the previous stage of the delay cell; a feedback mode for propagating the first signal from the previous stage of the delay cell to the subsequent stage of the delay cell and back to the previous stage of the delay cell; a standby mode for propagating the first signal from the previous stage of the delay cell to the subsequent stage of the delay cell, and providing a first high-impedance output to the previous stage of the delay cell; and an idle mode for providing the first high-impedance output to the previous stage of the delay cell, and providing a second high-impedance output to the subsequent stage of the delay cell. The first propagation path is formed when a single delay cell in the chain is operated in the feedback mode, the delay cells previous to the single delay cell in the chain are operated in the propagation mode, a first subsequent delay cell following the single delay cell in the chain is operated in the standby mode, and the delay cells following the first subsequent delay cell in the chain are operated in the idle mode.

In some embodiments, a digital controlled delay line is provided. The digital controlled delay line includes the first to fifth inverters. The first inverter has an input terminal for receiving an input signal. The second inverter has an input terminal coupled to the input terminal of the first inverter. The third inverter has an input terminal coupled to an output terminal of the second inverter. The fourth inverter has an input terminal coupled to an output terminal of the third inverter. The fifth inverter has an input terminal coupled to output terminals of the first and fourth inverters, and an output terminal for providing an output signal.

In some embodiments, a digital controlled delay line is provided. The digital controlled delay line includes a plurality of first tri-state inverters coupled in series and controlled by a first set of control signals, a plurality of second tri-state inverters coupled in series and controlled by a second set of control signals, and a plurality of third tri-state inverters controlled by a third set of control signals. A third tri-state inverter of the third tri-state inverters has an input terminal coupled to an input terminal of an individual first tri-state inverter, and an output terminal coupled to an output terminal of an individual second tri-state inverter. When one of the third tri-state inverters is enabled, an input signal is propagated and delayed by a first delay time via a first propagation path, and the first propagation path is formed by the enabled third tri-state inverter, each of the first tri-state inverters having an output terminal coupled to the input terminal of the enabled third tri-state inverter, and each of the second tri-state inverters having an input terminal coupled to the output terminal of the enabled third tri-state inverter.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.