Signal transmission circuit

This application is a U.S. national stage of the PCT international application No. PCT/JP2016/003242 filed on Jul. 8, 2016, which claims the benefit of foreign priority of Japanese patent application No. 2015-161359 filed on Aug. 18, 2015, the contents all of which are incorporated herein by reference.

The present invention relates to a signal transmission circuit, particularly to a signal transmission circuit including a primary circuit and a secondary circuit magnetically or capacitively coupled with the primary circuit.

A wireless communication system (a signal transmission circuit) transmits signals from a primary circuit to a secondary circuit using magnetic coupling. Such a wireless communication system is disclosed in PTL 1 which includes a transmitter and a receiver.

The transmitter includes a transmission circuit (a primary circuit) which receives transmitted data, and a transmitting coil functioning as a transmitting antenna. The transmission circuit supplies a current which corresponds to the transmitting data to the transmitting coil so that the transmitting coil can induce a magnetic-field change corresponding to the transmitting data.

The receiver includes a receiving coil functioning as a receiving antenna, and a reception circuit (a secondary circuit). The receiving coil is inductively coupled with the transmitting coil, and detects the magnetic-field change induced by the transmitting coil. The reception circuit generates receiving data based on an induced electromotive force generated at both ends of the receiving coil.

Patent Literature

PTL 1: Japanese Patent Laid-Open Publication No. 2007-036497

A signal transmission circuit includes a primary element configured to receive differential signals which are generated from a transmission signal and which contain alternating-current (AC) components, a secondary element magnetically or capacitively coupled with the primary element and configured to output AC signals containing the AC components of the differential signals, a secondary circuit including a pair of transmission lines that propagate the AC signals, the secondary circuit being electrically connected to the secondary element and extracting the transmission signal from the AC signals, a feedback circuit configured to feedback an intermediate voltage between voltages of the pair of transmission lines such that the intermediate voltage is converged to a reference voltage. This signal transmission circuit prevents the secondary circuit from malfunctioning due to noises.

FIG. 1 is a schematic block diagram of a signal transmission circuit according to an exemplary embodiment.

FIG. 2 is a schematic circuit diagram of the signal transmission circuit according to the embodiment.

FIG. 3 is a schematic circuit diagram of a primary circuit of the signal transmission circuit according to the embodiment.

FIG. 4 shows signal waveforms of the primary circuit of the signal transmission circuit according to the embodiment.

FIG. 5 shows signal waveforms of a secondary circuit of the signal transmission circuit according to the embodiment.

FIG. 6A is a schematic block diagram of a feedback circuit of the signal transmission circuit according to the embodiment.

FIG. 6B is a schematic circuit diagram of a differential amplifier circuit and a control circuit of the signal transmission circuit according to the embodiment.

FIG. 7 is a schematic circuit diagram of a secondary circuit of a comparative example of a signal transmission circuit.

FIG. 8 shows signal waveforms obtained by a simulation of an operation of the comparative example of the signal transmission circuit.

FIG. 9 shows signal waveforms indicating simulation results of the operation of the signal transmission circuit according to the embodiment.

FIG. 10 shows frequency characteristics of the feedback circuit of the signal transmission circuit according to the embodiment.

FIG. 11 is a schematic circuit diagram of another primary circuit and another insulation circuit of the signal transmission circuit according to the embodiment.

FIGS. 1 and 2 are a schematic block diagram and a schematic circuit diagram of signal transmission circuit 100 according to an exemplary embodiment, respectively. Signal transmission circuit 100 includes insulation circuit 3 , secondary circuit 2 , and feedback circuit 4 . Insulation circuit 3 includes a transformer including primary coil L 1 as a primary element and secondary coil L 2 as a secondary element. Primary coil L 1 receives differential signals S 21 and S 22 which are generated from a transmission signal S 1 .

Secondary coil L 2 is magnetically coupled with primary coil L 1 , and outputs alternating-current (AC) signals S 31 and S 32 which contain AC components of the differential signals S 21 and S 22 . Secondary circuit 2 includes a pair of transmission lines 24 and 25 which are electrically connected to secondary coil L 2 . The AC signals S 31 and S 32 propagate through transmission lines 24 and 25 . Secondary circuit 2 extracts the transmission signal S 1 from the AC signals S 31 and S 32 and outputs extracted transmission signal S 1 as an output signal S 5 .

Feedback circuit 4 feedbacks an intermediate voltage VC 1 between voltages of transmission lines 24 and 25 to converge voltage VC 1 to a reference voltage VR 1 .

Signal transmission circuit 100 according to the embodiment will be detailed below. The following embodiment is just an example of the present invention, and the present invention can be variously modified according to design or other requirements within the technical idea of the present invention.

Signal transmission circuit 100 further includes primary circuit 1 electrically connected to primary coil L 1 (primary element). Primary circuit 1 generates the differential signals S 21 and S 22 from the transmission signal S 1 . The transmission signal S 1 is a signal electrically indicating data. Data in accordance with the present embodiment is serial data. Primary circuit 1 includes waveform shaping circuit 11 , AC component extraction circuit 12 , and driving circuit 13 .

Waveform shaping circuit 11 is implemented by, for example, a Schmitt trigger circuit. Waveform shaping circuit 11 sharply shapes the rising and falling edges of the transmission signal S 1 so as to amplify harmonic components of the signal S 1 . Circuit 11 is not necessarily a Schmitt trigger circuit.

AC component extraction circuit 12 includes signal conversion circuit 14 and differential circuit 15 . Circuit 14 is implemented by a differential amplifier. FIG. 3 is a schematic circuit diagram of primary circuit 1 . FIG. 4 shows signal waveforms of primary circuit 1 . FIG. 5 shows signal waveforms of secondary circuit 2 . In FIGS. 4 and 5 , the vertical axis represents signal values, and the horizontal axis represents time. Signal conversion circuit 14 converts a single-end signal S 11 supplied from waveform shaping circuit 11 into two differential signals S 12 and S 13 , and outputs differential signals S 12 and S 13 , as shown in FIG. 3 . The differential signal S 13 is slightly delayed in phase with respect to the signal S 11 as shown in FIG. 4 . The differential signal S 12 has a phase inverted to that of the signal S 13 , as shown in FIG. 4 .

As shown in FIG. 3 , differential circuit 15 differentiates the differential signals S 12 and S 13 received from signal conversion circuit 14 , extracts the AC components of the signals S 12 and S 13 , and outputs differential signals S 14 and S 15 . Differential circuit 15 includes two inverters 151 and 152 , two differentiators 153 and 154 , and two switching elements 155 and 156 . Inverters 151 and 152 output signals with phases inverted to those of the differential signals S 12 and S 13 . Differentiators 153 and 154 differentiate the signals output from Inverters 151 and 152 , respectively, and output the differentiated signals. Differentiators 153 and 154 may be implemented by, for example, an RC circuit including a resistor and a capacitor.

Switching elements 155 and 156 are electrically connected in parallel with differentiators 153 and 154 , respectively. Switching elements 155 and 156 are turned on and off in response to the differential signals S 12 and S 13 , respectively. In accordance with the present embodiment, switching element 155 is turned on when the level of signal S 12 is high while switching element 155 is turned off when the level of signal S 12 is low. Switching element 156 is turned on when the level of signal S 13 is high while switching element 156 is turned off when the level of signal S 13 is low.

Therefore, the signals supplied from inverters 151 and 152 pass through differentiators 153 and 154 when the levels of differential signals S 12 and S 13 are high, respectively. The signals supplied from inverters 151 and 152 do not pass through differentiators 153 and 154 when the levels of signals S 12 and S 13 are low, respectively. Hence, the differential signal S 14 is a signal that is obtained by differentiating the rising edge of the signal S 11 , as shown in FIG. 4 . The differential signal S 15 is a signal that is obtained by differentiating the falling edge of the signal S 11 , as shown in FIG. 4 . An offset from constant current source IS 3 supplying a constant current to power-supply potential point Vdd is added to the differential signal S 14 . An offset from constant current source IS 4 supplying a constant current to a circuit ground GND is added to the differential signal S 15 .

As shown in FIG. 3 , driving circuit 13 generates the differential signals S 21 and S 22 based on the differential signals S 12 to S 15 supplied from differential circuit 15 . The differential signals S 21 and S 22 are current signals for driving primary coil L 1 of insulation circuit 3 . Driving circuit 13 includes four switching elements Q 1 to Q 4 . Switching elements Q 1 and Q 2 are npn-type bipolar transistors. Elements Q 3 and Q 4 are enhancement-mode n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs).

The collectors of elements Q 1 and Q 2 are electrically connected to power-supply potential point Vdd. The base of element Q 1 receives the differential signal S 14 (the node “a” shown in FIG. 3 ). The base of element Q 2 receives the differential signal S 15 (the node “b” shown in FIG. 3 ). The sources of elements Q 3 and Q 4 are electrically connected to the circuit ground GND. The gate of element Q 3 receives the differential signal S 12 (the node “c” shown in FIG. 3 ). The gate of element Q 4 receives the differential signal S 13 (the node “d” shown in FIG. 3 ). The emitter of element Q 1 and the drain of element Q 3 are connected together at node N 12 electrically connected to end L 11 of primary coil L 1 . The emitter of element Q 2 and the drain of element Q 4 are connected together at node N 13 electrically connected to end L 12 of primary coil L 1 .

FIG. 4 shows signal waveforms of primary circuit 1 . Driving circuit 13 allows the differential signal S 21 , a current, to be applied to end L 11 of primary coil L 1 . Driving circuit 13 also allows the differential signal S 22 , a current, to be applied to end L 12 of primary coil L 1 . The signal S 22 is a signal with a phase inverted to that of the signal S 21 . As a result, an AC voltage V 1 shown in FIG. 4 is supplied to primary coil L 1 .

In other words, driving circuit 13 sends the differential signal S 21 to end L 11 of primary coil L 1 . The signal S 21 is the signal corresponding to the rising edge of the transmission signal S 1 . Meanwhile, driving circuit 13 sends the differential signal S 22 to end L 12 of primary coil L 1 . The signal S 22 is the signal corresponding to the falling edge of the transmission signal S 1 .

In the case that a rectangular wave corresponding to data is simply applied to the transformer including primary coil L 1 and secondary coil L 2 , the AC component of the signal applied to primary coil L 1 is transmitted to secondary coil L 2 . However, if such a rectangular wave is applied to the transformer, a current is continuously supplied to primary coil L 1 and primary circuit 1 since the transformer has a low impedance to DC components. This configuration increases power consumption.

Meanwhile, in signal transmission circuit 100 according to the present embodiment, differential circuit 15 of primary circuit 1 removes a direct-current (DC) component of the signal applied to primary coil L 1 . This configuration prevents a current from being continuously supplied to primary coil L 1 and primary circuit 1 , hence preventing power consumption from increasing. Primary circuit 1 does not necessarily include differential circuit 15 .

Secondary circuit 2 includes AD converter 21 and extraction circuit 22 , as shown in FIGS. 1 and 2 . Secondary circuit 2 further includes transmission lines 24 and 25 through which the AC signals S 31 and S 32 propagate, respectively.

AD converter 21 converts the AC signals S 31 and S 32 , analog signals supplied from secondary coil L 2 , into digital pulse signals S 41 and S 42 , respectively, and outputs digital pulse signals S 41 and S 42 . AD converter 21 includes comparators 211 and 212 and voltage divider circuit 23 .

Comparators 211 and 212 are electrically connected to transmission lines 24 and 25 , respectively, and compare the AC signals S 31 and S 32 that propagate through transmission lines 24 and 25 with each other.

Comparator 211 has inverting input terminal 211 a which receives the AC signal S 31 . Comparator 211 further has non-inverting input terminal 211 b which receives a signal S 32 a which is obtained by adding an offset voltage Voff 1 to the AC signal S 32 . The offset voltage Voff 1 (see FIG. 5 ) is generated by resistor R 3 and constant current source IS 1 . Resistor R 3 is electrically connected between transmission line 25 and non-inverting input terminal 211 b of comparator 211 . Constant current source IS 1 is electrically connected between power-supply potential point Vdd and node P 101 at which one end of resistor R 3 is connected with non-inverting input terminal 211 b of comparator 211 .

Comparator 211 outputs the pulse signal S 41 . The level of the pulse signal S 41 is high when the signal S 32 a is larger than the AC signal S 31 . The level of the pulse signal S 41 is low when the signal S 32 a is not larger than the AC signal S 31 . The pulse signal S 41 is generated substantially at the timing of the falling edge of the transmission signal S 1 . Thus, comparator 211 outputs the signal (the pulse signal S 41 ) corresponding to the falling edge of the transmission signal S 1 .

Comparator 212 has inverting input terminal 212 a which receives the AC signal S 32 . Comparator 212 further has non-inverting input terminal 212 b which receives a signal 531 a which is obtained by adding an offset voltage Voff 2 to the AC signal S 31 . The offset voltage Voff 2 is generated by resistor R 4 and constant current source IS 2 . Resistor R 4 is electrically connected between transmission line 24 and non-inverting input terminal 212 b of comparator 212 . Constant current source IS 2 is electrically connected between power-supply potential point Vdd and node P 102 at which one end of resistor R 4 is connected with non-inverting input terminal 212 b of comparator 212 .

Comparator 212 outputs the pulse signal S 42 . The level of pulse signal S 42 is high when the signal 531 a is larger than the AC signal S 32 . The level of pulse signal S 42 is low when the signal 531 a is not larger than the AC signal S 32 . The pulse signal S 42 is generated substantially at the timing of the rising edge of the transmission signal S 1 . Thus, comparator 212 outputs the signal (the pulse signal S 42 ) corresponding to the rising edge of the transmission signal S 1 .

As described above, in signal transmission circuit 100 according to the present embodiment, the offset voltages Voff 1 and Voff 2 are supplied to non-inverting input terminals 211 b and 212 b of comparators 211 and 212 , respectively. This configuration prevents comparators 211 and 212 of signal transmission circuit 100 from causing chattering.

Signal transmission circuit 100 according to the present embodiment may preferably include a trimming circuit capable of arbitrarily adjusting the offset voltages Voff 1 and Voff 2 . The trimming circuit can adjust the sensitivities of comparators 211 and 212 if the sensitivities changes due to component variation. The trimming circuit adjusts the value of the current supplied, for example, from constant current sources IS 1 and IS 2 , thereby arbitrarily adjusting the offset voltages Voff 1 and Voff 2 . Signal transmission circuit 100 may not necessarily include the trimming circuit, and the offset voltages Voff 1 and Voff 2 may not necessarily be supplied to comparators 211 and 212 .

Voltage divider circuit 23 is configured to divide the voltage between transmission lines 24 and 25 . Voltage divider circuit 23 includes a series assembly including resistors R 1 and R 2 connected in series with each other. A first end of resistor R 1 is electrically connected to transmission line 24 . A first end of resistor R 2 is electrically connected to transmission line 25 . Second ends of resistors R 1 and R 2 are connected with each other at node P 103 where the intermediate voltage VC 1 between the voltages of transmission lines 24 and 25 is generated. In other words, the voltage VC 1 is a voltage obtained by voltage divider circuit 23 .

The intermediate voltage VC 1 is obtained by dividing the voltage between transmission lines 24 and 25 . Resistors R 1 and R 2 do not necessarily have the same common resistance value; however, resistors R 1 and R 2 have the same resistance value so that the circuit design can be simplified. Voltage divider circuit 23 may include a series assembly including three or more resistors connected in series with one another instead of two resistors R 1 and R 2 . Voltage divider circuit 23 may be implemented by a series assembly of plural capacitors connected in series with each other, instead of resistors. Signal transmission circuit 100 according to the present embodiment may not necessarily include voltage divider circuit 23 .

Extraction circuit 22 is implemented by, for example, an RS flip-flop circuit. Extraction circuit 22 extracts the transmission signal S 1 based on the pulse signals S 41 and S 42 and outputs the extracted signal as the output signal S 5 . In other words, extraction circuit 22 extracts the signal S 1 based on the comparison results of the comparators ( 211 and 212 ).

The term “extract the transmission signal S 1 ” means to extract the signal S 1 such that data transmitted from primary circuit 1 to secondary circuit 2 can be taken out. In other words, the signal S 1 extracted by extraction circuit 22 contain the same information as the signal S 1 applied to primary circuit 1 . Thus, the signal S 1 extracted by extraction circuit 22 may have a different waveform, such as amplitude, or may be delayed from the transmission signal S 1 applied to primary circuit 1 .

The pulse signal S 41 is applied to reset terminal 22 b , whereas the pulse signal S 42 is applied to set terminal 22 a of extraction circuit 22 . Extraction circuit 22 outputs the output signal S 5 . The level of the output signal S 5 is high when set terminal 22 a receives the pulse of the pulse signal S 42 . The level of the output signal S 5 is low when reset terminal 22 b receives the pulse of the pulse signal S 41 . As described above, the pulse signal S 41 generates a pulse substantially simultaneously to the falling edge of the signal S 1 . The pulse signal S 42 generates a pulse substantially simultaneously to the rising edge of the signal S 1 . As a result, the level of the output signal S 5 alternates high and low substantially simultaneously to the rising edge and the falling edge of the signal S 1 , respectively. Extraction circuit 22 thus extracts the transmission signal S 1 and output the extracted signal as the output signal S 5 .

FIG. 6A is a schematic block diagram of feedback circuit 4 . As shown in FIG. 6A , feedback circuit 4 includes differential amplifier circuit 41 and control circuit 42 . Control circuit 42 includes buffers 421 and 422 and a pair of terminals T 11 and T 12 . As shown in FIG. 2 , terminals T 11 and T 12 are electrically connected to nodes 26 and 27 , respectively. Nodes 26 and 27 are provided on transmission lines 24 and 25 , respectively. Terminals T 11 and T 12 maybe, for example, parts of conductors as wires on a substrate.

FIG. 6B is a schematic circuit diagram of differential amplifier circuit 41 and control circuit 42 . As shown in FIG. 6B , differential amplifier circuit 41 includes eight switching elements Q 5 to Q 12 and constant current source IS 5 . Switching elements Q 5 , Q 6 , Q 9 , and Q 12 are enhancement-mode n-channel MOSFETs, whereas switching elements Q 7 , Q 8 , Q 10 , and Q 11 are enhancement-mode p-channel MOSFETs. The gate of switching element Q 5 receives the reference voltage VR 1 . The voltage VR 1 is generated in, for example, a band gap reference (BGR) circuit. The gate of switching element Q 6 receives the intermediate voltage VC 1 . The sources of switching elements Q 5 and Q 6 are electrically connected to constant current source IS 5 . Constant current source IS 5 supplies a constant current to the circuit ground GND.

The drain of switching element Q 5 is electrically connected to the drain and gate of switching element Q 7 . The gate of switching element Q 7 is electrically connected to the gate of switching element Q 8 . The drain of switching element Q 8 is electrically connected to the drain and gate of switching element Q 9 . The sources of switching elements Q 7 and Q 8 are electrically connected to power-supply potential point Vdd. The source of switching element Q 9 is electrically connected to the circuit ground GND. Switching elements Q 5 , Q 7 , Q 8 , and Q 9 thus constitute a current mirror circuit.

The drain of switching element Q 6 is electrically connected to the drain and gate of switching element Q 10 . The gate of switching element Q 10 is electrically connected to the gate of switching element Q 11 . The drain of switching element Q 11 is electrically connected to the drain of switching element Q 12 . The gate of switching element Q 12 is electrically connected to the gate of switching element Q 9 . The sources of switching elements Q 10 and Q 11 are electrically connected to power-supply potential point Vdd. The source of switching element Q 12 is electrically connected to the circuit ground GND. Switching elements Q 6 , Q 10 , Q 11 , and Q 12 thus constitute a current mirror circuit.

Differential amplifier circuit 41 outputs, to buffers 421 and 422 , a current signal increasing and decreasing according to the difference between the intermediate voltage VC 1 and the reference voltage VR 1 . Differential amplifier circuit 41 increases the current signal when the intermediate voltage VC 1 exceeds the reference voltage VR 1 . Differential amplifier circuit 41 decreases the current signal when the intermediate voltage VC 1 is lower than the reference voltage VR 1 .

Buffer 421 is a current mirror circuit including three switching elements Q 13 to Q 15 , capacitor C 1 , and constant current source IS 6 , as shown in FIG. 6B . Switching elements Q 13 and Q 15 are enhancement-mode n-channel MOSFETs. Switching element Q 14 is an enhancement-mode p-channel MOSFET. Constant current source IS 6 supplies a constant current from power-supply potential point Vdd to the drain of switching element Q 13 . The drain and gate of switching element Q 13 are electrically connected to each other. The gate of switching element Q 13 is electrically connected to the gate of switching element Q 15 . The drain of switching element Q 15 is electrically connected to the drain of switching element Q 14 . The capacitor C 1 is electrically connected between the gate and drain of switching element Q 14 . The source of switching element Q 14 is electrically connected to power-supply potential point Vdd. The sources of switching elements Q 13 and Q 15 are electrically connected to the circuit ground GND.

Buffer 422 is a current mirror circuit including three switching element Q 13 , Q 16 , and Q 17 , capacitor C 2 , and constant current source IS 6 , as shown in FIG. 6B . Switching element Q 16 is an enhancement-mode p-channel MOSFET. Switching element Q 17 is an enhancement-mode n-channel MOSFET. Buffers 421 and 422 thus commonly share switching element Q 13 and constant current source IS 6 . The gate of switching element Q 17 is electrically connected to the gate of switching element Q 13 . The drain of switching element Q 17 is electrically connected to the drain of switching element Q 16 . The capacitor C 2 is electrically connected between the gate and drain of switching element Q 16 . The source of switching element Q 16 is electrically connected to power-supply potential point Vdd. The source of switching element Q 17 is electrically connected to the circuit ground GND.

Control circuit 42 controls the current flowing through nodes 26 and 27 according to the signal supplied from differential amplifier circuit 41 . When the intermediate voltage VC 1 exceeds the reference voltage VR 1 , currents flowing in the drains of switching elements Q 14 and Q 16 are larger than the current supplied from constant current source IS 6 , so that control circuit 42 supplies currents from terminals T 11 and T 12 to nodes 26 and 27 , respectively. When the intermediate voltage VC 1 is lower than the reference voltage VR 1 , currents flowing in the drains of switching elements Q 14 and Q 16 are smaller than the current supplied from constant current source IS 6 , so that control circuit 42 pulls currents from nodes 26 and 27 to terminals T 11 and T 12 , respectively.

Thus, feedback circuit 4 is electrically connected to nodes 26 and 27 provided on transmission lines 24 and 25 , respectively. Feedback circuit 4 feedbacks the intermediate voltage VC 1 by controlling the current flowing through nodes 26 and 27 according to the difference between the intermediate voltage VC 1 and the reference voltage VR 1 .

Nodes 26 and 27 are preferably connected directly to input ports T 1 and T 2 of secondary circuit 2 , and are also preferably connected directly to both ends of secondary coil L 2 which generates the AC signals S 31 and S 32 . In other words, nodes 26 and 27 are preferably connected to input ports T 1 and T 2 (or both ends of secondary coil L 2 ) in order to reduce wiring impedance between each of nodes 26 and 27 and respective one of input ports T 1 and T 2 (or both ends of secondary coil L 2 ). In this configuration, feedback circuit 4 can feedback the intermediate voltage VC 1 so as to reduce influence of the wiring impedance between transmission lines 24 and 25 .

An operation of signal transmission circuit 100 according to the embodiment will be briefly described below. Primary circuit 1 generates the differential signals S 21 and S 22 from the transmission signal S 1 and transmits the differential signals S 21 and S 22 to primary coil L 1 . Upon receiving the differential signals S 21 and S 22 , an alternating-current (AC) current flows in primary coil L 1 . When the AC current flows in primary coil L 1 , secondary coil L 2 generates AC signals S 31 and S 32 containing AC components of the signals S 21 and S 22 .

In secondary circuit 2 , comparator 211 compares the AC signals S 31 and S 32 , and outputs the pulse signal S 41 corresponding to the falling edge of the transmission signal S 1 . Comparator 212 compares the AC signals S 31 and S 32 , and outputs the pulse signal S 42 corresponding to the rising edge of the transmission signal S 1 . Then, extraction circuit 22 extracts the transmission signal S 1 from the pulse signals S 41 and S 42 , and outputs the extracted signal as the output signal S 5 .

In signal transmission circuit 100 according to the embodiment, primary circuit 1 generates the differential signals S 21 and S 22 from the received transmission signal S 1 , and transmits the differential signals S 21 and S 22 to secondary circuit 2 via insulation circuit 3 . Then, secondary circuit 2 extracts the transmission signal S 1 from the signals received from primary circuit 1 , and outputs the output signal S 5 corresponding to the transmission signal S 1 .

Parasitic capacitances Cp 1 and Cp 2 exist between primary coil L 1 (the primary element) and secondary coil L 2 (the secondary element), as shown in FIG. 2 . If noise, especially common mode noise is applied to primary circuit 1 due to, for example, lightning surges, the noise may be transmitted to secondary circuit 2 via the parasitic capacitances Cp 1 and Cp 2 .

FIG. 7 is a schematic circuit diagram of secondary circuit 200 of a comparative example of a signal transmission circuit. In FIG. 7 , components identical to those of secondary circuit 2 shown in FIG. 2 are denoted by the same reference numerals. As shown in FIG. 7 , the comparative example of the signal transmission circuit (secondary circuit 200 ) is identical to signal transmission circuit 100 (secondary circuit 2 ) according to the present embodiment except that secondary circuit 200 does not include feedback circuit 4 . An operation of the primary circuit of the comparative example of the signal transmission circuit upon having noise applied thereto will be described below. FIG. 8 shows signal waveforms obtained by a simulation in which common mode noise is applied to the primary circuit of the comparative example of the signal transmission circuit. In FIG. 8 , the vertical axis represents signal values, and the horizontal axis represents time.

In the simulation shown in FIG. 8 for the comparative example of the signal transmission circuit, several tens of kilovolts of positive-polarity voltage CN 1 , a simulated common mode noise, is applied to the primary circuit for a period from time point t 0 to time point t 3 . The intermediate voltage VC 1 increases for the period (e.g, 1 μs) between time points t 0 and t 1 , whereas the voltage levels of the AC signals S 31 and S 32 decrease for the period. Therefore, in the example shown in FIG. 8 , comparators 211 and 212 may malfunction when the voltage levels of the AC signals S 31 and S 32 fall outside allowable input voltage ranges of comparators 211 and 212 .

Similarly, the intermediate voltage VC 1 decreases for a period (e.g., 1 μs) between time points t 2 and t 3 , whereas the voltage levels of the AC signals S 31 and S 32 increase for the period. Therefore, in the example shown in FIG. 8 , comparators 211 and 212 may malfunction when the voltage levels of the AC signals S 31 and S 32 fall outside the allowable input voltage range of comparators 211 and 212 . Hence, the comparative example of the signal transmission circuit may produce abnormalities in the pulse signals S 41 and S 42 applied to extraction circuit 22 . In this case, the output signal S 5 of extraction circuit 22 may not be output properly. This may cause transmission errors of the transmission signal S 1 .

Even in the above-described conventional signal transmission circuit, if noise is applied to the primary circuit due to, for example, lightning surges, the noise can be transmitted to the secondary circuit, possibly causing the secondary circuit to malfunction.

An operation of primary circuit 1 of signal transmission circuit 100 according to the embodiment upon having noise applied thereto will be described below. FIG. 9 shows signal waveforms indicating simulation results when common mode noise is applied to primary circuit 1 of circuit 100 according to the present embodiment. In FIG. 9 , the vertical axis represents signal values, and the horizontal axis represents time.

In signal transmission circuit 100 according to the present embodiment, as shown in FIG. 9 , even if the positive-polarity voltage CN 1 , a simulated common mode noise, is applied, the intermediate voltage VC 1 hardly changes since feedback circuit 4 feedbacks the intermediate voltage VC 1 so as to converge the intermediate voltage VC 1 to the reference voltage VR 1 . For the same reason, the intermediate voltage VC 1 hardly changes when the negative-polarity voltage CN 1 is applied. Therefore, the voltage levels of the AC signals S 31 and S 32 hardly change, and hardly fall outside the allowable input voltage ranges of comparators 211 and 212 . As a result, comparators 211 and 212 hardly malfunction.

Thus, signal transmission circuit 100 according to the present embodiment hardly causes abnormalities in the pulse signals S 41 and S 42 applied to extraction circuit 22 , so that extraction circuit 22 can output the output signal S 5 properly. Signal transmission circuit 100 thus hardly causes transmission errors of the transmission signal S 1 .

As described above, in signal transmission circuit 100 according to the present embodiment, even if noise is applied to primary circuit 1 and transmitted to secondary circuit 2 , feedback circuit 4 converges the intermediate voltage VC 1 to the reference voltage VR 1 . This configuration reduces variations in the input voltage to secondary circuit 2 (particularly, the input voltage to comparators 211 and 212 ). For this reason, in signal transmission circuit 100 , noise applied to primary circuit 1 hardly causes secondary circuit 2 to malfunction.

The malfunction of secondary circuit 2 due to the noise applied to primary circuit 1 may be reduced by insulation circuit 3 including two transformers each including primary coil L 1 and secondary coil L 2 . However, this configuration with two transformers increases circuit size and cost.

In signal transmission circuit 100 according to the present embodiment, feedback circuit 4 allows secondary circuit 2 to be less likely to malfunction without two transformers, consequently preventing the size cost of circuitry from increasing.

In signal transmission circuit 100 according to the present embodiment, the frequency of possible noise (common mode noise) is at most several hundreds of megahertz although it depends on the frequency of occurrence of noise. On the other hand, the frequencies of the AC signals S 31 and S 32 supplied from secondary coil L 2 (the secondary element) are higher than several hundreds of megahertz or are several gigahertz in accordance with properties of the transformer (primary coil L 1 and secondary coil L 2 ).

The AC signals S 31 and S 32 are differential signals, and may not be removed by feedback circuit 4 which removes in-phase components, such as common mode noise. However, considering exceptional cases, feedback circuit 4 preferably remove only common mode noise and not to affect the AC signals S 31 and S 32 .

For this reason, in signal transmission circuit 100 of the present embodiment, feedback circuit 4 preferably limits the propagation of the AC signals S 31 and S 32 . FIG. 10 shows frequency characteristics of feedback circuit 4 . Assuming that the common mode noise has frequencies ranging from 0 to frequency f 0 (Hz), and the AC signals S 31 and S 32 have frequencies ranging from frequency f 1 to frequency f 2 (Hz), as shown in FIG. 10 . In this case, feedback circuit 4 preferably has a cut-off frequency fc 1 between frequencies f 0 and f 1 , that is, satisfies the relation, f 0 <fc 1 <f 1 . In this configuration, feedback circuit 4 responds to the common mode noise with frequencies lower than the cut-off frequency fc 1 and hardly responds to the AC signals S 31 and S 32 with frequencies higher than the cut-off frequency fc 1 .

The cut-off frequency fc 1 is determined by a capacitive component and a resistance component present in feedback circuit 4 . The capacitive and resistance components can be properly modified by adjusting the size of switching elements Q 5 to Q 17 of feedback circuit 4 or the current supplied from the constant current source IS 3 .

In signal transmission circuit 100 according to the present embodiment, insulation circuit 3 includes primary coil L 1 (the primary element) and secondary coil L 2 (the secondary element) which are magnetically coupled with each other. The primary element and the secondary element are thus magnetically coupled with each other Alternatively, the primary element and the secondary element may be coupled with each other in another effect.

FIG. 11 is a schematic circuit diagram of primary circuit 1 a and insulation circuit 3 a of the signal transmission circuit according to the present embodiment. In FIG. 11 , components identical to those of primary circuit 1 and insulation circuit 3 of signal transmission circuit 100 shown in FIG. 2 are denoted by the same reference numerals. Primary circuit 1 a includes buffers 16 and 17 in place of driving circuit 13 of primary circuit 1 shown in FIG. 2 . Each of buffers 16 and 17 has an input port connected to respective one of the output ports of differential circuit 15 . Insulation circuit 3 a includes capacitor C 11 including opposing electrodes C 11 a and C 11 b which form the capacitance of capacitor C 11 . Insulation circuit 3 a further includes capacitor C 12 including opposing electrodes C 12 a and C 12 b which form the capacitance of capacitor C 12 . Electrodes C 11 a and C 12 a of capacitors C 11 and C 12 are electrically connected to respective output ports of buffers 16 and 17 of primary circuit 1 a . Electrodes C 11 b and C 12 b of capacitors C 11 and C 12 are connected to input ports T 1 and T 2 of secondary circuit 2 , respectively. In capacitors C 11 and C 12 , electrodes C 11 a and C 12 a adjacent to primary circuit 1 function as the primary element, and electrodes C 11 b and C 12 b adjacent to secondary circuit 2 function as the secondary element. In other words, in signal transmission circuit 100 according to the present embodiment, the primary element may be capacitively coupled with the secondary element.

100 signal transmission circuit

1 primary circuit

13 driving circuit

15 differential circuit

2 secondary circuit

211 comparator (first comparator)

212 comparator (second comparator)

22 extraction circuit

23 voltage divider circuit

24 , 25 a pair of transmission lines

26 , 27 node

4 feedback circuit

S 1 transmission signal

S 21 , S 22 differential signal

L 1 primary coil (primary element)

L 11 end (first end)

L 12 end (second end)

L 2 secondary coil (secondary element)

S 31 , S 32 AC signal

VC 1 intermediate voltage

VR 1 reference voltage

T 1 , T 2 input port