On-board control device, on-board integrated circuit

The present invention relates to a vehicle-mounted integrated circuit and a vehicle-mounted control device using the vehicle-mounted integrated circuit.

In recent years, various devices mounted on vehicles have been electronically controlled, and, for example, in function of monitoring output values from power generation units, sensors, or drive devices of vehicle-mounted control devices, semiconductor integrated circuits have been widely used.

A long time operation of these semiconductor integrated circuits gradually changes the characteristics thereof due to influence of hot carrier, negative bias temperature instability (NBTI), wire migration, or the like, and thus, the characteristics of vehicle-mounted control devices may be deteriorated and the deterioration may influence vehicle control.

Technologies for detecting the presence/absence of failure by self tests or the like for semiconductor integrated circuits after shipment have been disclosed. For example, the following PTL 1 describes a semiconductor integrated circuit “configured to supply outputs at three levels of the high level, the low level, and the intermediate level generated by the diagnostic signal generation circuit, to an analog signal input terminal of the A/D converter to perform A/D conversion, the semiconductor integrated circuit diagnosing success or failure in performance of the A/D converter on the basis of a digital output from the A/D converter” (see claim 1 ).

Patent Literature

PTL 1: JP 2007-309773 A

Technical Problem

In PTL 1, as seen from the description “diagnosing success or failure in performance of the A/D converter on the basis of a digital output from the A/D converter”, normal operation disabled by an abnormal condition generated in the circuit can be detected, but detection of a change in characteristics due to the age deterioration or the like of the circuit is not taken into consideration. Therefore, the lifetimes of the semiconductor integrated circuit and a vehicle-mounted control device using the semiconductor integrated circuit may be reduced relative to expected lifetimes thereof.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit which can continuously and stably generate an output value even after shipment and a vehicle-mounted control device using the semiconductor integrated circuit.

Solution to Problem

The present invention includes a reference signal generation unit for outputting a reference signal, and detects the operation state of a semiconductor circuit on the basis of a difference between output values from the semiconductor circuit corresponding to the reference signals output at two different time points by the reference signal generation unit.

Advantageous Effects of Invention

According to the present invention, even when the characteristics of a semiconductor circuit varies with time, the variation can be detected and output values can be stably generated continuously. Problems, configurations, and effects other than the above description will be made clear by the following description of the embodiments.

FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated device 1 according to a first embodiment.

FIG. 2 is a flowchart illustrating operation of the semiconductor integrated device 1 before shipment.

FIG. 3 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment.

FIG. 4 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment.

FIG. 5 is a block diagram illustrating a configuration of a vehicle-mounted control device U 1 according to a second embodiment.

FIG. 6 is a graph illustrating an example of a change in load current IL over time.

FIG. 7 is a block diagram illustrating a configuration of a vehicle-mounted control device according to a third embodiment.

FIG. 8 is a block diagram illustrating a configuration of a vehicle-mounted control device according to a fourth embodiment.

FIG. 9 is a block diagram illustrating a configuration of a semiconductor integrated device 1 according to a fifth embodiment.

FIG. 10 is a flowchart illustrating operation of the semiconductor integrated device 1 before shipment.

FIG. 11 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment.

FIG. 12 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment.

FIG. 13 is a block diagram illustrating a configuration of a semiconductor integrated device 1 according to a sixth embodiment.

FIG. 14 is a flowchart illustrating operation of the semiconductor integrated device 1 before shipment.

FIG. 15 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment.

FIG. 16 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment.

FIG. 17 is a block diagram illustrating a configuration of a semiconductor integrated device 1 according to a seventh embodiment.

FIG. 18 is a flowchart illustrating operation of the semiconductor integrated device 1 before shipment.

FIG. 19 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment.

FIG. 20 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment.

FIG. 21 is a block diagram illustrating a configuration of a semiconductor integrated device 1 according to an eighth embodiment.

FIG. 22 is a flowchart illustrating operation of the semiconductor integrated device 1 before shipment.

FIG. 23 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment.

FIG. 24 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment.

First Embodiment

FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated device 1 according to a first embodiment of the present invention. The semiconductor integrated device 1 is a device mounted, for example, on a vehicle and outputting a signal used to control a vehicle-mounted device. The semiconductor integrated device 1 includes an input circuit 100 , a reference signal generator 200 , an input switching circuit 300 , a semiconductor circuit 400 , an initial value storage circuit 500 , a difference operation circuit 600 , a correction-value storage circuit 700 , a write circuit S 3 , and a write circuit S 4 .

The input circuit 100 is a circuit, such as a sensor circuit of a vehicle-mounted control device or a drive current monitoring circuit of an electromagnetic load drive device, for providing a signal being an input value to the semiconductor circuit 400 . The reference signal generator 200 generates a reference signal used as a reference for measurement of a characteristic variation of the semiconductor circuit 400 over time. The input switching circuit 300 includes switching circuits S 1 and S 2 , and switches the switching circuits S 1 and S 2 to transmit an output 101 from the input circuit 100 or a reference signal 201 from the reference signal generator 200 to the semiconductor circuit 400 . The semiconductor circuit 400 is a circuit for outputting a signal used to control, for example, a vehicle-mounted device, and includes a signal processing circuit 401 and a correction circuit 800 . The initial value storage circuit 500 is a storage element, such as a memory device, and stores an output value from the correction circuit 800 . The write circuit S 3 switches writing of a value to the initial value storage circuit 500 . The difference operation circuit 600 calculates a difference between an output 501 from the initial value storage circuit 500 and an output 801 from the correction circuit 800 . The correction-value storage circuit 700 is a storage element, such as a register, and stores an output 601 from the difference operation circuit 600 . The write circuit S 4 switches writing of a value to the correction-value storage circuit 700 .

The signal processing circuit 401 is a circuit performing for example signal conversion on an output 301 from the input switching circuit 300 , and includes, for example, an AD converter. The correction circuit 800 uses an output 701 from the correction-value storage circuit 700 to correct an output 403 from the signal processing circuit 401 (e.g., add both outputs to correct a difference between both output values), and generates an output 801 as a result of the correction.

FIG. 2 is a flowchart illustrating operation of the semiconductor integrated device 1 before shipment. Before shipment, the semiconductor integrated device 1 turns off the switching circuit S 1 , turns on the switching circuit S 2 , turns on the write circuit S 3 , and turns off the write circuit S 4 (S 201 ). The semiconductor integrated device 1 activates the reference signal generator 200 (S 202 ). The semiconductor integrated device 1 sets an output 701 from the correction-value storage circuit 700 to zero (S 203 ). When the semiconductor circuit 400 is operated in this condition (S 204 ), the semiconductor circuit 400 outputs an output value Y 1 according to the reference signal 201 from the reference signal generator 200 , and Y 1 is stored in the initial value storage circuit 500 (S 205 ).

The flowchart of FIG. 2 has significance in storage of an output value from the semiconductor circuit 400 , at a time point before shipment of the semiconductor integrated device 1 (i.e., before the characteristic variation of the semiconductor circuit 400 over time). Accordingly, this operation is preferably performed, for example, in a release test for the semiconductor integrated device 1 .

FIG. 3 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment. The flowchart of FIG. 3 illustrates the process of determining a correction amount for an output value from the semiconductor circuit 400 , and the steps of the flowchart are preferably performed, for example, upon activation of the semiconductor integrated device 1 .

The semiconductor integrated device 1 turns off the switching circuit S 1 , turns on the switching circuit S 2 , turns off the write circuit S 3 , and turns on the write circuit S 4 (S 301 ). The semiconductor integrated device 1 activates the reference signal generator 200 (S 302 ). The semiconductor integrated device 1 sets an output 701 from the correction-value storage circuit 700 to zero (S 303 ). When the semiconductor circuit 400 is operated in this condition, the semiconductor circuit 400 outputs an output value Y 2 according to the reference signal 201 from the reference signal generator 200 (S 304 ). The difference operation circuit 600 calculates a difference between Y 2 and an output 501 representing a value stored in the initial value storage circuit 500 at a time point before shipment, and stores an output 601 representing a result of the calculation in the correction-value storage circuit 700 (S 305 ). The semiconductor integrated device 1 turns off the reference signal generator 200 (S 306 ).

In the flowchart of FIG. 3 , a variation of the semiconductor circuit 400 over time caused by operation of the semiconductor integrated device 1 after shipment can be obtained for an initial value Y 1 determined before shipment. The variation can be used as a correction value to correct the characteristic variation of the semiconductor circuit 400 over time. The correction value can be calculated, for example, on the basis of the following formula (A1):

correction value= Y 1− Y 2  (A1)

FIG. 4 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment. The flowchart of FIG. 4 illustrates the steps of correcting a characteristic variation of the semiconductor circuit 400 over time during normal operation of the semiconductor integrated device 1 .

The semiconductor integrated device 1 turns on the switching circuit S 1 , turns off the switching circuit S 2 , turns off the write circuit S 3 , and turns off the write circuit S 4 (S 401 ). The semiconductor integrated device 1 turns off the reference signal generator 200 (S 402 ). The correction-value storage circuit 700 outputs the correction value stored in the flowchart of FIG. 3 (S 403 ). The semiconductor integrated device 1 operates the input circuit 100 and the semiconductor circuit 400 (S 404 ). The correction circuit 800 applies the correction value output from the correction-value storage circuit 700 to an output 403 from the semiconductor circuit 400 to correct the variation of the output 403 from the semiconductor circuit 400 over time and generate an output 801 after correction (S 405 ).

In addition to the variation of the semiconductor circuit 400 over time, the age deterioration of the reference signal generator 200 , the initial value storage circuit 500 , the difference operation circuit 600 , the write circuit S 3 , and the write circuit S 4 can be also prevented. For example, in a normal operation state, stopping the operation of these circuits prevents the age deterioration of these circuits, thus enabling appropriate correction amount detection according to the flowchart of FIG. 3 . Hereinafter, a specific process will be described.

It is known that a threshold voltage of a semiconductor device, such as a metal oxide semiconductor (MOS) transistor, varies with time while a voltage is applied to the gate terminal. When a supply voltage to the reference signal generator 200 is shut off, a gate voltage of a MOS device of the reference signal generator 200 is reduced to zero, thus preventing the variation thereof over time. Alternatively, an appropriate switch can be used to change the gate voltage to zero without shutting off the supply voltage, thus obtaining the same effects.

It is known that a semiconductor device (e.g., MOS transistor) of the reference signal generator 200 exposed to high temperature varies with time at an accelerating rate. Therefore, a heat insulating portion can be provided between the reference signal generator 200 and heat generating portions to prevent age deterioration. Here, a representative example of a heat generating portion includes a microcontroller performing control calculation. When the reference signal generator 200 is separated as much as possible from these heat generating portions, air between the circuits functions as the heat insulating portion. Alternately, between the reference signal generator 200 and the heat generating portions, another heat-resistant member (structural member, another electrical component having characteristics hardly deteriorated by heat, or the like) may be arranged to be functioned as the heat insulating portion.

First Embodiment: Effects

As described above, according to the semiconductor integrated device 1 according to the present first embodiment, even when the characteristics of the semiconductor circuit 400 vary with time, the output 801 having the characteristics equal to those in an initial state upon shipment of the semiconductor integrated device 1 can be generated. Accordingly, the semiconductor integrated device 1 can maintain initial performance upon shipment.

Second Embodiment

FIG. 5 is a block diagram illustrating a configuration of a vehicle-mounted control device U 1 according to a second embodiment of the present invention. The vehicle-mounted control device U 1 includes the semiconductor integrated device 1 described in the first embodiment, a controller 900 , an electromagnetic load drive circuit 902 , an electromagnetic load 903 , and a load current monitoring circuit 904 .

The controller 900 includes a calculation control device, such as a microcontroller, and outputs a control signal 901 for controlling the electromagnetic load drive circuit 902 in accordance with the output 801 from the semiconductor integrated device 1 . The electromagnetic load drive circuit 902 drives the electromagnetic load 903 in accordance with the control signal 901 . The electromagnetic load 903 is a load circuit, such as a solenoid, used for control of vehicle operation. The load current monitoring circuit 904 monitors the load current IL running through the electromagnetic load 903 , and outputs a result of the monitoring as a monitor signal 905 to the input circuit 100 of the semiconductor integrated device 1 .

The semiconductor circuit 400 performs processing, such as conversion of the monitor signal 905 received by the input circuit 100 to, for example, a digital signal, and outputs the digital signal to the controller 900 . The controller 900 monitors the load current IL on the basis of the output 801 from the semiconductor circuit 400 , and outputs the control signal 901 in accordance with the load current IL. Therefore, the load current IL flowing through the electromagnetic load 903 can be controlled highly accurately.

FIG. 6 is a graph illustrating an example of a change in load current IL over time. The semiconductor circuit 400 sometimes generates an output 801 (current before correction in FIG. 6 ) having characteristics changed due to, for example, a variation over time with the passage of operating time, and thereby representing a value different from the monitor signal 905 received by the input circuit 100 . Then, the controller 900 outputs a control signal 901 on the basis of a value different from the actual load current IL.

The output 403 from the semiconductor circuit 400 is corrected (current after correction in FIG. 6 ) by using the configuration described in the first embodiment and thereby an output from the semiconductor integrated device 1 can be generated with accuracy equal to that set at the factory before shipment. Thus, an accuracy of a result of monitoring the load current IL being an output from the vehicle-mounted control device U 1 can be maintained.

Operation of determining a correction value described in FIG. 3 is preferably performed, for example, upon activation of the vehicle-mounted control device U 1 , or performed by the controller 900 by controlling the semiconductor integrated device 1 to perform the steps of the flowchart of FIG. 3 , if necessary.

Second Embodiment: Effects

As described above, according to the vehicle-mounted control device U 1 according to the present second embodiment, even when the characteristics of the semiconductor circuit 400 vary with time, the output 801 can be obtained with accuracy equal to that set before shipment. Thus, the failure of the controller 900 , wrong operation of a vehicle/vehicle-mounted device as a result of the failure, or the like can be prevented.

Third Embodiment

FIG. 7 is a block diagram illustrating a configuration of a vehicle-mounted control device according to a third embodiment of the present invention. The vehicle-mounted control device illustrated in FIG. 7 includes a detection circuit IC (integrated circuit) 1 and a controller IC 2 . The detection circuit IC 1 includes the semiconductor integrated device 1 , which has been described in the first embodiment. The controller IC 2 includes the controller 900 , which has been described in the second embodiment. These circuits are put together in the respective ICs, and thus the number of signal lines of the vehicle-mounted control device can be reduced to reduce the size of the device.

Fourth Embodiment

FIG. 8 is a block diagram illustrating a configuration of a vehicle-mounted control device according to a fourth embodiment of the present invention. The vehicle-mounted control device illustrated in FIG. 8 includes a detection circuit IC 3 and a controller IC 4 . The detection circuit IC 3 includes the input circuit 100 , the reference signal generator 200 , the input switching circuit 300 , and part of the semiconductor circuit 400 (e.g., an amplifier circuit 404 ) of the configuration described in the first embodiment. The controller IC 4 includes the rest of the semiconductor circuit 400 (e.g., an AD converter 405 ), the initial value storage circuit 500 , the difference operation circuit 600 , the correction-value storage circuit 700 , the correction circuit 800 , the write circuit S 3 , the write circuit S 4 , and further includes the controller 900 described in the second embodiment. The vehicle-mounted control device according to the present fourth embodiment can provide effects similar to those of the first to third embodiments.

Fifth Embodiment

FIG. 9 is a block diagram illustrating a configuration of a semiconductor integrated device 1 according to a fifth embodiment of the present invention. The semiconductor integrated device 1 according to the present fifth embodiment includes a temperature monitor circuit 503 and a selector circuit 505 , in addition to the configuration described in the first embodiment. Furthermore, the initial value storage circuit 500 stores a plurality of initial values (Y 1 _ 1 to Y 1 _ n ). The other configurations are basically similar to those of the first embodiment, and thus different points will be mainly described below.

The temperature monitor circuit 503 measures the temperature of the semiconductor integrated device 1 (in particular, the temperature of the semiconductor circuit 400 ), and outputs a result of the measurement as an output 504 . The selector circuit 505 selects an initial value corresponding to the output 504 from the temperature monitor circuit 503 , from a plurality of initial values stored in the initial value storage circuit 500 , and generates the selected initial value as the output 501 .

FIG. 10 is a flowchart illustrating operation of the semiconductor integrated device 1 before shipment. In step S 1002 , the temperature of the semiconductor integrated device 1 is measured more than once, and an initial value corresponding to each measurement is stored in the initial value storage circuit 500 , in step S 1006 . The other steps are similar to the steps of FIG. 2 . For preparation of diverse initial values, it is desirable to store initial values which are acquired in temperature conditions within as wide operation temperature range as possible of, for example, the semiconductor integrated device 1 (in particular, the semiconductor circuit 400 ). The initial value storage circuit 500 can store a pair of each initial value and a measurement result of the initial value from the temperature monitor circuit 503 .

FIG. 11 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment. In step S 1105 , the selector circuit 505 acquires a measurement result from the temperature monitor circuit 503 , and selects an initial value corresponding to the measurement result. In step S 1106 , the difference operation circuit 600 calculates a difference between the initial value selected by the selector circuit 505 and Y 2 . The other steps are similar to the steps of FIG. 3 .

FIG. 12 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment. In step S 1203 , the correction-value storage circuit 700 outputs a correction value corresponding to the initial value selected by the selector circuit 505 (corresponding to the measurement result from the temperature monitor circuit 503 ). The other steps are similar to the steps of FIG. 4 .

Fifth Embodiment: Effects

As described above, the semiconductor integrated device 1 according to the present fifth embodiment uses a correction value corresponding to a temperature upon operation to correct an output from the semiconductor circuit 400 . Thus, a temperature dependence of a characteristic variation can be corrected.

Sixth Embodiment

FIG. 13 is a block diagram illustrating a configuration of a semiconductor integrated device 1 according to a sixth embodiment of the present invention. The semiconductor integrated device 1 according to the present sixth embodiment includes a second reference signal generator 202 , in addition to the configuration described in the first embodiment. The second reference signal generator 202 outputs a second reference signal 203 having a signal level different from that of the reference signal generator 200 . The input switching circuit 300 includes a switching circuit S 5 in addition to the configuration described in the first embodiment. The initial value storage circuit 500 can store two initial values (Y 1 and Y 1 ′). The difference operation circuit 600 determines a correction value relating to the above configuration, which is described later. The other configurations are basically similar to those of the first embodiment, and thus different points will be mainly described below.

FIG. 14 is a flowchart illustrating operation of the semiconductor integrated device 1 before shipment. In step S 1401 , the input switching circuit 300 turns on only the switching circuit S 2 corresponding to the reference signal generator 200 . In step S 1402 , the reference signal generator 200 and the second reference signal generator 202 are operated. Thereby, the initial value storage circuit 500 stores the initial value Y 1 corresponding to the reference signal 201 . In step S 1406 , the input switching circuit 300 turns on only the switching circuit S 5 corresponding to the second reference signal generator 202 . When the semiconductor circuit 400 is operated in this condition (S 1407 ), the initial value storage circuit 500 stores an initial value Y 1 ′ corresponding to the second reference signal 203 .

From the viewpoint of correction value calculation, which is described later, it is desirable that the reference signal generator 200 outputs the reference signal 201 which corresponds to a maximum value within an input range of the semiconductor circuit 400 , and the second reference signal generator 202 outputs the second reference signal 203 which corresponds to a minimum value within the input range of the semiconductor circuit 400 .

FIG. 15 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment. In step S 1501 to S 1504 , the semiconductor integrated device 1 acquires the output value Y 2 from the semiconductor circuit 400 corresponding to the reference signal 201 . In step S 1505 to S 1507 , the semiconductor integrated device 1 similarly acquires an output value Y 2 ′ from the semiconductor circuit 400 corresponding to the second reference signal 203 . In step S 1508 , the difference operation circuit 600 calculates an offset variation and a gain variation on the basis of the characteristic variation of the semiconductor circuit 400 over time, in accordance with the following formulas A2 and A3. The correction-value storage circuit 700 stores these offset variation and gain variation as correction values.

Offset variation= Y 1− Y 2  (A2)

Gain variation=( Y 2− Y 2′)/( Y 1− Y 1′)  (A3)

FIG. 16 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment. In step S 1603 , the correction circuit 800 uses the offset variation and the gain variation stored in the correction-value storage circuit 700 to correct an offset and a gain of the semiconductor circuit 400 . The other steps are similar to the steps of FIG. 4 .

Seventh Embodiment

FIG. 17 is a block diagram illustrating a configuration of a semiconductor integrated device 1 according to a seventh embodiment of the present invention. The semiconductor integrated device 1 according to the present seventh embodiment is a device for generating and outputting a signal by itself, and includes the semiconductor circuit 400 , the initial value storage circuit 500 , the difference operation circuit 600 , the correction-value storage circuit 700 , the write circuit S 3 , and the write circuit S 4 .

In the present seventh embodiment, the semiconductor circuit 400 includes a signal generator 402 for generating an output 407 , and a regulator circuit 406 for regulating the output 407 . The regulator circuit 406 corrects the output 407 from the signal generator 402 , in accordance with the output 701 from the correction-value storage circuit 700 , that is, a correction value. The functions of the initial value storage circuit 500 , the difference operation circuit 600 , the correction-value storage circuit 700 , the write circuit S 3 , and the write circuit S 4 are similar to those in the first embodiment.

FIG. 18 is a flowchart illustrating operation of the semiconductor integrated device 1 before shipment. Before shipment, the semiconductor integrated device 1 turns on the write circuit S 3 , and turns off the write circuit S 4 (S 1801 ). The semiconductor integrated device 1 sets the output 701 from the correction-value storage circuit 700 to zero (S 1802 ). The regulator circuit 406 performs regulation corresponding to the correction value (e.g., no regulation). When the semiconductor circuit 400 is operated in this condition (S 1803 ), the initial value storage circuit 500 stores a value corresponding to the output 407 from the signal generator 402 (S 1804 ). The steps of the flowchart of FIG. 18 are preferably performed, for example, in a release test for the semiconductor integrated device 1 , as in FIG. 2 .

FIG. 19 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment. The steps of the flowchart of FIG. 19 are preferably performed, for example, upon activation of the semiconductor integrated device 1 , as in FIG. 3 .

The semiconductor integrated device 1 turns off the write circuit S 3 , and turns on the write circuit S 4 (S 1901 ). The semiconductor integrated device 1 sets the output 701 from the correction-value storage circuit 700 to zero (S 1902 ). When the semiconductor circuit 400 is operated in this condition, the semiconductor circuit 400 outputs the output value Y 2 (S 1903 ). The difference operation circuit 600 calculates a difference between Y 2 and the output 501 representing a value stored in the initial value storage circuit 500 at a time point before shipment, and stores the output 601 representing a result of the calculation in the correction-value storage circuit 700 (S 1904 ). In accordance with the flowchart of FIG. 19 , a variation of the semiconductor circuit 400 over time caused by the operation of the semiconductor integrated device 1 after shipment can be obtained for the initial value Y 1 determined before shipment.

FIG. 20 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment. The flowchart of FIG. 20 illustrates the steps of correcting a characteristic variation of the semiconductor circuit 400 over time during normal operation of the semiconductor integrated device 1 , as in FIG. 4 . The semiconductor integrated device 1 turns off the write circuit S 3 , and turns off the write circuit S 4 (S 2001 ). Step S 2002 to S 2004 are similar to steps S 403 to S 405 .

Seventh Embodiment: Effects

As described above, even when the characteristics of the semiconductor circuit 400 and the correction-value storage circuit 700 vary with time, the semiconductor integrated device 1 according to the present seventh embodiment can maintain the characteristics of the output 407 upon shipment, as in the first embodiment. Furthermore, the operations of the initial value storage circuit 500 , the difference operation circuit 600 , the write circuit S 3 , and the write circuit S 4 are stopped, and thereby the age deterioration of these circuits can be also prevented, as in the first embodiment.

Eighth Embodiment

FIG. 21 is a block diagram illustrating a configuration of a semiconductor integrated device 1 according to an eighth embodiment of the present invention. The semiconductor integrated device 1 according to the present eighth embodiment includes the input circuit 100 , the reference signal generator 200 , the input switching circuit 300 , the semiconductor circuit 400 , the initial value storage circuit 500 , the difference operation circuit 600 , a threshold generation circuit 702 , a determination circuit 703 , and the write circuit S 3 . The functions of the input circuit 100 , the reference signal generator 200 , the input switching circuit 300 , the initial value storage circuit 500 , the difference operation circuit 600 , and the write circuit S 3 are basically similar to those of the first embodiment, and thus different points about the other configurations will be described below.

In the present eighth embodiment, unlike the first embodiment, the semiconductor circuit 400 does not include the correction circuit 800 . Accordingly, the difference operation circuit 600 calculates a difference between the output 403 from the semiconductor circuit 400 and the initial value Y 1 stored in the initial value storage circuit 500 .

The threshold generation circuit 702 generates a threshold value previously set, and generates an output 704 representing the threshold value. The determination circuit 703 compares the output 601 from the difference operation circuit 600 and the output 704 from the threshold generation circuit 702 , and outputs a determination result 705 .

FIG. 22 is a flowchart illustrating operation of the semiconductor integrated device 1 before shipment. Before shipment, the semiconductor integrated device 1 turns off the switching circuit S 1 , turns on the switching circuit S 2 , and turns on the write circuit S 3 (S 2201 ). The semiconductor integrated device 1 activates the reference signal generator 200 , and turns off the determination circuit 703 (S 2202 ). When the semiconductor circuit 400 is operated in this condition (S 2203 ), the semiconductor circuit 400 outputs an output value Y 1 according to the reference signal 201 from the reference signal generator 200 , and Y 1 is stored in the initial value storage circuit 500 (S 2204 ). The steps of the flowchart of FIG. 22 are preferably performed, for example, in a release test for the semiconductor integrated device 1 , as in FIG. 2 .

FIG. 23 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment. The steps of the flowchart of FIG. 23 are preferably performed, for example, upon activation of the semiconductor integrated device 1 , as in FIG. 3 .

The semiconductor integrated device 1 turns off the switching circuit S 1 , turns on the switching circuit S 2 , and turns off the write circuit S 3 (S 2301 ). The semiconductor integrated device 1 activates the reference signal generator 200 and the determination circuit 703 (S 2302 ). When the semiconductor circuit 400 is operated in this condition, the semiconductor circuit 400 outputs an output value Y 2 according to the reference signal 201 from the reference signal generator 200 (S 2303 ). The difference operation circuit 600 calculates a difference between Y 2 and the output 501 representing a value stored in the initial value storage circuit 500 at a time point before shipment, and transmits the output 601 representing a result of the calculation to the determination circuit 703 (S 2304 ). The determination circuit 703 outputs a result of comparison between the outputs 601 and 704 (S 2305 ). The semiconductor integrated device 1 turns off the reference signal generator 200 and the determination circuit 703 (S 2306 ).

When the semiconductor integrated device 1 according to the present eighth embodiment is mounted, for example, to a vehicle-mounted control device, the controller of the vehicle-mounted control device can determine an abnormal condition of the semiconductor integrated device 1 on the basis of the determination result 705 . Thus, error notification of for example turning on of an alarm indicator can be made.

FIG. 24 is a flowchart illustrating operation of the semiconductor integrated device 1 after shipment. The flowchart of FIG. 24 illustrates the steps of correcting a characteristic variation of the semiconductor circuit 400 over time during normal operation of the semiconductor integrated device 1 .

The semiconductor integrated device 1 turns on the switching circuit S 1 , turns off the switching circuit S 2 , and turns off the write circuit S 3 (S 2401 ). The semiconductor integrated device 1 turns off the reference signal generator 200 and the determination circuit 703 (S 2402 ). The semiconductor integrated device 1 operates the input circuit 100 and the semiconductor circuit 400 (S 2403 ). The operations of the initial value storage circuit 500 , the difference operation circuit 600 , the determination circuit 703 , and the threshold generation circuit 702 are stopped, and thereby the age deterioration of these circuits can be also prevented, as in the first embodiment.

Eighth Embodiment: Effects

As described above, the semiconductor integrated device 1 according to the present eighth embodiment can detect the age deterioration of the semiconductor circuit 400 by using the determination circuit 703 . Furthermore, on the basis of a detection result, the following measures can be taken (a) reporting an abnormal condition of the semiconductor circuit 400 to a vehicle driver, (b) recording an abnormal log, or (c) performing fail-safe processing (e.g., suspending control of a vehicle-mounted device or a vehicle).

Modifications of the Present Invention

The present invention is not limited to the examples described above, and can include various modifications. For example, the above examples are described in detail for convenience to understand the present invention, and therefore, the present invention is not necessarily limited to a configuration including all of the configurations described above. Furthermore, part of a configuration according to an example can be replaced with a configuration according to another example, and a configuration according to an example can be also applied to a configuration according to another example. In addition, for part of a configuration according to each example, addition, elimination, or substitution of another configuration may be made.

In the above embodiments, control lines or information lines considered to be necessary for description are described, and all control lines or information lines required for a product are not always illustrated. Any of analog signal and digital signal can be input to or output from each component circuit, with similar effects. The component elements of the semiconductor integrated device 1 may be formed on the same semiconductor chip to be configured as an integrated circuit, or may be separated to be mounted as a plurality of components.

In the above embodiments, the operation of the semiconductor integrated device 1 may be controlled in accordance with a command from a calculation control device such as the controller 900 or the semiconductor integrated device 1 may include a control device for controlling the operation of the semiconductor integrated device 1 .

1 semiconductor integrated device

100 input circuit

200 reference signal generator

300 input switching circuit

400 semiconductor circuit

500 initial value storage circuit

503 temperature monitor circuit

505 selector circuit

600 difference operation circuit

700 correction-value storage circuit

702 threshold generation circuit

703 determination circuit

800 correction circuit

900 controller