Signal transmission circuit provided with logic circuit

This application is based on and claims the benefit of priority from earlier Japanese Patent Application No. 2016-88515 filed Apr. 26, 2016, the description of which is incorporated herein by reference.

The present disclosure relates to signal transmission circuits adapted for a power system having a plurality of mutually isolated drive circuits each driving a semiconductor switching element.

Generally, an inverter that drives an on-vehicle motor is configured of a high voltage system, and a control unit that controls the inverter is configured of low voltage system which is isolated from the high voltage system. In the case where signals are transmitted from the inverter to the control unit, the signals are transmitted from the high voltage system to the low voltage system, the signals including temperature information and abnormality information notifying occurrence of abnormalities in the switching elements of the inverter. Since isolation is required between the high voltage system and the low voltage system, an isolation element is used for transmitting the signals from the inverter to the control unit.

As an example of a related art, for example, JP-A-2009-136115 discloses a technique of using a photo coupler as an isolation element, in which the secondary side circuit of the photo coupler is series-connected, whereby the transmission path from the isolation element to the control unit (receiving unit) are shared by the secondary side circuit. In other words, a single photo coupler is used for circuitry of the control unit. When an abnormality occurs on at least one of the switching elements, a signal indicating an abnormality is transmitted to the control unit. The transmission path is commonly used by the secondary side circuit, whereby the wiring between the control unit and the isolation element can be simplified.

In recent years, magnetic couplers have been used as isolation elements instead of photo couplers. The magnetic coupler outputs, in response to the input signal, a signal relative to a predetermined reference voltage (ground voltage). Hence, the magnetic coupler cannot be used like photo couplers, where the secondary side circuits are serially-connected.

The present disclosure provides a signal transmission circuit having a plurality of isolation elements outputting a signal relative to a predetermined reference voltage, in which a signal transmission path between the isolation elements and the receiving unit is designed to be common.

The configuration according to the present disclosure provides a signal transmission circuit transmitting abnormality signals from a primary side circuit to a secondary side circuit.

The signal transmission circuit includes: a plurality of isolation elements that electrically isolate the primary side circuit and the secondary side circuit, and allows the abnormality signals to be transmitted therethrough; and a logic circuit that receives the abnormality signals from the isolation elements, the logic circuit being disposed in the secondary circuit, outputting a predetermined signal indicating an occurrence of an abnormality when at least one of the switching elements shows the abnormality.

The primary side circuit including a plurality of switching elements and a plurality of drive circuits that drive the switching elements, the drive circuits each being isolated from each other, the secondary circuit including a receiving unit that receives the abnormality signals corresponding to respective switching elements, transmitted from the primary side circuit.

The isolation elements transmit the abnormality signals relative to a predetermined reference voltage in the secondary side circuit and the predetermined signal outputted by the logic circuit is received by the receiving unit.

According to the configuration, a signal transmission path between a plurality of isolation elements and the receiving unit, through which an abnormality signal is transmitted, can be greatly simplified.

In the accompanying drawings:

FIG. 1 is an electrical configuration of an inverter;

FIG. 2 is an overall diagram showing a circuit substrate on which the inverter is mounted;

FIG. 3 is an overall configuration of a power card (semiconductor switching element);

FIG. 4 is a diagram showing an electrical configuration of a magnetic coupler;

FIG. 5 is a diagram showing a connection between a magnetic coupler and a logic circuit according to a first embodiment;

FIG. 6 is a diagram showing a connection between a magnetic coupler and a logic circuit according to a second embodiment;

FIG. 7 is a diagram showing a connection between a magnetic coupler and a logic circuit according to a third embodiment;

FIG. 8 is a diagram showing a connection between a magnetic coupler and a logic circuit according to a fourth embodiment;

FIG. 9 is a diagram showing an electrical configuration of a module according to the fourth embodiment; and

FIG. 10 is a diagram showing a connection between a magnetic coupler and a logic circuit; and

FIG. 11 is a diagram showing wirings connected between magnetic couplers and a control unit.

First Embodiment

Hereinafter, with reference to the drawings, an embodiment of a signal transmission circuit applied to a power system will be described. The signal transmission circuit is used for a hybrid vehicle in the embodiment.

FIG. 1 is an electrical configuration of a power conversion apparatus according to the first embodiment. A motor generator 10 is mechanically coupled to a drive wheel or an internal combustion engine. The motor generator 10 is connected to an inverter INV. The inverter INV (power conversion circuit) accepts output voltage of a DC (direct current) power source 12 as input voltage, and converts the DC power to AC (alternating current) power. The DC power source 12 is a high voltage battery in which the terminal voltage exceeds 100 Volts. The DC power source may be configured as a step up/down converter.

The inverter INV configured of high voltage side switching elements SWp 1 to SWp 3 (upper arm switching elements), and low voltage side switching elements SWn 1 to SWn 3 (lower arm switching element). Each of the high voltage side elements and each of the low voltage side elements are paired to form a series-connected element, and three series-connected elements are connected in parallel to compose the inverter INV. Connection points between each of the switching elements SWp 1 to SWp 3 and each of the switching elements SWn 1 to SWn 3 are connected to each phase of the motor generator 10

Each of the high voltage side switching elements SWp 1 to SWp 3 has a free wheel diode FDpn (n=1, 2, 3) connected between the input terminal and the output terminal (between collector and emitter) of respective switching elements SWp 1 to SWp 3 , such that the cathode and the anode are connected to the collector and the emitter of the switching element respectively.

Similarly, each of the low voltage side switching elements SWn 1 to SWn 3 has a free wheel diode FDnn (n=1, 2, 3) connected between the input terminal and the output terminal (between collector and emitter) of respective switching elements SWn 1 to SWn 3 , such that the cathode and the anode are connected to the collector and the emitter of the switching element respectively.

The capacitor CA is connected to the collector terminals of the upper arm switches SWp 1 to SWp 3 (high voltage side terminals) and the emitter terminals of the lower switches SWn 1 to SWn 3 (low voltage side terminals), serving as a smoothing capacitor that smoothes voltage between both terminals.

The semiconductor switching elements SW (SWp 1 to SWp 3 , SWn 1 to SWn 3 ) which configure the above-mentioned inverter INV are power semiconductors. More specifically, the semiconductor switching elements are isolation bipolar transistor (IGBT).

The control unit 4 is configured of a microprocessor, serving as a digital processing means that controls a control amount of the motor generator 10 by operating the inverter INV. Specifically, the control unit 40 outputs operating signals to the switching elements SW of the inverter INV via an interface 42 as an isolation means including magnetic couplers Mp 1 to Mp 3 , and Mn 1 to Mn 3 , thereby operating the inverter INV.

More specifically, the control unit 40 outputs a drive command signal to the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 which output a drive command signal to the control terminal (gate) of each switching element via the interface 42 . The drive command signal is a PWM (pulse width modulation) signal which is set based on the target value of the output voltage of the inverter INV and the detection value of the inverter INV. The isolation means is provided in the interface 42 to isolate between the high voltage system provided with the inverter INV and the DC power source 12 , and the low voltage system provided with the control unit 40 . It should be noted that the high voltage system includes a primary side circuit and low voltage system includes a secondary side circuit (described later).

The emitters of the switching elements SWp 1 to SWp 3 are isolated. Similarly, the emitters of the switching elements SWn 1 to SWn 3 are isolated. These emitters are connected to different reference voltages. The drive circuits DP 1 to Dp 3 and the Dn 1 to Dn 3 are connected to emitters of the switching elements SWp 1 to SWp 3 and SWn 1 to SWn 3 to be driven. The drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 apply voltage to the gates of the switching elements SWp 1 to SWp 3 and SWn 1 to SWn 3 , using emitter voltages of the switching elements SWp 1 to SWp 3 and SWn 1 to SWn 3 as the reference voltage.

FIG. 2 shows a circuit substrate 50 on which the inverter INV according to the inverter INV is mounted. The circuit substrate 50 shown in FIG. 2 includes a high voltage circuit area HV connected to the inverter INV and the low voltage circuit area LV. An area on the right side in FIG. 2 (an opposite direction along which the upper arm switch SWp 2 is provided against the upper arm switch SWp 3 ) is defined as low voltage circuit region LV, an area of the center and the left side (an opposite direction along which the upper arm switch SWp 2 is provided against the upper arm switch SWp 3 ) is defined as high voltage circuit area HV. It should be noted that components belonging to both the low voltage system and the high voltage system such as magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 are present in the high voltage circuit area HV.

The control unit 40 is disposed in the low voltage circuit area LV in the right side of FIG. 2 . An electrolytic capacitor (nor shown) of a fly-back converter that configures the power circuit of the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 of the switching elements SW in the inverter INV is disposed in the low voltage circuit area LV as a low voltage system component. Also, a primary winding side circuit of a transformer (not shown) of the fly-back converter that configures the power circuit of the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 is disposed in the low voltage circuit area LV as a low voltage system circuit, and the secondary winding side circuit is disposed in the high voltage area HV as a high voltage system circuit.

As shown in FIG. 3 , each switching element SW in the above-described inverter INV is inserted into the circuit substrate 50 from the backside thereof (backside shown in FIG. 2 ) to make an electrical connection between the switching element SW and the circuit board 50 . Each switching element SW is coated by an isolation material and configures a power card PWC (module) together with other components. The power card PWC accommodates a free wheel diode FD and a temperature sensitive diode SD. However, in FIG. 3 , illustration of the free wheel diode FD is omitted.

The power card PWC has the same structure for one accommodating the high voltage side switching elements SWp and one accommodating the low voltage side switching elements SWn. The power card PWC has a plurality of signal terminals exposed outside from the isolation material. Specifically, these signal terminals including a gate terminal G, an emitter detection terminal KE, a sense terminal SE of the switching element, and anode A/cathode K terminals of the temperature sensing diode SD are inserted into the circuit substrate 50 . The emitter detection terminal KE is connected to the emitter E of the switching element SW, the emitter detection terminal KE having the same voltage as the emitter E. The collector detection terminal KC is connected to the collector of the switching element SW, the collector detection terminal KC having the same voltage as the collector. The sense terminal SE serves as a terminal outputting small current correlated to the current flowing through the switching element SW.

As shown in FIG. 2 , since the switching elements SW configure high voltage system, an isolation area IA is provided in the circuit board 50 to isolate these switching elements and other circuit components. The isolation area IA has no circuit components (elements, wiring and power supply pattern).

In upper side in FIG. 2 , terminals of the power cards PWC provided with the upper arm switches SWp 1 to Swp 3 are shown, which are mutually isolated by an isolation area IA. Each of the drive circuits Dp 1 to Dp 3 which drive the upper arm switches SWp 1 to SWp 3 is mounted in an area surrounded by the isolation area IA. The reason why these drive circuits Dp 1 to Dp 3 are isolated is that voltages at KE terminals of the upper arm switches SWp 1 to SWp 3 significantly vary depending on a state of whether ON or OFF in the respective lower arm switches SWn 1 to SWn 3 . Accordingly, although the operating voltages of the drive circuits Dp 1 to Dp 3 are small, the drive circuits Dp 1 to Dp 3 have to be isolated from each other. The width of the above-described isolation area IA is determined considering legal requirement or a view point of preventing isolation breakdown.

The terminals of the power card PWC including the lower arm switches SWn 1 to SWn 3 are shown in lower side of FIG. 2 . Since the voltages of the emitter detection terminals KE corresponding to the lower arm switches SWn 1 to SWn 3 are close to each other, the isolation area IA is not disposed therebetween. The operating voltage of components related to the drive circuits Dn 1 to Dn 3 is not so high compared to components disposed in the low voltage circuit area LV. Hence, the isolation area IA is not necessarily provided to the drive circuits Dn 1 to Dn 3 of the lower arm switches SWn 1 to SWn 3 on the circuit board 50 .

However, reference voltages (emitter voltage of corresponding switches SWn 1 to SWn 3 ) of the drive circuits Dn 1 to Dn 3 are mutually different during the operation of the inverter INV, based on resistance component and inductive component between the emitter terminals of the switches SWn 1 to SWn 3 . Therefore, although the isolation area IA is not provided among the drive circuits Dn 1 to DN 3 , the drive circuits Dn 1 to Dn 3 are isolated from each other.

Each of the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 (hereinafter also referred to as drive circuit D) is connected to the gate terminal G and the emitter detection terminal KE of the respective switching elements SW, and applies voltage to the gate terminal G of the respective switching elements, thereby driving the switching element SW.

Further, the drive circuit D according to the present embodiment is connected to the sense terminal SE of corresponding switching element SW and the anode A and the cathode K of the temperature sensing diode SD. The drive circuit D detects, based on the voltage of the sense terminal SE, current flowing through the switching element SW. The drive circuit D detects, based on the voltage between the anode A and the cathode K, the temperature of the switching element SW. Moreover, the drive circuit D determines, based on the detection value of the temperature of the switching element SW, whether or not an abnormality occurs on the switching element SW. The drive circuit D also determines where or not an abnormality occurs on the drive circuit D itself. Then, the drive circuit D transmits an abnormality signal to the control unit 40 , the abnormality signal including abnormality information (i.e., abnormality corresponding to the switching element SW) of the switching element SW and the drive circuit D. It should be noted that a switching element or other ICs can be used to determine abnormality as a main abnormality determination device.

Here, as described above, the drive circuit D and the control unit 40 are connected via the interface 42 . Specifically, the drive circuit D and the control unit 40 are connected via the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 (hereinafter also referred to as magnetic coupler M) which configure the interface 42 . The above-described switching elements SWp/n and the drive circuits D belong to the primary side circuit, and the control unit 40 and related logic circuits belongs to the secondary side circuit.

As shown in FIG. 4 , the magnetic coupler M is provided with an input circuit 22 in the drive circuit D side, an output circuit 21 in the control unit 40 side, and a transformer 23 as an isolation element between the input circuit 22 and the output circuit 21 . The input circuit 22 receives an input signal to the magnetic coupler M transmitted from the drive circuit D. The input circuit 22 transmits a pulse signal to the output circuit 21 in accordance with the input signal via the transformer 23 . The output circuit 21 transmits, in accordance with the pulse signal transmitted from the input circuit 22 , an output signal to the control unit 40 from the magnetic coupler M. The signal transmitted to the input circuit 22 from the drive circuit D is an abnormality signal detected by the drive circuit D.

Further, the magnetic coupler M is provided with an input circuit 24 in the control unit 40 side, an output circuit 25 in the drive circuit D side, and a transformer 26 as an isolation element between the input circuit 24 and the output circuit 25 . The input circuit 24 receives an input signal transmitted to the magnetic coupler M from the control unit 40 . The input circuit 24 transmits a pulse signal to the output circuit 25 via the transformer 26 in accordance with the input signal. The output circuit 25 transmits an output signal to the drive circuit D from the magnetic coupler M in accordance with the output signal. The signal transmitted from the control unit 40 to the input circuit 24 serves as a drive command signal to the drive circuit D.

The output circuit 21 of the magnetic coupler M drives switches S 1 and S 2 , thereby outputting the signal. The switches S 1 and S 2 are configured of MOSFETs such that either one switch S 1 or switch S 2 turns ON when the magnetic coupler is in operation state. When the switch S 1 turns ON, the output terminal and the power are conducted so that Hi state signal is outputted from the output terminal. Similarly, when the switch S 2 turns ON, the output terminal and the ground are conducted so that Low state signal is outputted from the output terminal. In other words, the magnetic coupler M transmits an output signal depending on the input signal using a binary signal which takes either High or Low with respect to a predetermined reference voltage (ground voltage). Similar to the output circuit 21 , the output circuit 25 of the magnetic coupler M drives the switches S 3 and S 4 , thereby outputting a signal.

As shown in FIG. 5 , according to the present embodiment, to simplify the circuit configuration, a logic circuit 30 is provided between the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 , and the control unit 40 . Here, simplifying circuit configuration includes reducing the number of terminals used for receiving abnormality information, simplifying wirings between the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 , and the control unit 4 . When the logic circuit 30 receives an abnormality signal from at least one of the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 via the magnetic couplers Mp 1 to Mp 3 , and the Mn 1 to Mn 3 , the logic circuit 30 outputs a predetermined signal indicating an occurrence of an abnormality in the whole system to the control unit 40 .

Each of the magnetic couplers Mp 1 to MP 3 and Mn 1 to Mn 3 according to the present embodiment outputs High state signal at the secondary side (control unit 40 side) when an abnormality signal indicating an occurrence of an abnormality is received from corresponding primary side drive circuit Dp 1 to Dp 3 and Dn 1 to Dn 3 (primary side circuit). The logic circuit 30 is configured of OR circuits. Hence, when an abnormality signal is received from at least one of the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 , the logic circuit 30 outputs, by using the OR circuit, a High state signal to the control unit 40 .

In other words, the logic circuit 30 performs logical OR of all magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 , and outputs the result to the control unit 40 . Accordingly, a predetermined signal indicating an occurrence of abnormality as a whole system is outputted to the control unit 40 . According to the configuration, a transmission path can be commonly used for a plurality of magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 to transmit an abnormality signal to the control unit 40 .

The logic circuit 30 connects adjacent magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 to be in serial (serial connection). As shown in FIG. 2 , the magnetic coupler Mn 3 and the magnetic coupler Mn 2 are adjacently located, the magnetic coupler Mn 2 and the magnetic coupler Mn 1 are adjacently located, and the magnetic coupler Mn 1 and the magnetic coupler Mp 1 are adjacently located, and the magnetic coupler Mp 2 and the magnetic coupler Mp 3 are adjacently located.

The logic circuit 30 is provided with an OR circuit On 2 to which the output of the magnetic coupler Mn 3 and the output of the magnetic coupler Mn 2 are connected to the inputs of the OR circuit Ont. Also, the logic circuit 30 is provided with an OR circuit On 1 to which the output of the OR circuit On 2 and the output of the magnetic coupler Mn 1 are connected to the inputs of the OR circuit On 1 . Moreover, the logic circuit 30 is provided with an OR circuit Op 1 to which the output of the OR circuit On 1 and the output of the magnetic coupler Mp 1 are connected to the inputs of the OR circuit Op 1 . Further, the logic circuit 30 is provided with an OR circuit Opt to which the output of the OR circuit Op 1 and the output of the magnetic coupler Mp 2 are connected to the inputs of the OR circuit Opt. Furthermore, the logic circuit 30 is provided with an OR circuit Op 3 to which the output of the OR circuit Opt and the output of the magnetic coupler Mp 3 are connected to the inputs of the OR circuit Op 3 .

The OR circuits Op 1 to Op 3 and On 1 correspond to “first logic circuit” to which corresponding one output among the magnetic couplers Mp 1 to Mp 3 and Mn 1 is connected and correspond one output of adjacent OR circuit Op 1 , Op 2 , On 1 and On 2 is connected. The OR circuit Op 3 corresponds to “second logic circuit” in which the output is connected to the control unit 40 . The output signal of the OR circuit Op 3 is outputted to the control unit 40 as an output signal of the logic circuit 30 . The OR circuit On 2 corresponds to third logic circuit to which two outputs of corresponding magnetic couplers Mn 2 and Mn 3 are connected.

According to the configuration, as described above, the OR circuits OP 1 to Op 3 , On 1 and On 2 are provided such that adjacent magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 are serially connected. Thus, wirings among the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 , the logic circuit 30 and the control unit 40 can be simplified.

As shown in FIG. 2 , the magnetic coupler Mp 3 is located to have the shortest distance to the control unit 40 , in which the magnetic coupler Mp 3 corresponds to the OR circuit Op 3 as the “second logic circuit” connected to the control unit 40 at the output of the second logic circuit, among the OR circuit Op 1 to Op 3 and On 1 and On 2 . Therefore, the length of the wiring L between the magnetic couplers Mp 1 to Mp 3 , Mn 1 and Mn 3 , the logic circuit 30 , and the control unit 40 can be shorter. Thus, the control unit 40 can detect abnormality faster in the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 .

Further, the magnetic couplers Mp 1 to MP 3 and Mn 1 to Mn 3 continues to output a Low signal, when an abnormality signal indicating an occurrence of abnormality from the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 , that is, none of drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 detects abnormality. The OR circuits Op 1 to Op 3 and On 1 to On 2 are pulled up via resistors at the input circuits thereof. Hence, when no abnormality is detected in the whole system, Low signals are inputted to the OR circuits Op 1 to Op 3 and On 1 and On 2 , and the logic circuit 30 (OR circuit Op 3 ) outputs a Low signal indicating that the whole system is in a normal state.

According to this configuration, in the case where an open failure occurs in the connection between the magnetic couplers Mp 1 to Mp 3 , Mn 1 and Mn 2 , and the OR circuits Op 1 to Op 3 , On 1 and On 2 , any one of inputs of the OR circuits Op 1 to Op 3 , On 1 and On 2 becomes High. Hence, the logic circuit 30 outputs a High signal indicating an occurrence of abnormality in the whole system. Also, when an open failure occurs due to wire-breakage or the like in the connection among the OR circuits Op 1 to Op 3 , On 1 and On 2 , any one of inputs of the OR circuits Op 1 to Op 3 , and On 1 becomes High. Thus, the logic circuit 30 outputs High signal indicating an occurrence of abnormality as the whole system.

Thus, according to the present embodiment, an open failure in a connection between the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 , and the OR circuits Op 1 to Op 3 and On 1 and On 2 , and an open failure in a connection between the OR circuits Op 1 to Op 3 and On 1 and ON 2 can be detected as an abnormality of the whole system.

In the case where an abnormality of the magnetic coupler Mp 1 to Mp 3 , and Mn 1 to Mn 3 causes operation of the magnetic couplers Mp 1 to Mp 3 , and Mn 1 to Mn 3 , to stop, any one of inputs of the OR circuits Op 1 to Op 3 and On 1 and On 2 becomes High. Hence, the logic circuit 30 outputs High signal indicating an occurrence of an abnormality as the whole system. In other words, according to the configuration, abnormality in the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 can be detected as an abnormality as the whole system.

According to the present embodiment, “isolation element” is a magnetically-coupled type isolation element, specifically a magnetic coupler. According to the present embodiment, even in a magnetic coupler that outputs a binary signal either High or Low with respect to a predetermined reference voltage, a transmission path to the control unit 40 as a “receiving unit” can be commonly used (shared transmission path).

Second Embodiment

The magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 according to the second embodiment outputs Low signal outputs Low signal, when an abnormality signal is transmitted from the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 . Further, the logic circuit 30 A of the second embodiment outputs Low signal to the control unit 40 by using an AND circuit, when an abnormality signal is transmitted from at least one of the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 .

A configuration of the second embodiment is shown in FIG. 6 . The logic circuit 30 A receives output signals Mn 3 and Mn 2 at the inputs of the AND circuits An 2 . Also, the output of the AND circuit An 2 and the output of the magnetic coupler Mn 1 are connected to the AND circuit An 1 . The output of the AND circuit An 1 and the output of the magnetic coupler Mp 1 are connected to the AND circuit Ap 1 . The output of the AND circuit Ap 1 and the output of the magnetic couplet Mpg are connected to the AND circuit Ap 2 . The output of the AND circuit Ap 2 and the output of the magnetic coupler Mp 3 are connected to the AND circuit Ap 3 . The output signal of the AND circuit Ap 3 as the output signal of the logic circuit 30 A is connected to the control unit 40 .

In the configuration shown in FIG. 6 in which the logic circuit 30 A includes AND circuits Ap 1 to Ap 3 , An 1 and An 2 , the inputs of the AND circuits Ap 1 to Ap 3 , An 1 and An 2 are pulled down. The magnetic couplers Mp 1 to Mp 3 , Mn 1 to Mn 3 continue to output a High level signal when none of the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 detects any abnormalities.

According to the above-described configuration, when an open failure occurs in the connection between the magnetic couplers MP 1 to Mp 3 , Mn 1 to Mn 3 , and the AND circuits Ap 1 to Ap 3 , An 1 , An 2 , a Low level signal representing an occurrence of abnormality as the whole system is outputted to the control unit 40 . Similarly, when an open failure occurs in the connection among the AND circuits Ap 1 to Ap 3 , An 1 and An 2 , a Low level signal representing an occurrence of abnormality as the whole system is outputted to the control unit 40 . When an operation of the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 is stopped, a Low level signal representing an occurrence of abnormality as the whole system is outputted to the control unit 40 .

According to the above-described configuration, an open failure of a connection between the magnetic couplers Mp 1 to Mp 3 , Mn 1 to Mn 3 and the AND circuits Ap 1 to Ap 3 , An 1 and An 2 , and an open failure among the AND circuits Ap 1 to Ap 3 , An 1 and An 2 can be detected as an abnormality in the whole system.

Third Embodiment

A configuration of the third embodiment is shown in FIG. 7 . Comparing with the first embodiment shown in FIG. 5 , the logic circuit 30 B of the present embodiment includes an OR circuit On 3 as “fourth logic circuit”. The OR circuit On 3 accepts the output of the magnetic coupler Mn 3 and the ground voltage at the input thereof. The output of OR circuit On 3 is connected to the input of the OR circuit Ont. Thus, the OR circuit On 3 passes the output of the magnetic coupler Mn 3 to the OR circuit On 2 without any changes.

According to the third embodiment, the OR circuits Op 1 to Op 3 and On 1 to On 3 are provided corresponding to the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 respectively. In this respect, the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 , and corresponding OR circuits Op 1 to Op 3 and On 1 to On 3 are provided in a single module. The module is sealed by resin or the like. The module includes one magnetic coupler and a plurality of elements including the OR circuits corresponding to the magnetic coupler M, and wirings that connects these elements.

According to the third embodiment, the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 , and corresponding OR circuits Op 1 to Op 3 and On 1 to On 4 are sealed to form modules Pp 1 to Pp 3 , and Pn 1 to Pn 3 having the same configuration. In other words, since the configuration is common in the modules Pp 1 to Pp 3 , and Pn 1 to Pn 3 , the same device can be used for the modules Pp 1 to Pp 3 and Pn 1 to Pn 3 so that manufacturing cost can be reduced.

Similar to the third embodiment, in the configuration of the second embodiment, the AND circuit An 3 may be provided corresponding to the magnetic coupler Mn 3 , and the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 and corresponding AND circuits Ap 1 to Ap 3 and An 1 to An 3 may compose a module. In the inputs of the AND circuit An 3 , a terminal to which the magnetic couple Mn 3 is not connected may be pulled up. According to the present configuration, similar effects to the third embodiment can be obtained.

Fourth Embodiment

The configuration of the fourth embodiment is shown in FIG. 8 . Similar to the configuration of the second embodiment shown in FIG. 6 , the logic circuit 30 C according to the fourth embodiment includes a AND circuit. Further, an AND circuit An 3 as the “fourth logic element” is provided.

Similar to the third embodiment, the magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 and corresponding AND circuits Ap 1 to Ap 3 and An 1 to An 3 are formed in the modules. According to the configuration of the present embodiment, pull-down resistors which pull-down the inputs of the AND circuits Ap 1 to Ap 3 and An 1 to An 3 are integrated into the modules Pp 1 to Pp 3 and Pn 1 to Pn 3 .

According to the present embodiment, the AND circuit An 3 accepts, at the inputs thereof, the output of the magnetic coupler Mn 3 and the output of the AND circuit Ap 3 (logical circuit 30 C). Specifically, the input terminal of the AND circuit An 3 is pulled up with a resistor Ra outside the module Pn 3 and connected to the output of the AND circuit Ap 3 . The resistance of the pull-up resistor Ra that pulls-up the input of the module Pn 3 outside the module Pn 3 is set to be smaller than the resistance of the pull-down resistor integrated in the module Pn. Thus, the configuration of the module Pn 3 is commonly used for the modules Pp 1 to Pp 3 and Pn 1 and Pn 2 , and inputs of the module Pn 3 (AND circuit An 3 ) are pulled up.

When an abnormality as the whole system occurs, the output of the logic circuit 30 C turns to Low, and the AND circuit An 3 receives the Low signal at the input thereof. When the output of the logic circuit 30 C is not Low (high or floating), High signal is outputted to the OR circuit On 3 . According to this configuration, when an abnormality occurs as the whole system, the outputs of all AND circuits Ap 1 to Ap 3 and An 1 to An 3 become Low.

Also, as shown in FIG. 9 , the magnetic coupler M (magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 ) according to the present embodiment transmits an abnormality signal indicating an abnormality detected by the drive circuit D to the control unit 40 from the drive circuit D, and transmits a drive command signal commanding the drive circuit D to drive the switch SW from the control unit 40 .

As shown in FIG. 9 , the input circuit 24 of the magnetic coupler M according to the present embodiment receives an output of the AND circuit AN. As described above, when an abnormality as the whole system occurs, the outputs of all AND circuits become Low. When receiving Low signal from the AND circuit AN, the input circuit 24 stops outputting the pulse signal to the transformer 26 regardless of the drive command signal transmitted from the control unit 40 . The configuration of the input circuit 24 , in which the output signal of the AND circuit AN and the drive command signal are received, may be changed to a configuration in which the output signal of the AND circuit AN and the drive command signal are outputted to an AND circuit, and the output of the AND circuit is outputted to the input circuit 24 .

According to the present embodiment, when an abnormality occurs on any one of the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 , the output signals of all of the AND circuits show an occurrence of an abnormality. The magnetic couplers Mp 1 to Mp 3 and Mn 1 to Mn 3 stop transmitting, in response to the AND circuits Ap 1 to Ap 3 and An 1 to An 3 , the drive command signal to corresponding drive circuit in Dp 1 to Dp 3 and Dn 1 . to Dn 3 . According to the configuration, without using the control unit 40 , the output of the inverter INV can be stopped, when an abnormality occurs in at least one of drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 .

According to the present embodiment, similar to the second embodiment, the magnetic couplers Mp 1 to Mp and Mn 1 to Mn 3 , and the AND circuits Ap 1 to Ap 3 and An 1 to An 3 are sealed to form modules Pp 1 to Pp 3 , and Pn 1 to Pn 3 . In other words, configuration of the modules Pp 1 to Pp 3 and Pn 1 to Pn 3 are commonly used so that the same device can be used for the modules Pp 1 to Pp 3 and Pn 1 to Pn 3 . As a result, manufacturing cost can be reduced.

Similar to the forth embodiment, the configuration of the third embodiment may be changed such that the output signal of the logic circuit 30 is connected to the input of the OR circuit On 3 . In this case, the output of the magnetic coupler Mn 3 and the output of the logic circuit 30 B (OR circuit Op 3 ) are connected to the OR circuit On 3 . Specifically, when the output signal of the logic circuit 30 B is High, a High state signal is outputted to the OR circuit On 3 , and a Low state signal is outputted to the OR circuit On 3 when the logic circuit 30 B is a state other than High (i.e., Low state or floating state).

Fifth Embodiment

A configuration of the fifth embodiment is shown in FIG. 10 . According to the present embodiment, the magnetic couplers Mp 1 to Mp 3 are connected in series by the first logic circuit 30 D configured of the OR circuit Op 1 and Op 2 , and the magnetic couplers Mn 1 to Mn 3 are connected in series by the second logic circuit 30 E configured of the OR circuit On 1 and On 2 . Each of the outputs of the logic circuits 30 D and 30 E is connected to the control unit 40 .

In other words, the first logic circuit 30 D accepts abnormality signals from the magnetic couplers Mp 1 to Mp 3 corresponding to the upper arm switches SWp 1 to SWp 3 . Then, when an abnormality is detected on at least one of the drive circuits Dp 1 to Dp 3 corresponding to the upper arm switches SWp 1 to SWp 3 , the first logic circuit 30 D outputs an abnormality signal indicating an occurrence of abnormality as the whole system including the upper arm switches SWp 1 to SWp 3 and the drive circuits Dp 1 to DP 3 to the control unit 40 .

Similarly, the second logic circuit 30 E accepts abnormality signals from the magnetic couplers Mn 1 to Mp 3 corresponding to the lower arm switches SWn 1 to SWn 3 . Then, when an abnormality is detected on at least one of the drive circuits Dn 1 to Dn 3 corresponding to the lower arm switches SWn 1 to SWn 3 , the second logic circuit 30 E outputs an abnormality signal indicating an occurrence of abnormality as the whole system including the lower arm switches SWn 1 to SWn 3 and the drive circuits Dn 1 to Dn 3 to the control unit 40 .

FIG. 11 shows a wiring Ln which connects the magnetic couplers Mn 1 to Mn 3 , and a wiring Lp which connects the magnetic couplers Mp 1 to Mp 3 , according to the present embodiment.

According to the present embodiment, the control unit 40 acquires each of the abnormality signals separately from the drive circuits Dp 1 to DP 3 of the upper arm switches SWp 1 to SWp 3 and the drive circuits Dn 1 to DN 3 of the lower arm switches SWn 1 to SWn 3 , whereby the control unit 40 can acquire an occurrence of abnormality faster in the drive circuits Dp 1 to Dp 3 , and Dn 1 to Dn 3 . Also, when the drive circuits Dp 1 to DP 3 corresponding to the upper arm switches SWp 1 to SWp 3 detect an abnormality, for example, by controlling the lower arm switches SWn 1 to SWn 3 , power stored in the inverter INV can be discharged. When the drive circuits Dn 1 to Dn 3 corresponding to the lower arm switches SWn 1 to SWn 3 detect an abnormality, by controlling the upper arm switches SWp 1 to SWp 3 , power stored in the inverter INV can be discharged.

Other Embodiment

The pull-up resistors of the input terminals of the OR circuits Op 1 to Op 3 , On 1 and On 2 may be omitted. In a configuration in which the input side pull-up resistors are omitted, when the drive circuits Dp 1 to Dp 3 and Dn 1 to Dn 3 do not detect any abnormalities, Low level signal may not be outputted continuously.

In the configuration according to the first embodiment, instead of the OR circuits Op 1 to Op 3 and On 1 to On 3 , NOR circuit may be used. In this case, each output of the respective NOR circuits may be inverted and outputted to adjacent NOR circuit. Similarly, in the configuration of the second embodiment, instead of the AND circuit, NAND circuit may be used. In this case, each output of the respective NAND circuits may be inverted and outputted to an adjacent NAND circuit.

According to the above-described embodiments, as a logic element, a 2-inputs/1-output OR circuit or AND circuit is used. However, an n-inputs/1-output OR circuit or AND circuit may be used, where and n is 3 or more and a natural number).

The “power system” may be a circuit other than the inverter, for example, DC-DC converter.

The output circuits 21 and 25 of the magnetic couplers M shown in FIGS. 4 and 9 are configured of push-pull type and output High state (power source voltage) or Low state (ground voltage) voltage. However, this configuration can be changed to an open-drain output.

As an isolation element, a charge-coupled type isolation element may be used.