Testkey structure and method of measuring device defect or connection defect by using the same

1. Field of the Invention

The present invention relates to a testkey structure and a method of using the same to measure device defect or connection defect.

2. Description of the Prior Art

In recent years, as various kinds of consumer electronic products are being constantly modified towards increased miniaturization, the size of semiconductor components are modified to be reduced accordingly, in order to meet high integration, high performance, low power consumption, and the demands of products.

However, with the increasing miniaturization of electronic products, current planar FETs no longer meet the requirements of the products. Thus, non-planar FETs such as Fin-shaped FETs (FinFET) have been developed, which includes a three-dimensional channel structure. The manufacturing processes of FinFET devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the FinFET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased. In current years, the development of the FinFETs is still aiming to devices with smaller scales.

However, many problem would raise because the shrinkage of the FinFETs size. For example, measuring a resistance value of a FinFET would become more difficult because additional components should be added into original circuits, taking extra space and affecting original design of the products. Thus, there is still a need to develop a novel device to overcome abovementioned problem.

The present invention provides a testkey structure and a method of using the same to measure device defect or connection defect.

According to one embodiment of the present invention, a testkey structure is provided. The testkey structure includes a fin structure, a first gate structure, a second gate structure, a first common source region, a first drain region and a second drain region. The fin structure is disposed on a substrate and stretches along a first direction. The first gate structure and the second gate structure are disposed on the fin structure and stretch along a second direction. The first common source region is disposed in the fin structure between the first gate structure and the second gate structure. The first drain region is disposed in the fin structure at a side of the first gate structure opposite to the first common source region, wherein the fin structure, the first gate structure, the first drain region and the first common source region forms a first transistor. The second drain region disposed in the fin structure at a side of the second gate structure opposite to the first common source region, wherein the fin structure, the second gate structure, the second drain region and the first common source region forms a second transistor. The testkey structure is symmetrical along a horizontal line crossing the first common source region.

According to another embodiment of the present invention, a method of measuring device defect or connection defect is provided. First, a testkey structure shown above is provided. A first current is measured by turning on the first transistor, a second current is measured by turning on the second transistor, and a common current is measured by turning on both the first transistor and the second transistor. Whether a device defect or a connection defect occurs is decided according to the first current, the second current or the common current.

Since the testkey structure is simply and is easy to operate, it can be easily designed as an array so as to gain lots of sample results by quickly scanning the array. Thus, the time for obtaining the sample result and evaluating device defect or connection defect can be greatly saved.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 shows a schematic diagram of the testkey structure on a wafer according to one embodiment of the present invention.

FIG. 2 and FIG. 3 show schematic diagrams of the testkey structure according to one embodiment of the present invention.

FIG. 4 shows a schematic diagram of the device defect according to one embodiment of the present invention.

FIG. 5 shows a schematic diagram of the connection defect according to one embodiment of the present invention.

FIG. 6 shows a flow chart of the method for measuring a device defect or a connection defect according to embodiment of the present invention.

FIG. 7 and FIG. 8 show schematic diagrams of the testkey structure according to another embodiment of the present invention.

FIG. 9 and FIG. 10 show schematic diagrams of the testkey structure according to another embodiment of the present invention.

To provide a better understanding of the presented invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.

Please refer to FIG. 1 , which show a schematic diagram of the testkey structure on a wafer according to one embodiment of the present invention. As shown in FIG. 1 , a wafer 401 including a plurality of die regions 404 , a plurality of first scribing line regions 406 stretching along a first direction 400 and a plurality of second scribing line regions 408 stretching along a second direction 402 are provided. In one embodiment, the first direction 400 is perpendicular to the second direction 402 . Preferably, the die regions 404 are arranged in an array manner and the die regions 404 are separated from each other by the first scribe line regions 406 and the second scribe line regions 408 . In the subsequent process, various semiconductor structures (not shown) such as Fin-FETs will be formed in the die regions 404 for executing logic or non-logic process, and thereafter, a dicing process will be carried out along central lines of the first scribe line regions 406 and the second scribe line regions 408 for example, to separate each dicing region 404 into a single die. A testkey structure (not explicitly shown in FIG. 1 ) for monitoring the accuracy of the semiconductor structures in the die region 404 is disposed in a testkey region 410 . In one embodiment, the testkey region 410 is disposed in an intersection region of the first scribe line region 402 and the second scribe line region 404 , as illustrated in FIG. 1 . In another embodiment, the testkey region 410 can be disposed in a middle portion of the first scribe line region 406 or a middle portion of the second scribe region 408 (not shown in FIG. 1 ). In still another embodiment, it is also available that the testkey region 410 is disposed in the die region 404 (not shown in FIG. 1 ).

Please refer to FIG. 2 and FIG. 3 , which show schematic diagrams of the testkey structure according to one embodiment of the present invention, wherein FIG. 2 shows a top view and FIG. 3 shows a cross-sectional view taken along line AA′ in FIG. 2 . As shown in FIG. 2 and FIG. 3 , the testkey structure 330 in the present embodiment includes a substrate 300 , a first fin structure 304 α, a first gate structure 306 A, a second gate structure 306 B, a first common source region 312 α, a first drain region 314 A and a second drain region 314 B. The substrate 300 is provided to serve as a base for forming devices, components, or circuits. The substrate 300 is preferably composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layered materials thereof. The substrate 300 may also be composed of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs. Although the substrate 300 is depicted as a bulk semiconductor substrate, the arrangement of a semiconductor on an insulator substrate, such as silicon-on-insulator (SOI) substrates, are also suitable for the substrate 300 .

The first fin structure 304 α is disposed on the substrate 300 and stretches along the first direction 400 . The first fin structure 304 α is encompassed by an insulation structure such as a shallow trench isolation (STI) 302 . The method for forming the first fin structure 304 α includes, for example, forming a patterned hard mask layer (not shown) on the substrate 300 , performing an etching process to from a plurality of trenches (not shown) in the substrate 300 , filling an insulating material such as SiO 2 into the trenches, and performing a planarization and/or etching process to from said STI 302 . The protruding portion of the substrate 300 above STI 302 therefore becomes the first fin structure 304 α.

Thereafter, the first gate structure 306 A and the second gate structure 306 B are formed on the first fin structure 304 α. The first gate structure 306 A and the second gate structure 306 B stretch along the second direction 402 and straddle over the first fin structure 304 α. In one embodiment, the first gate structure 306 A and the second gate structure 306 B include a capping layer 308 , a conductive layer 310 , a gate dielectric layer 312 and a spacer 314 . The capping layer 308 includes, for example, silicon nitride (SiN), silicon carbide (SiC) or silicon oxynitride (SiON). In one embodiment, the capping layer 308 may be one or multi layers composed of different dielectric materials. For example, the capping layer 310 may comprise a first capping layer (not shown) and a second capping layer (not shown), which is composed of SiO 2 and SiN, respectively. The conductive layer 310 can include metal or poly-silicon. The gate dielectric layer 312 includes SiO 2 or high-k dielectric materials, such as a material having dielectric constant greater than 4. High-k material can be are earth metal oxides or lanthanide oxides, such as hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO), yttrium oxide (Yb 2 O 3 ), yttrium silicon oxide (YbSiO), zirconium aluminate (ZrAlO), hafnium aluminate (HfAlO), aluminum nitride (AlN), titanium oxide (TiO 2 ), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), zirconium silicon oxynitride (ZrSiON), hafnium silicon oxynitride (HfSiON), strontium bismuth tantalite (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT) or barium strontium titanate (Ba x Sr 1-x TiO 3 , BST), but is not limited thereto. The spacer 314 is disposed on at least a sidewall of the capping layer 308 , the conductive layer 310 and the gate dielectric layer 312 . The spacer 314 can be a single layer or a composite layer, which is composed of high temperature oxide (HTO), silicon nitride, silicon oxide or silicon nitride (HCD-SiN) formed by hexachlorodisilane (Si 2 Cl 6 ). In one embodiment, the spacer 314 and/or the capping layer 308 can be omitted.

The first common source region 312 α is disposed in the first fin structure 304 α between the first gate structure 306 A and the second gate structure 308 B. The first common source region 312 α is formed by implanting appropriate type of dopant into the first fin structure 304 α. When forming a P-type transistor, the predetermined conductivity type dopant is P type dopant, such as boron (B) and/or boron fluoride (BF). Conversely, in N-type transistor, the predetermined conductivity type dopant an N-type dopant such as arsenic (As) and/or phosphorus (P) and/or antimony (Sb), but are not limited thereto. In one embodiment, as shown in FIG. 3 , the first common source region 312 α is disposed in an epitaxial structure 313 with appropriate stress. The first drain region 314 A is disposed in the first fin structure 304 α at a side of the first gate structure 306 A opposite to the first common source region 312 α. The second drain region 314 B is disposed in the first fin structure 304 α at a side of the second gate structure 306 B opposite to the first common source region 312 α. The first drain region 314 A and the second drain region 314 B have the same type of dopant as that in the first common source region 312 α. Similarly, the first drain region 314 A and the second drain region 314 B can be disposed in the epitaxial structures 313 if required. A silicide layer 322 such CoSi can be formed on the first common source region 312 α, the first drain region 314 A and the second drain region 314 B.

After forming the first gate structure 306 A and the second gate structure 306 B, a first inter-layered dielectric (ILD) 316 is formed on the substrate 300 . The first ILD 316 may include SiO 2 , silicon dioxide formed by precursor tetraethyl orthosilicate (TEOS), plasma enhanced silicon dioxide formed by precursor etraethyl orthosilicate (PETEOS), and is not limited thereto. Trenches (not shown) in predetermined position are formed by using a patterned mask (not shown), following by filling into conductive materials to from a common slot contact 318 , a first slot contact 320 A and a second slot contact 320 B. The common slot contact 318 electrically connects the first common source region 312 α, for example, by directly contacting it (or the above silicide layer 322 ). The first slot contact 320 A electrically connects the first drain region 314 A, the second slot contact 320 B electrically connects the second drain region 314 B, for example, by directly contacting the first drain region 314 A or the second drain region 314 B (or their above silicide layer 322 ), respectively. In one embodiment, the common slot contact 318 , the first slot contact 320 A and the second slot contact 320 B include titanium (Ti), titanium nitride (TiN) tantalum nitride (TaN) aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), and is not limited thereto.

After forming the common slot contact 318 , the first slot contact 320 A and the second slot contact 320 B, a second ILD layer 324 is formed on the first ILD layer 316 wherein the second ILD layer 324 includes dielectric material having etching selectivity with respect to that of the first ILD layer 316 . Plural holes (not shown) are formed in the second ILD layer 324 and a conductive material is filled into the holes to from a common plug 326 , plural first plugs 328 A and plural second plugs 328 B. The common plug 326 electrically connects the common slot contact 318 , for example, by directly contacting it. The first plugs 328 A electrically connect the first slot contact 320 A, the second plugs 328 B electrically connect the second slot contact 320 B, for example, by directly contacting the first slot contact 320 A or the second slot contact 320 B, respectively. The common plug 326 , the first plugs 328 A and the second plugs 328 B can include conductive materials the same or different from those of the common slot contact 318 , the first slot contact 320 A and the second slot contact 320 B.

It is one salient feature in the present invention that the testkey structure 330 is mirror symmetrical along a horizontal line B and a vertical line C, which go across the first fin structure 304 α, the first common source region 312 α, the common slot contact 318 and the common plug 326 . The symmetricity, for example, exhibits that the length and the width of the first contact plug 320 A are equal to the length and the width of the second contact plug 320 B, making a project of the first contact plug 320 A along the first direction 400 completely coincides with a projection of the second contact plug 320 B along the first direction 400 , and the so does along the second direction 404 . Similar symmetrical employment can also be found in the first plugs 328 A and the second plugs 328 B. In addition, the number N of the first plugs 328 A is the same as the number of the second plugs 328 B (N=3), while the number N of the first plugs 328 A is greater than the number M of the common plug 326 (M=1).

By showing the above components, a first transistor 332 A and a second transistor 332 B can be formed. The first transistor 332 A is composed of the first fin structure 304 α, the first gate structure 306 A, the first drain region 314 and the first common source region 312 α, and the second transistor 332 B is composed of the first fin structure 304 α, the second gate structure 306 B, the second drain region 314 B and the first common source region 312 α, wherein the first transistor 332 A and the second transistor 332 B have the first common source region 312 α as their common source.

The testkey structure 330 of the present invention can be fabricated simultaneously when forming logical FinFETs in the die region 404 or in a logic region (not explicitly shown) in the die region 404 . Thus, the testkey structure 330 can be used to monitor the defects of the fabrication when forming the FinFETs. In one embodiment, the defects can be categorized into device defects and connection defects. The device defects, for example, refer to the defects that occur in the transistor itself. Please refer to FIG. 4 , which shows a schematic diagram of the device defect according to one embodiment of the present invention. As shown in FIG. 4 , a phenomenon called “device channel high resistance” is shown in the figure, which is resulted from inappropriate stress when forming the gate structure 502 on the fin structure 500 . The device channel high resistance 504 would occur in the fin structure 500 beneath the interface between the fin structure 500 and the gate structure 502 . Where there is a device defect such as device channel high resistance 504 , the resistance value of the device would be changed, resulting also in change of the current when operating. When referring back to the embodiment in FIG. 2 , if the first gate structure 306 A is normal but the second gate structure 306 B has “device channel high resistance”, high resistance would happen at the second gate structure 306 B. The current through the first transistor 332 A may be different from the current through the second transistor 332 B. The device defect can therefore be monitored by measuring currents through the first transistor 332 A and/or the second transistor 332 B.

Regarding to the connection defect, it refers to the defects formed at the connection route between the devices, such as the mis-landing or poor connection of the vias or contact plugs. Please refer to FIG. 5 , which shows a schematic diagram of the connection defect according to one embodiment of the present invention. As shown in FIG. 5 , due to the defects during fabrication, some of the first plugs 328 A, the second plugs 328 B and the common plug 326 α are has poor conductivity. The resistance value would be changed when operating the devices. The current, whether through the first transistor 332 A or the second transistor 332 B, would be changed comparing to a predetermined value. Thus, the connection defect can be monitored by measuring the current through the first transistor 332 A and the second transistor 332 B.

Since both the connection defect and the device defect can be monitored by the current through the first transistor 332 A and/or the second transistor 332 B, the testkey structure 330 in the present invention can be used to monitor if there is a device defect or a connection defect in the testkey structure 330 , thereby monitoring the FinFETs in the die region 404 as well. Please refer to FIG. 6 , which shows a flow chart of the method for measuring a device defect or a connection defect according to embodiment of the present invention. As shown in FIG. 5 , a testkey structure as shown in FIG. 2 is provided (step 600 ). Next, a first current, a second current and a common current are obtained (step 602 ). The first current is measured by turning on the first transistor 332 A, for example, by applying a first threshold voltage (Vt) to the first gate structure 308 A, and applying a common voltage to the common plug 328 α. The first current can be measured at the first plug 328 A. The second current is measured by turning on the second transistor 332 B, for example, by applying a second threshold voltage to the second gate structure 308 B, and applying a common voltage to the common plug 328 α. The second current can be measured at the second plug 328 B. The common current is measured by turning on both the first transistor 332 A and the second transistor 332 B, for example, by applying a first threshold voltage to the first gate structure 308 A and a second threshold voltage to the second gate structure 308 B and applying a common voltage to the first plug 328 A. The common current would be measured at the second plug 328 B. Then, whether a device defect or a connection defect occurs or not will be decided according to the first current, the second current or the common current (step 604 ). If the first current is equal to a first predetermined value, the second current is equal to a second predetermined value, there is no device defect or connection defect occurs (step 606 ). The first predetermined value or the second predetermined value refers to the normal current value that no defect occurs. In one embodiment, the first predetermined value and the second predetermined value can be determined by measuring the first current and the second current from plural testkey structures 330 and calculating the average value therefrom. On the other hand, if the first current is different from a first predetermined value and the second current is different from a second predetermined value and the common current is equal to a predetermined common value, it shows that the connection defect occurs (step 608 ), especially referring to the connection defect between the common plug 326 and the contact plug 318 (It is noted that since the number N of the first plugs 328 A and the second plugs 328 B is greater than the number M of the common plug 326 , it eliminates the possibility of defects on the connection between the first plugs 328 A and the first contact plug 320 A, the second plugs 328 B and the second contact plug 320 B). If the first current is different from a first predetermined value and the second current is equal to a second predetermined value, it is decided that the first transistor 332 A has the device defect (step 610 ) (As discussed above, the un-match of the first current and the first predetermined value would not result from the connect defect between the first plugs 328 A and the first slot contact 320 A). If the first current is equal to a first predetermined value and the second current is different from a second predetermined value, it is decided that the second transistor 332 B has the device defect (step 612 ).

In one embodiment, the testkey structure in the present invention can be expanded along the first direction 400 . Please refer to FIG. 7 and FIG. 8 , which show schematic diagrams of the testkey structure according to another embodiment of the present invention, wherein FIG. 7 shows a top view and FIG. 8 shows a cross-sectional view taken along line DD′ in FIG. 7 . As shown in FIG. 7 and FIG. 8 , comparing to the testkey structure 330 in the previous embodiment in FIG. 2 , the testkey structure 330 ′ in this embodiment further includes a third gate structure 306 C, a third slot contact 320 C, plural third plugs 328 C, a fourth gate structure 306 D, a fourth slot contact 320 D and plural fourth plugs 328 D. The third gate structure 306 C and the fourth gate structure 306 D stretch along the second direction 402 . The third gate structure 306 C, the first gate structure 306 A, the second gate structure 306 B and the fourth gate structure 306 D are arranged in sequence. The components of the third gate structure 306 C and the fourth gate structure 306 D are similar to those of the first gate structure 306 A and the second gate structure 306 B, and thus are omitted for the sake of simplicity. The third drain region 314 C is disposed in the first fin structure 304 α at a side of the third gate structure 306 C opposite to the first common source region 312 α, wherein the third drain region 314 C electrically connects the third slot contact 320 C and the third plugs 328 C. The fourth drain region 314 D is disposed in the first fin structure 304 α at a side of the third gate structure 306 D opposite to the first common source region 312 α, wherein the fourth drain region 314 D electrically connects the fourth slot contact 320 D and the fourth plugs 328 D. The embodiments of the third drain region 314 C, the third slot contact 320 C and the third plug 328 C are similar to the first drain region 314 A, the first slot contact 320 A and the firsts plug 320 A, and so do the fourth drain region 314 D, the fourth slot contact 320 A, and the fourth plug 320 D. The first fin structure 304 α, the third gate structure 306 C, the first drain region 314 A and the third drain region 314 C forms a third transistor 332 C, while the first fin structure 304 α, the fourth gate structure 306 D, the second drain region 314 B and the fourth drain region 314 D forms a fourth transistor 332 D. Similarly, the testkey structure 330 ′ is mirror symmetrical along a horizontal line B and a vertical line C.

Based on the testkey structure 330 ′, another method for measuring device defect or connection defect is further provided. First, a testkey structure 330 ′ is provided. A third current is measured by turning on the first transistor 332 A and the third transistor 332 C. A fourth current is measured by turning on the second transistor 332 B and the fourth transistor 332 D. A second common current is measured by turning on the first transistor 332 A, the second transistor 332 B, the third transistor 332 C and the fourth transistor 332 D. It is then decided whether a device defect or a connection defect occurs or not according to the third current, the fourth current or the second common current. If the third current is equal to a third predetermined value, the fourth current is equal to a fourth predetermined value, there is no device defect or connection defect occurs. In one embodiment, the third predetermined value and the fourth predetermined value can be decided by measuring plural testkey structures 330 ′ and calculating the average value therefrom. If the third current is different from the third predetermined value, the fourth current is different from the fourth predetermined value, and the second common current is the same as a second common predetermined value, it is decided that the connection defect occurs. If the third current is different from the third predetermined value, the fourth current is the same as the fourth predetermined value, it is decided that the first transistor 332 A or the third transistor 332 C has the device defect. If the third current is the same as the third predetermined value, the fourth current is different from the fourth predetermined value, it is decided that the second transistor 332 B or the fourth transistor 332 D has the device defect.

In one embodiment, the testkey structure in the present invention can be expanded along the second direction 402 . Please refer to FIG. 9 , FIG. 10 and FIG. 3 , which show schematic diagrams of the testkey structure according to another embodiment of the present invention, wherein FIG. 9 shows a top view, FIG. 10 shows a cross-sectional view taken along line EE′ in FIG. 9 , and FIG. 3 shows a cross-sectional view taken along line AA′ in FIG. 9 . As shown in FIG. 9 and FIG. 10 , comparing to the testkey structure 330 in the previous embodiment in FIG. 2 , the testkey structure 330 ″ in this embodiment further includes a second fin structure 304 β, a fifth gate structure 306 E, a fifth slot contact 320 E, plural fifth plugs 328 E, a sixth gate structure 306 F, a sixth slot contact 320 F and plural sixth plugs 328 F. The second fin structure 304 β is disposed on the substrate 300 and stretch along the first direction 400 . The fifth gate structure 306 E and the fourth gate structure 306 F are disposed on the second fin structure 304 β and stretch along the second direction 402 . The second common source region 312 β is disposed in the second fin structure 312 β between the fifth gate structure 306 E and the sixth gate structure 306 F. The common slot contact 318 contacts the second common source region 312 β, thereby electrically connecting the first common source region 312 α and the second common source region 312 β. The fifth drain region 314 E is disposed in the second fin structure 304 β at a side of the fifth gate structure 306 E opposite to the second common source region 312 β and is electrically connected to the fifth slot contact 320 E and the fifth plugs 328 E. The sixth drain region 314 F is disposed in the second fin structure 304 β at a side of the sixth gate structure 306 F opposite to the second common source region 312 β and is electrically connected to the sixth slot contact 320 F and the sixth plug 328 F. The embodiments of the fifth drain region 314 E, the fifth slot contact 320 E and the fifth plug 328 E are similar to the first drain region 314 A, the first slot contact 320 A and the first plug 320 A, and so do the sixth drain region 314 F, the sixth slot contact 320 F, and the sixth plug 320 F. The second fin structure 304 β, the fifth gate structure 306 E, the second common source region 312 β and the fifth drain region 314 E forms a fifth transistor 332 E, while the second fin structure 304 β, the sixth gate structure 306 F, the second common source region 312 β and the sixth drain region 314 F forms a sixth transistor 332 F. Similarly, the testkey structure 330 ″ is mirror symmetrical along a horizontal line B and a vertical line C.

Based on the testkey structure 330 ″, another method for measuring device defect or connection defect is further provided. First, a testkey structure 330 ″ is provided. A first current is measured by turning on the first transistor 332 A, and a second current is measured by turning on the second transistor 332 B. A fifth current is measured by turning on the fifth transistor 332 E, and a sixth current is measured by turning on the sixth transistor 332 F. A first common current is measured by turning on the first transistor 332 A and the second transistor 332 B with turning off the fifth transistor 332 E and the sixth transistor 332 F. A second common current is measured by turning on both the fifth transistor 332 E and the sixth transistor 332 F with turning off the first transistor 332 A and the second transistor 332 B. It is then decided whether a device defect or a connection defect occurs according to the first current, the second current, the fifth current, the sixth current, the first common current or the third common current. If the first common current is the same as a first predetermined common value and the second common current is the same as a second predetermined common value, but the first current, the second current, the fifth current and the sixth current are not equal to the first predetermined value, the second predetermined value, the third predetermined value, the fourth predetermined value, it is determined that the connection defects occurs. If there is no connection defects issue, then the device defect issue is individually checked based on the first current v.s. first predetermined value, the second current v.s. the second predetermined current, the third current v.s. the third predetermined value, and the fourth current v.s. the fourth predetermined value, which is similar to the method shown in FIG. 6 .

It is understood that, based on the same principle, the testkey structure can be extended further along the first direction 400 (as the embodiment in FIG. 7 and FIG. 8 ) and/or along the second direction 402 (as the embodiment in FIG. 9 and FIG. 10 ).

In summary, the present invention provides a testkey structure and a method of measuring device defect or connection defect by using said testkey structure. Since the testkey structure is simply and is easy to operate, it can be easily designed as an array so as to gain lots of sample results by quickly scanning the array. Thus, the time for obtaining the sample result and evaluating device defect or connection defect can be greatly saved.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.