High dynamic range storage gate pixel circuitry

This relates generally to imaging devices, and more particularly, to imaging devices with image sensor pixels.

Image sensors are commonly used in electronic devices such as cellular telephones, cameras, and computers to capture images. In a typical arrangement, an electronic device is provided with an array of image pixels arranged in pixel rows and pixel columns.

To eliminate motion artifacts, global shutter CMOS (complementary metal-oxide semiconductor) image sensors incorporate a storage node between the photodiode and readout transistors. Unlike rolling shutter CMOS pixels, the start and end of integration in global shutter CMOS image sensors occur simultaneously for all pixels. Charge stored at the storage node are then readout using the standard rolling shutter method.

Many applications require high dynamic range (HDR) performance. One method for extending the dynamic range for rolling shutter pixels is to capture multiple images with different exposure times and then merge the images together post-capture to create an HDR image. Motion artifacts are a well-known issue with rolling shutter readout. The addition of multiple exposure times only exacerbates the motion artifacts.

It is within this context that the embodiments herein arise.

FIG. 1 is a schematic diagram of an illustrative electronic device with an image sensor having high dynamic range (HDR) storage gate pixel circuitry in accordance with an embodiment.

FIG. 2A is a circuit diagram of an illustrative HDR global shutter pixel in accordance with an embodiment.

FIG. 2B is a top layout view of the pixel shown in FIG. 2A in accordance with an embodiment.

FIG. 2C is a circuit diagram of an illustrative HDR global shutter pixel that shares floating diffusion regions between adjacent columns in accordance with an embodiment.

FIG. 2D is a top layout view of the pixel shown in FIG. 2C in accordance with an embodiment.

FIG. 3A is a timing diagram illustrating how two different exposure times can be captured in accordance with an embodiment.

FIG. 3B is a timing diagram illustrating how an exposure time can be divided into two separate partial exposure times in accordance with an embodiment.

FIGS. 3C and 3D are timing diagrams illustrating how two different exposure times can each be divided into multiple partial exposure times in accordance with an embodiment.

FIG. 4A is a timing diagram illustrating how three different exposure times can be captured in accordance with an embodiment.

FIG. 4B is a timing diagram illustrating how four different exposure times can be captured in accordance with an embodiment.

FIG. 5A is a circuit diagram of an illustrative HDR global shutter pixel that can be used to capture four different exposure times at four separate floating diffusion nodes in accordance with an embodiment.

FIG. 5B is a top layout view of the pixel shown in FIG. 5A in accordance with an embodiment.

FIG. 6 is a timing diagram illustrating how the pixel of FIGS. 5A and 5B can be operating in accordance with an embodiment.

FIG. 7A is a circuit diagram of an illustrative HDR global shutter having a serial readout configuration in accordance with an embodiment.

FIG. 7B is a top layout view of the pixel shown in FIG. 7A in accordance with an embodiment.

FIG. 8 is a flow chart of illustrative steps for operating the pixel of FIGS. 7A and 7B in accordance with an embodiment.

The present embodiments relate to ways for obtaining high dynamic range (HDR) performance in a global shutter image sensor by storing the charge from different integration times into different storage nodes.

An electronic device with a camera module is shown in FIG. 1 . Electronic device 10 (sometimes referred to as an imaging system) may be a digital camera, a computer, a cellular telephone, a medical device, or other electronic device. Camera module 12 (sometimes referred to as an imaging device) may include one or more image sensors 14 and one or more lenses 28 . During operation, lenses 28 (sometimes referred to as optics 28 ) focus light onto image sensor 14 .

Image sensor 14 may include photosensitive elements (e.g., pixels) that convert the light into digital data. Image sensors may have any number of pixels (e.g., hundreds, thousands, millions, or more of imaging pixels). A typical image sensor may, for example, have millions of pixels (e.g., megapixels). As examples, image sensor 14 may include bias circuitry (e.g., source follower load circuits), sample and hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital (ADC) converter circuitry, data output circuitry, memory (e.g., buffer circuitry), address circuitry, etc.

Still and video image data from image sensor 14 may be provided to image processing and data formatting circuitry 16 . Image processing and data formatting circuitry 16 may be used to perform image processing functions such as automatic focusing functions, depth sensing, data formatting, adjusting white balance and exposure, implementing video image stabilization, face detection, etc. For example, during automatic focusing operations, image processing and data formatting circuitry 16 may process data gathered by three-dimensional imaging pixels in image sensor 14 to determine the magnitude and direction of lens movement (e.g., movement of lens 28 ) needed to bring an object of interest into focus.

Image processing and data formatting circuitry 16 may also be used to compress raw camera image files if desired (e.g., to Joint Photographic Experts Group or JPEG format). In a typical arrangement, which is sometimes referred to as a system on chip (SoC) arrangement, camera sensor 14 and image processing and data formatting circuitry 16 are implemented on a common integrated circuit. The use of a single integrated circuit to implement camera sensor 14 and image processing and data formatting circuitry 16 can help to reduce costs. This is, however, merely illustrative. If desired, camera sensor 14 and image processing and data formatting circuitry 16 may be implemented using separate integrated circuits. For example, camera sensor 14 and image processing and data formatting circuitry 16 may be formed using separate integrated circuits that have been stacked.

Camera module 12 may convey acquired image data to host subsystems 20 over path 18 (e.g., image processing and data formatting circuitry 16 may convey image data to subsystems 20 ). Electronic device 10 (sometimes referred to as a system or imaging system) typically provides a user with numerous high-level functions. In a computer or advanced cellular telephone, for example, a user may be provided with the ability to run user applications. To implement these functions, host subsystem 20 of electronic device 10 may include storage and processing circuitry 24 and input-output devices 22 such as keypads, input-output ports, joysticks, and displays. Input-output devices 22 may also include light sources such as light-emitting diodes that may be used in combination with image sensor(s) 14 to obtain time-of-flight depth sensing information. Input-output devices 22 may include, for example, a light source that emits visible or infrared light.

Storage and processing circuitry 24 may include volatile and nonvolatile memory (e.g., random-access memory, flash memory, hard drives, solid state drives, etc.). Storage and processing circuitry 24 may also include microprocessors, microcontrollers, digital signal processors, application specific integrated circuits, or other processing circuits.

FIG. 2A is a circuit diagram of an illustrative HDR global shutter pixel 100 . As shown in FIG. 2A , pixel 100 may include a photodiode (PD) 130 that is coupled to supply line 150 (e.g., a line on which power supply voltage Vpix is provided) via an anti-blooming transistor 110 (controlled by signal AB). Photodiode PD may also be coupled to a shared floating diffusion node 126 via charge transfer transistor 120 a (controlled by signal TX 0 A), storage gate 122 a (controlled by signal SGA), and charge transfer transistor 124 a (controlled by signal TX 1 A). Floating diffusion node 126 may be coupled to a corresponding column readout line 158 via additional pixel readout circuits such as reset (RESFD) transistor 152 , source follower (SF) transistor 154 , and row select (ROW) transistor 156 .

Photodiode 130 may also be coupled to floating diffusion node 126 via charge transfer transistor 120 b (controlled by signal TX 0 B), storage gate 122 b (controlled by signal SGB), and charge transfer transistor 124 b (controlled by signal TX 1 B).

FIG. 2B is a top layout view of the pixel shown in FIG. 2A in accordance with an embodiment. As shown in FIG. 2B , the anti-blooming gate (AB) and the charge transfer gates (TX 0 A associated with a first exposure and TX 0 B associated with a second exposure) may be formed immediately adjacent to photodiode PD. Storage node SGA may be formed between gate TX 0 A and TX 1 A, whereas storage node SGB may be formed between gate TX 0 B and TX 1 B. Additional pixel transistors (e.g., reset transistors, source follower transistors, row select transistors, etc.) may be formed in the vicinity as well.

Configured in this way and referring back to FIG. 2A , photodiode 130 can be readout by two independent storage gate nodes 122 a and 122 b . The extended dynamic range may be obtained by merging together two images captured using a global shutter readout with two different exposure settings.

FIG. 2C is a circuit diagram of an illustrative HDR global shutter pixel 200 that shares floating diffusion regions between adjacent columns in accordance with an embodiment. As shown in FIG. 2C , pixel 200 may include a photodiode 230 that is coupled to supply line 250 (e.g., a line on which power supply voltage Vpix is provided) via an anti-blooming transistor 210 (controlled by signal AB). Photodiode PD may also be coupled to a first floating diffusion node 226 b N via charge transfer transistor 220 a (controlled by signal TX 0 A), storage gate 222 a (controlled by signal SGA), and charge transfer transistor 224 a (controlled by signal TX 1 A). Floating diffusion node 226 b N may be coupled to a corresponding column readout line 258 (in Column N) via additional pixel readout circuits such as reset transistor 252 (in Column N), source follower transistor 254 (in Column N), and row select transistor 256 (in Column N). Moreover, the first floating diffusion node 226 b (in Column N) may also be coupled to charge transfer gates 220 b , 222 b , and 224 b associated with a subsequent column (i.e., column “N+1”).

Photodiode PD may further be coupled to a second floating diffusion node 226 b N− 1 via charge transfer transistor 220 b (controlled by signal TX 0 B), storage gate 222 b (controlled by signal SGB), and charge transfer transistor 224 b (controlled by signal TX 1 B). The second floating diffusion node 226 b N− 1 may be coupled to a corresponding column readout line 258 (in Column N−1) via additional pixel readout circuits such as reset transistor 252 (in Column N−1), source follower transistor 254 (in Column N−1), and row select transistor 256 (in Column N−1). Moreover, the second floating diffusion node 226 b N− 1 may also be coupled to charge transfer gates 220 a , 222 a , and 224 a associated with a preceding column.

FIG. 2D is a top layout view of the pixel shown in FIG. 2C in accordance with an embodiment. As shown in FIG. 2D , the anti-blooming gate (AB) and the charge transfer gates (TX 0 A associated with exposure E 1 and TX 0 B associated with exposure E 2 ) may be formed immediately adjacent to photodiode PD. Storage node SGA may be formed between gate TX 0 A and TX 1 A, whereas storage node SGB may be formed between gate TX 0 B and TX 1 B. Additional pixel transistors (e.g., reset transistors, source follower transistors, row select transistors, etc.) may be formed in the vicinity as well. The source follower (SF) transistor may be coupled to the floating diffusion region from the row below. Each floating diffusion region may be shared between adjacent columns.

Configured in this way and referring back to FIG. 2C , photodiode 230 can be readout by two independent storage gate nodes 222 a and 222 b . The extended dynamic range may be obtained by merging together two images captured using a global shutter readout with two different exposure settings.

For example, consider a scenario in which the image sensor is running at 60 fps (i.e., a 16.667 ms frame time), the read noise is 3 e-rms, and the PD/SG/FD capacity is 15 ke—for this 4.2 um pitch. The start of integration is defined by clocking AB at time t 1 to empty the photodiode (see FIG. 3A ). After 16.650 ms (at time t 2 ), the first exposure (E 1 ) photodiode charge packet is globally clocked to the SGA storage node, and after 0.017 ms (at time t 3 ), the second exposure (E 2 ) photodiode charge packet is globally clocked to the SGB storage node. Signal AB may optionally be clocked at time t 2 , as shown by pulse 300 . Each storage gate node may then read out using the standard rolling shutter mode method. The rolling shutter readout can continue while the photodiode is integrating signal for the E 1 exposure for the next frame.

Merging the two exposures together can help enhance the dynamic range of the final output. The images can be easily merged because since the linearity is the same for both exposures except for a multiplicative scaling factor and since there is a large overlap region for interpolation. There might be 0.017 ms of motion difference between the end of the E 1 and E 2 exposures, but for most application the small amount of motion difference is acceptable.

A timing scheme that eliminates the motion difference between the two images is illustrated in FIG. 3B . Again, pulsing AB at time t 1 starts the integration. After 8.333 ms (at time t 2 ), the first half of the E 1 exposure (labeled 1/2*TintA) charge packet is transferred to the SGA node. After 0.017 ms (at time t 3 ), the E 2 exposure (labeled TintB) charge packet is transferred to the SGB node. While the photodiode is integrating the second half of the E 1 exposure (labeled 1/2*TintA′), all the SGB nodes are readout using a standard rolling shutter method. Then the charge packet from the second half of the E 1 exposure is transferred to the SGA node (at time t 4 ). During the first half of the next frame, the SGA nodes are readout using a standard rolling shutter method.

More complicated (LED Flicker Mitigation) LFM timings are possible if the SGA node can be readout faster than half the frame time. FIG. 3C shows an example where E 1 is sampled four times (see, e.g., the four 4.167 ms partial exposure periods) while E 2 is sampled three times (see, e.g., the three 0.043 ms partial exposure periods). More complicated LFM timings may or may not be possible depending on whether all the SGB or SGA nodes can be readout fast enough. More complicated timing schemes are still possible if part of the E 1 exposure is sacrificed for the necessary rolling shutter overhead, as illustrated in FIG. 3D . FIG. 3D illustrates how E 1 and/or E 2 can be divided into 10 or more partial exposure periods.

FIG. 4A is a timing diagram illustrating how three different exposure times can be captured to further extend the dynamic range. In the example of FIG. 4A , E 1 is sampled twice using SGA (see, e.g., the two 8.257 ms integration periods), E 2 (e.g., the 0.15 ms integration period) is read out using SGB, and E 3 (e.g., the 0.015 ms integration period) is also read out using SGB. In general, at least a 10× factor between the different exposure times may be desirable to maintain a signal-to-noise ratio (SNR) of 40. In other words, the different exposure times can be independently and separately controlled to be linearly related. Independent control of the different exposure times may obviate the need for using a dual conversion gain scheme; thus, a single gain mode might be sufficient. This is merely illustrative. In other suitable embodiments, a factor of at least 2×, 4×, 8×, 16×, 64×, or 100× may be used.

FIG. 4B is a timing diagram illustrating how four different exposure times E 1 -E 4 can be captured to further extend the dynamic range. In the example of FIG. 4B , E 1 is sampled three times using SGA (see, e.g., the three 5.505 ms integration periods), E 2 (e.g., the 0.15 ms integration period) is read out using SGB, E 3 (e.g., the 0.015 ms integration period) is also read out using SGB, and E 4 (e.g., the 0.0015 ms integration period) is also read out using SGB.

From a practical standpoint, it may be difficult to globally read out all the photodiodes in less than 0.0015 ms without spatial integration time shading. Thus, a simple E 4 capture is impractical. One method for an E 4 exposure is, with AB on, to clock TX 0 B/SGB to transfer charge from the PD to SGB. With AB on, only a fraction of the charge will spill into the SGB node. Operated in this way, the linearity of the E 4 capture will be different than the E 1 , E 2 , and E 3 captures, so merging E 4 with the other captures will require a pixel by pixel lookup table and this look-up table will be lens dependent.

Another method for an E 4 exposure is to read out the Global Shutter Efficiency (GSE) signal from the SGB node. The GSE signal depends only on parasitic/stray light and not on charge accumulated in the photodiode. The integration time for this node is set by clocking TX 1 B to clear the SGB node. Unfortunately, this node will have rolling shutter artifacts since all nodes cannot be readout at the same time. Again, the linearity for the EGSE capture will be different than the E 1 , E 2 , and E 3 captures, so merging EGSE with the other captures will again require a pixel by pixel lookup table.

Another E 4 capture method would be to read the GSE signal from the FD node itself.

With only two storage gate nodes SGA and SGB, it might be difficult to create LFM timings where the E 2 and E 3 exposures overlap in time. In another suitable arrangement, additional storage gate nodes may be included. FIGS. 5A show how photodiode 530 can be readout using four independent storage gate nodes. Arranged in this way, an extended dynamic range is obtained by merging together four images with four different exposure settings. With this configuration, the LFM timings can be implemented where all the exposure times overlap.

As shown in FIG. 5A , pixel 500 may include a photodiode 530 that is coupled to supply line 550 (e.g., a line on which power supply voltage Vpix is provided) via an anti-blooming transistor 510 (controlled by signal AB). Photodiode 530 may also be coupled to a first floating diffusion node 526 a via charge transfer transistor 520 a (controlled by signal TX 0 A), storage gate 522 a (controlled by signal SGA), and charge transfer transistor 524 a (controlled by signal TX 1 A). Floating diffusion node 526 a may be coupled to a first corresponding column readout line 558 a via additional pixel readout circuits such as reset transistor 552 a , source follower transistor 554 a , and row select transistor 556 a.

Photodiode 530 may further be coupled to a second floating diffusion node 526 b via charge transfer transistor 520 b (controlled by signal TX 0 B), storage gate 522 b (controlled by signal SGB), and charge transfer transistor 524 b (controlled by signal TX 1 B). Floating diffusion node 526 b may be coupled to a second corresponding column readout line 558 b via additional pixel readout circuits such as reset transistor 552 b , source follower transistor 554 b , and row select transistor 556 b.

Photodiode 530 may further be coupled to a third floating diffusion node 526 c via charge transfer transistor 520 c (controlled by signal TX 0 C), storage gate 522 c (controlled by signal SGC), and charge transfer transistor 524 c (controlled by signal TX 1 C). Floating diffusion node 526 c may be coupled to a third corresponding column readout line 558 c via additional pixel readout circuits such as reset transistor 552 c , source follower transistor 554 c , and row select transistor 556 c.

Photodiode 530 may further be coupled to a fourth floating diffusion node 526 d via charge transfer transistor 520 d (controlled by signal TX 0 D), storage gate 522 d (controlled by signal SGD), and charge transfer transistor 524 d (controlled by signal TX 1 D). Floating diffusion node 526 d may be coupled to a fourth corresponding column readout line 558 d via additional pixel readout circuits such as reset transistor 552 d , source follower transistor 554 d , and row select transistor 556 d.

FIG. 5B is a top layout view of the pixel shown in FIG. 5A in accordance with an embodiment. As shown in FIG. 5B , the anti-blooming gate (AB) and the charge transfer gates (TX 0 A associated with exposure E 1 , TX 0 B associated with exposure E 2 , TX 0 C associated with exposure E 3 , and TX 0 D associated with exposure E 4 ) may be formed immediately adjacent to photodiode PD. Storage node SGA may be formed between gate TX 0 A and TX 1 A; storage node SGB may be formed between gate TX 0 B and TX 1 B; storage node SGC may be formed between gate TX 0 C and TX 1 C; and storage node SGD may be formed between gate TX 0 D and TX 1 D. Additional pixel transistors (e.g., reset transistors, source follower transistors, row select transistors, etc.) for each of the four floating diffusion regions may be formed in the vicinity as well.

An example of an LFM timing is given in FIG. 6 . FIG. 6 shows an example where E 1 is sampled eight times (see, e.g., the eight 2.06 ms partial exposure periods), E 2 is sampled 6 times (see, e.g., the six 0.025 ms partial exposure periods), E 3 is sampled once (see, e.g., the 0.015 ms exposure period), and E 4 is also sampled once (see, e.g., the 0.0015 ms exposure period). This is merely illustrative. If desired, more complicated timing schemes are still possible.

Also note that for the embodiment illustrated in FIGS. 5 and 6 that signal charge that passes through each storage gate (SGA, SGB, SGC, and SGD) is readout a separate transistor trunk (RESET, SF, and ROW). It is possible to connect the FD node associated with SGA, SGB, SGC, and SGD to a single transistor trunk. This will eliminate slight gain differences due to the separate trunks, at the expense of frame rate and charge to voltage conversion gain.

FIG. 7A shows another suitable embodiment where pixel 700 includes four storage nodes separated by three barrier isolation implants. As shown in FIG. 7A , pixel 500 may include a photodiode 730 that is coupled to supply line 750 (e.g., a line on which power supply voltage Vpix is provided) via an anti-blooming transistor 710 (controlled by signal AB). Photodiode 730 may also be coupled to a first storage gate node 722 a via charge transfer transistor 720 a (controlled by signal TX 0 A), to a second storage gate node 722 b via charge transfer transistor 720 b (controlled by signal TX 0 B), to a third storage gate node 722 c via charge transfer transistor 720 c (controlled by signal TX 0 C), and also to a fourth storage gate node 722 d via charge transfer transistor 720 d (controlled by signal TX 0 D).

A first barrier isolation implant (controlled by signal BARA) may be formed between SGA and SGB. A second barrier isolation implant (controlled by signal BARB) may be formed between SGB and SGC. A third barrier isolation implant (controlled by signal BARC) may be formed between SGC and SGD. A charge transfer gate 724 (controlled by signal TX 1 ) may couple storage gate node SGA to floating diffusion node 726 . Floating diffusion node 726 may be coupled to a corresponding column readout line 758 via additional pixel readout circuits such as reset transistor 752 , source follower transistor 754 , and row select transistor 756 . Reading data out from all the storage gates using one a common set of readout circuit (i.e., using at least the same source follower transistor) may be advantageous since the gain will be consistent across all the different exposure times.

FIG. 7B is a top layout view of the pixel shown in FIG. 7A in accordance with an embodiment. As shown in FIG. 7B , the anti-blooming gate (AB) and the charge transfer gates (e.g., TX 0 A, TX 0 B, TX 0 C, and TX 0 D) may be formed immediately adjacent to photodiode PD. Storage node SGA may be formed immediately adjacent to TX 0 A; storage node SGB may be formed immediately adjacent to TX 0 B; storage node SGC may be formed immediately adjacent to TX 0 C; and storage node SGD may be formed immediately adjacent to TX 0 D. Barrier implant BARA may be physically interposed between SGA and SGB; barrier implant BARB may be physically interposed between SGB and SGC; and barrier implant BARC may be interposed between SBC and SGD. Transfer gate TX 1 may be formed between SGA and the floating diffusion region, which is coupled to additional pixel transistors (e.g., reset transistors, source follower transistors, row select transistors, etc.). A lateral overflow drain such as region 710 may be required to guarantee that the E 1 charge packet does not bloom into the E 2 and E 3 packets. Region 710 may be formed immediately adjacent to and electrically and/or physically contact the storage gate nodes and the barrier implant regions.

Moreover, if there are more than one column output line per pixel pitch then the metal wiring can be greatly simplified. This is accomplished by sharing reset, row select, and TX 1 metal lines. The purpose of this disclosure is not optimization of the metal wiring, so all the different configurations if the FD node is 2-shared or 4-shared can be employed. Generalization to those cases are well known to those skilled in the art.

During operation, the PD can be readout globally to any of the SGA, SGB, SGC, or SGD storage nodes. Readout in the SGA node occurs by holding TX 0 A and SGA high; readout in the SGB node occurs by holding TX 0 B and SGB high; etc. Each of the four SG nodes are readout in a rolling shutter fashion at floating diffusion node 726 , and each node is transfer forward using a CCD (Charge-Coupled Device) bucket brigade technique.

As an example, if the E 1 exposure using an LFM timing contains 4 partial captures, the first partial E 1 capture would occur by transferring the PD electron packet into SGD. If the SG nodes advance 1 phase, then after the second E 1 partial capture, the next PD electron packet is transferred into SGC. If the SG nodes advance 1 more phase, then after the third partial E 1 capture, the next PD electron packet is transferred into SGB. Finally, if the SG nodes advance 1 more phase, then after the fourth and final partial E 1 capture, the last PD electron packet is transferred into SGA. Thereafter, the total E 1 charge packet is readout in a rolling shutter manner.

FIG. 8 is a flow chart of illustrative steps for operating pixel 700 of the type shown in FIGS. 7A and 7B . At step 800 , the photodiode may be allowed to integrate for a first exposure period E 1 (or for multiple partial exposure durations that sum to E 1 ). At step 802 , the accumulated charge may be transferred from the PD to the first storage node SGA (e.g., charge could be directly transferred from the PD to SGA or through at least some of SGB-SGD).

At step 804 , the photodiode may be allowed to integrate for a second exposure period E 2 that is different than E 1 (or for multiple partial exposure periods that sum to period E 2 ). At step 806 , the accumulated charge may be transferred from the PD to the second storage node SGB (e.g., charge could be directly transferred from the PD to SGB or through at least some of SGC-SGD).

At step 808 , the photodiode may be allowed to integrated for a third exposure period E 3 that is different than E 1 and E 2 (or for multiple partial exposure periods that sum to E 3 ). At step 810 , the accumulated charge may be transferred from the PD to the third storage node SGC (e.g., charge could be directly transferred from the PD to SGC or also though SGD).

At step 812 , the photodiode may be allowed to integrated for a fourth exposure period E 4 that is different than E 1 -E 3 (or for multiple partial exposure periods that sum to E 4 ). At step 814 , the accumulated charge may be transferred from the PD to the fourth storage node SGD.

At step 816 , charge may be read out from the different storage nodes in a rolling shutter fashion (e.g., the charge may be transferred serially from one storage node to another using the CCD bucket brigade method).

These steps are merely illustrative and are not intended to limit the present embodiments. The existing steps may be modified or omitted; some of the steps may be performed in parallel; additional steps may be added; and the order of certain steps may be reversed or altered.

The foregoing embodiments are merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art. The foregoing embodiments may be implemented individually or in any combination.