Balancing charge pump circuits

The present application claims the benefit of priority under 35 U.S.C. § 119 from U.S. Provisional Patent Application Ser. No. 62/363,025 entitled “Balancing and Driving Charge Pump Circuits,” filed on Jul. 15, 2016, which is hereby incorporated by reference in its entirety for all purposes.

This disclosure generally relates to voltage converters. More particularly, the present disclosure relates to switched capacitor converter circuits that are more reliable.

A charge pump circuit is a type of switched capacitor circuit that may be used to convert a direct current (DC) input voltage to another DC voltage. A charge pump can be configured to generate an output voltage that is a multiple (e.g., 2, 3 . . . N times) the input voltage or it can set an output voltage that is a fraction thereof (e.g., ½, ⅓ . . . 1/N times of the input voltage). In some implementations, such circuit can also generate a negative output voltage from a positive input voltage. Since the charge pump circuit does not require inductors to do the voltage conversion, it is sometimes referred as an inductor-less DC/DC converter.

FIG. 1A illustrates a conventional switched capacitor converter circuit 100 . In the example of FIG. 1A , the input voltage approximately equals 2 times the output voltage at steady state. In the example of FIG. 1A , the transistors, which by way of example only and not by way of limitation, are illustrated to be metal oxide semiconductor field effect transistors (MOSFETs) Q 1 and Q 3 ( 106 and 110 ), are turned ON and OFF in a way that is complimentary to transistors Q 2 and Q 4 ( 108 and 112 ), as illustrated in FIG. 1B . The transistors are shown to switch at around 50% duty cycle. As illustrated in FIG. 1B , during steady state operation, the transistors Q 1 -Q 4 ( 106 to 112 ) are switched to cyclically charge and discharge capacitor 104 , sometimes referred to as a flying capacitor C FLY . By adding feedback to the circuit 100 , transistors Q 1 and Q 4 ( 106 and 112 ) can be driven differently to generate an output voltage V OUT other than V IN /2. For example, different duty ratios may be used to provide the flexibility of providing output voltages that are different factors (e.g., 0.75, 0.5, 0.25, etc.) of the input voltage. Also, by swapping the input and output nodes V IN and V OUT , respectively, the output voltage may be a multiple of the input voltage. For simplicity, as used herein, the term “factor” includes the meaning of fraction and multiple.

In the example of FIG. 1A , when transistors Q 1 106 and Q 3 110 are ON, capacitors C FLY 104 and C OUT 114 are effectively connected in series, thereby charging C FLY 104 and C OUT 114 to approximately V IN /2. The capacitors C FLY 104 and C OUT 114 are initially charged by the input voltage V IN at start-up, where the voltage across the nodes of C FLY 104 and C OUT 114 is at V IN /2. Typically, capacitors are connected external to any controller package due to their large size. The switches Q 1 -Q 4 ( 106 to 112 ) may also be external to the package to accommodate higher currents. The input voltage VIN 102 is directly connected to the top terminal of the transistor Q 1 ( 106 ), where capacitor—C FLY 104 is connected to VIN 102 via transistor Q 1 ( 106 ) when it is ON.

When the transistors Q 2 108 and Q 4 112 are ON, the capacitors C FLY 104 and C OUT 114 are in parallel. This arrangement forces the voltages across capacitors C FLY 104 and C OUT 114 to be substantially similar at approximately V IN /2.

Charge pump circuits, similar to the switched capacitor converter circuit 100 , may be subject to a large inrush current to sensitive circuit elements, such as transistors Q 1 to Q 4 ( 106 to 112 ). For example, the initial voltage across the capacitors, C FLY 104 and C OUT 114 may not be equal to V IN /2 during startup or due to the presence of a fault condition during operation, collectively referred to herein as a transient state. In various scenarios, a fault condition may arise, for example, when a capacitor, such as C OUT 114 , becomes a short circuit. Since there is no inductor in the switched capacitor converter circuit 100 to limit current, the input inrush current can rise quickly to a high level. In high current applications, this huge inrush current is exacerbated since very low ON-resistance MOSFETs may be used to implement transistors Q 1 to Q 4 ( 106 to 112 ) to achieve high power efficiency.

FIG. 1C is an example scenario that illustrates how, upon the V IN power supply powering up at time T 0 (e.g., when the capacitors C FLY 104 -C OUT 114 have a zero initial voltage), the in-rush current 130 may exceed 1000 A, depending on parasitic resistances in the path. The high current may last for a short time (e.g., less than 1 microsecond) but can nonetheless exceed the transistors' 106 to 112 safe operating current, thereby affecting the reliability of the switched capacitor converter circuit 100 in general, and the transistors 106 to 112 in particular. The output voltage V OUT reaches its steady state voltage after the capacitors C FLY 104 and C OUT 114 are fully charged and the switches Q 1 -Q 4 ( 106 to 112 ) are controlled, as illustrated in the context of FIG. 1B . Further, there may be ringing 132 at the output voltage node V OUT after the inrush current, as illustrated in FIG. 1C , which may affect the load 116 . During transient state (e.g., power-up or a fault condition), the voltages on the chip are not predictable because the voltages may not have been fully developed.

The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all of the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps.

FIG. 1A illustrates a conventional switched capacitor converter circuit.

FIG. 1B illustrates example gate driver input waveforms of the transistors of the circuit of FIG. 1A .

FIG. 1C illustrates example waveforms during a startup of the circuit of FIG. 1A .

FIG. 2 is a switched capacitor converter circuit that is coupled to a pre-balance circuit, consistent with an illustrative embodiment.

FIG. 3A is a switched capacitor converter circuit that is coupled to a pre-balance circuit, consistent with another illustrative embodiment.

FIG. 3B is a switched capacitor converter circuit that is coupled to another pre-balance circuit, consistent with an illustrative embodiment.

FIG. 4 is a switched capacitor converter circuit with a buck topology that is coupled to a pre-balance circuit, consistent with an illustrative embodiment.

In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings. Some embodiments may be practiced with additional components or steps and/or without all of the components or steps that are described.

The various methods and circuits disclosed herein generally relate to methods and circuits of providing fault protection for switched capacitor voltage converters. Both multiplying and dividing switched capacitor voltage converters are controlled by various pre-balance circuits such that large inrush currents are prevented, thereby providing a reliable operation of the switched capacitor voltage converters.

FIG. 2 illustrates a switched capacitor converter circuit 201 that is coupled to a pre-balance circuit 230 , consistent with an illustrative embodiment. The components of the switched capacitor converter circuit 201 are similar to those of FIG. 1A and are therefore not repeated here for brevity. The current through the transistors Q 1 to Q 4 ( 206 to 212 ) when the transistors Q 1 to Q 4 operates in the triode region and the capacitors C FLY 204 and C OUT 214 can be approximated by the equations below for both phases of operation:

Phase 1, I =( V IN −V CFLY ( t )− V COUT ( t ))/( R ON _ Q1 +R ON _ Q3 )  (EQ. 1)

Phase 2, I =( V CFLY ( t )− V COUT ( t ))/ R ON _ Q2 +R ON _ Q4 )  (EQ. 2)

Where:

Phase 1 is when transistors Q 1 and Q 3 are ON, and Q 2 and Q 4 are OFF, Phase 2 is when transistors Q 2 and Q 4 are ON, and Q 1 and Q 3 are OFF, I is the current through a transistor that is ON, R ON is the drain to source resistance of a transistor when it is ON, V CFLY (t) is the voltage across the C FLY at time t, and V COUT (t) is the voltage across the C OUT at time t.

The drain to source resistance R ON of each transistor Q 1 to Q 4 ( 206 to 212 ) may have a very low ON resistance for better power efficiency. The lower the R ON of the corresponding transistor, the larger the inrush current may be, thereby providing a potential threat to the reliability of the switched capacitor converter circuit.

Applicants have identified that in view of equations 1 and 2 above, that if the voltages of capacitors C FLY 204 and C OUT 214 are controlled by the manner disclosed herein, the inrush current can be minimized. For example, if the following two conditions of equations 3 and 4 are met, then the inrush current is zero:

Condition 1: V CFLY ( t= 0)= V COUT ( t= 0)  (EQ. 3)

Condition 2: V IN =V CFLY ( t= 0) V COUT ( t= 0)  (EQ. 4)

In various embodiments, the inrush current can be limited to different pre-determined values based on the transistors' Q 1 to Q 4 ( 206 to 212 ) safety operation range. For example, different types of transistors have different tolerances for proper operation that does not lead to a premature reliability degradation of the transistor.

In one embodiment, assuming that the ON-resistance R ON of the transistors Q 1 to Q 4 ( 206 to 212 ) is the same and if the transistor (e.g., MOSFET) maximum safety current is I IMAX , equations 5 and 6 can provide conditions for safe operation of the capacitor converter circuit 201 .

V IN /2−2 R ON *I max <V CFLY ( t= 0)< V IN /2+2 R ON *I max   (EQ. 5)

V IN /2−2 R ON *I max <V COUT ( t= 0)< V IN /2+ 2 R ON *I max   (EQ. 6)

Where:

2R ON *I max is the pre-determined offset voltage V HYS .

Hysteresis and the corresponding offset voltage is discussed in more detail later. The pre-balance circuit 230 is configured to pre-balance the voltage across capacitors C FLY 204 and C OUT 214 such that the conditions of equations 5 and 6 above are met when the switched capacitor converter circuit 201 is operative as a voltage divider charge pump. The pre-balancing of the pre-balancing circuit 230 may be performed during power-up or re-startup of the switched capacitor converter circuit 201 .

In the example of FIG. 2 , the pre-balance circuit includes three current sources 260 , 262 , and 264 , which are able to sink or source current to nodes SW 1 , −V OUT 228 , and SW 2 , respectively. The pre-balance circuit 230 includes a voltage divider, comprising a first resistance element 242 and a second resistance element 246 connected in series. The ratio of the first resistance element 242 to the second resistance element 246 may differ based on the voltage division to be achieved by the switched capacitor converter circuit 201 . For example, for a divide by two charge pump configuration, the first resistance element 242 and the second resistance element 246 may be equal in resistance such that a voltage of V IN /2 is provided at the voltage divider node 244 . The voltage divider is configured to sample the input voltage V IN 202 and provide a scaled version thereof at node 244 . The voltage at node 244 is used as a reference voltage for various components of the pre-balance circuit 230 .

The pre-balance circuit includes a pair of comparators 232 and 238 configured to compare the voltage across the capacitor C FLY 204 with the reference voltage of node 244 . In various embodiments, hysteresis may be added in order to provide a tolerance range for the comparators 232 and 238 . To that end, a first hysteresis voltage source V HYS 234 provides a first hysteresis voltage V HYS to an input terminal of the first comparator 234 . Similarly, a second hysteresis voltage source V HYS 236 is added to an input terminal of the second comparator 238 . In various embodiments, the first hysteresis voltage may be equal in magnitude to the second hysteresis voltage or may be different, depending on the desired hysteresis tolerance range to be implemented for the pre-balance circuit 230 . Put differently, the hysteresis voltage sources 234 and 236 provide threshold levels that, when exceeded, may trigger corrective action to pre-balance a switched capacitor converter circuit 201 .

If the V CFLY voltage is out of a predetermined tolerance defined by the hysteresis voltage sources 234 and 236 , then the pair of comparators 232 and 238 activate the first current source to provide a current to charge or sink the capacitor C FLY 204 and activate the second current source to draw current or source to the capacitor C FLY 204 such that the voltage across the capacitor C FLY 204 is controlled to be within the tolerance range discussed above.

The pre-balance circuit may also include a second pair of comparators 252 and 258 together providing a second comparator circuit that is configured to compare the voltage across capacitor C OUT 214 (i.e., the output voltage V OUT at node 228 ) with the reference voltage of node 244 . Similar to the first pair of comparators 232 and 238 (i.e., the first comparator circuit), hysteresis may be added in order to provide a tolerance range for the comparators 252 and 258 . To that end, a third hysteresis voltage source V HYS 254 provides a third hysteresis voltage V HYS to an input terminal of the first comparator V HYS 252 . Similarly, a fourth hysteresis voltage source V HYS 256 provides a hysteresis voltage to a terminal of the comparator 258 . In various embodiments, the third hysteresis voltage may be equal in magnitude to the fourth hysteresis voltage or may be different, depending on the desired hysteresis tolerance range to be implemented for the voltage across the output capacitance C OUT 214 of the pre-balance circuit 230 .

If the V OUT voltage is out of a predetermined tolerance defined by the hysteresis voltage sources 254 and 256 , then the second pair of comparators 252 and 258 activate the second current source to provide or sink current to adjust (e.g., charge/discharge) the output capacitor C OUT 214 such that the voltage across the output capacitor C OUT 214 is controlled to be within the tolerance range defined by the hysteresis voltage sources 254 and 256 .

In one embodiment, during a capacitor voltage pre-balance phase, the transistors Q 1 to Q 4 ( 206 to 212 ) remain OFF and each current source 260 , 262 , and or 264 draws or sources current to nodes sw 1 , sw 2 , and V OUT based on the sensed voltage across the capacitors C FLY 204 and C OUT 214 . The following equations provide conditions and polarity of each current source, respectively.

For current source I OUT 262 :

V OUT >( V IN /2+ V HYS )  (EQ. 7)

Where: I OUT draws current from node V OUT 228 .

( V IN /2− V HYS )< V OUT <( V IN /2 V HYS )  (EQ. 8)

Where: I OUT is turned OFF.

V OUT <( V IN /2 V HYS )  (EQ. 9)

Where: I OUT provides current to node V OUT 228 .

For current sources I SW1 260 and I SW2 264 :

V CFLY >( V IN /2+ V HYS )  (EQ. 10)

Where: I SW1 draws current from node SW 1 and I SW2 provides current to node SW 2 .

( V IN /2− V hys )< V CFLY <( V IN /2+ V hys )  (EQ. 11)

Where: I SW1 and I SW2 are OFF.

V CFLY <( V IN /2− V hys )  (EQ. 12)

Where: I SW1 provides current to node SW 1 and I SW2 draws current from node SW 2 .

Reference now is made to FIG. 3A , which is a switched capacitor converter circuit 301 that is coupled to a pre-balance circuit 330 , consistent with another illustrative embodiment. The components of the switched capacitor converter circuit 301 are similar to those of the switched capacitor converter circuit 201 and are therefore not discussed in substantial detail. In one embodiment, the switched capacitor converter circuit 301 may include an additional output capacitor C OPT 370 coupled between a terminal of the input voltage V IN 302 and the output capacitor C OUT 314 for better charge sharing and efficiency. As used herein, the term efficiency relates to the amount of input power is used to get a certain amount of power. For example, for a 100% efficient system, there are no losses and the input power used is the same as the output power. The capacitor C OPT 370 provides an additional path in transferring charge to the output capacitor C OUT , thereby reducing the amount of current flowing through the transistors. As a capacitor has lower effective resistance than the power transistors, it therefore has lower losses.

When the switched capacitor converter circuit 301 is configured to be operated as a voltage divider charge pump, as illustrated in FIG. 3A , the pre-balance circuit can be further simplified. For example, pre-balance circuit 330 may use a single current source 360 to charge or discharge the two capacitors C FLY 304 and C OUT 328 at the same time.

The pre-balance circuit 330 includes a voltage divider comprising a first resistance element 342 and a second resistance element 346 connected in series. The ratio of the first resistance element 342 to the second resistance element 346 may differ based on the voltage division to be achieved by the switched capacitor converter circuit 301 . The voltage divider is configured to sample the input voltage V IN 302 and provide a scaled version thereof at node 344 .

The pre-balance circuit 330 also includes a pair of comparators 332 and 338 that are configured to compare the voltage across the capacitor C OUT 314 with the reference voltage of the node 344 . The operation of the pair of comparators 332 and 338 is similar to that of comparators 252 and 258 of FIG. 2 and is therefore not discussed in detail for brevity.

The pre-balance circuit 330 is able to perform the pre-balancing without the use of the additional circuitry of the pre-balance circuit 230 of FIG. 2 , by virtue of a specific timing of activation and deactivation of the transistors Q 1 to Q 4 ( 306 to 312 ) during a capacitor (C OUT ) voltage pre-balance phase. For example, during such phase, transistors Q 2 and Q 4 ( 308 and 312 ) are turned ON (represented by shorted wires) while transistors Q 1 and Q 3 ( 306 and 310 ) are turned OFF (represented by gaps and a drain to source diode connection), as illustrated in FIG. 3A .

Before turning ON transistors Q 2 308 and Q 4 312 , the node SW 1 is pulled to a level substantially similar to V OUT 328 , and the node SW 2 is pulled down to a level substantially similar to GND. In one embodiment, two current sources may be used to pull the node SW 1 to GND and the node SW 2 to GND separately, or two resistance elements may be connected from node SW 1 to GND and node SW 2 to GND separately to pull these two nodes down. When transistors Q 2 308 and Q 4 312 are then turned ON, capacitors C FLY 304 and C OUT 314 are connected in parallel and the voltage across them is the same. The pre-balance circuit 330 charges or discharges the capacitors C FLY 304 and C OUT 314 simultaneously if the voltage sensed across the output capacitor C OUT 314 is not within a predetermined tolerance, as defined by the hysteresis voltage sources 334 and 336 . Alternately, if C FLY 304 is not required to be balanced as precise as capacitor C OUT 314 , the pre-balance may be done with only transistor Q 4 312 being ON (while transistor Q 2 308 is OFF) for simplicity. In such a scenario, the capacitor C FLY 304 may be charged up by the pre-balance circuit 330 through the body diode of Q 2 . The voltage on the C FLY capacitor 304 is one diode voltage drop (e.g., approximately 0.7V) lower than the voltage on the output capacitor C OUT 314 .

FIG. 3B is a switched capacitor converter circuit that is coupled to another pre-balance circuit, consistent with illustrative embodiment. The components of switched capacitor converter circuit 301 and some of the components of the pre-balance circuit 330 B are similar to those of FIG. 3A and are therefore not repeated here for brevity.

The pre-balance circuit 330 B can perform pre-balancing with load current on the output of the switched capacitor converter 301 . If the load current through R LOAD 358 is much less than the current source 360 (e.g., at least 10 time smaller), the current source 360 over-drives the small load current and performs balancing as normal. However, if the load current is comparable or larger than the current source 360 , a disconnect FET DQ 356 is used to disconnect the load current during pre-balancing. In the example of FIG. 3B , the outputs of the two comparators 332 338 are connected to an logic gate 350 , (which, in one embodiment may be an AND gate). The output of the logic gate 350 controls the gate of the disconnect FET QD 356 through an optional RC filter. For example, there is a series resistance element Rg 352 coupled in series between the logic gate 350 and the gate of the disconnect FET QD 356 . There is also a capacitance element Cg 354 coupled between the gate of the disconnect FET QD 356 and ground. The RC filter provided by Rg 352 and Cg 354 may be selected based on the desired delay and speed of turning ON the Disconnect FET QD 356 to meet the requirements of different applications.

The output of the logic gate 350 is high only when the outputs of both comparators 332 and 328 are high. Accordingly, V OUT is within the predetermined tolerance defined by the hysteresis voltage sources 334 and 336 . The logic gate 350 is supplied by a voltage source high enough to turn ON the disconnect FET QD. With the disconnect FET QD 356 , the pre-balancing may be performed in the same way as no load conditions and the load current is applied only after pre-balancing is finished.

Still further, the concepts discussed herein can be used together with various types of DC to DC voltage converters, such as buck, boost, and buck-boost. To that end, FIG. 4 illustrates by way of illustrative example a switched capacitor converter circuit 401 with a buck topology that is coupled to a pre-balance circuit 430 , consistent with an exemplary embodiment. The pre-balance circuit 430 is substantially similar to the pre-balance circuit 230 of FIG. 2 . Similarly, the switched capacitor converter circuit 401 is substantially similar to the switched capacitor converter circuit 201 of FIG. 2 . These blocks are therefore not repeated here for brevity.

The architecture 400 includes an output capacitor C OUT 464 that is coupled between node 480 and GND. There is an inductor L 468 coupled between node SW 2 and the output node V OUT . There is a second capacitor C OUT2 470 coupled between V OUT and GND. There are two resistance elements 472 and 474 coupled in series between V OUT and GND. There is a feedback and control circuit 462 coupled to the interface between the first resistance element 472 and the second resistance element 474 .

In one embodiment, by setting the amplitude of current sources Isw 1 260 and Isw 2 264 to be substantially similar, the hybrid buck converter is allowed to startup into a pre-biased output condition without charging or discharging the output voltage V OUT .

The components, steps, features, objects, benefits, and advantages that have been discussed are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection in any way. Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits, and/or advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently.

For example, any signal discussed herein may be scaled, buffered, scaled and buffered, converted to another mode (e.g., voltage, current, charge, time, etc.,), or converted to another state (e.g., from HIGH to LOW and LOW to HIGH) without materially changing the underlying control method.

The components, steps, features, objects, benefits and advantages that have been discussed are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection in any way. Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently. For example, bipolar transistors (e.g., PNP or NPN) or junction gate field-effect transistors (JFET) can be used instead of MOS transistors. A PNP may be used instead of NPN, and a PMOS may be used instead of NMOS.

Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.

Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.

All articles, patents, patent applications, and other publications that have been cited in this disclosure are incorporated herein by reference.

It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as “first” and “second” and the like may be used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between them. The terms “comprises,” “comprising,” and any other variation thereof when used in connection with a list of elements in the specification or claims are intended to indicate that the list is not exclusive and that other elements may be included. Similarly, an element preceded by an “a” or an “an” does not, without further constraints, preclude the existence of additional elements of the identical type.

The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.