Time de-interleaving circuit and method thereof

This application claims the benefit of Taiwan application Serial No. 105118299, filed Jun. 13, 2016, the subject matter of which is incorporated herein by reference.

The invention relates in general to a time de-interleaving circuit and method, and more particularly to a convolutional time de-interleaving circuit and method.

A receiver of Integrated Services Digital Broadcasting (ISDB) signals adopts convolutional time de-interleaving. In general, time interleaved data (e.g., data generated by a front-end frequency de-interleaving process) is divided into 13 groups, each of which further divided into n sections (n being different values for different transmission modes, as shown in Table-1). A plurality of sets of data of the same section undergo the same delay. The 13 groups of time-interleaved data may be divided into three layers, each of which using an independent time interleaving length l. FIG. 1 shows a schematic diagram of a receiver performing a time de-interleaving process. As shown in FIG. 1 , the 13 groups of time interleaved data respectively correspond to 13 convolutional de-interleaving circuits 110 , each of the 13 convolutional de-interleaving circuits 110 processes one group of data, and n paths respectively correspond to the n sections of data. Based on specifications, the delay length d i of a path i may be represented as (taking a transmission mode 1 for example, where i=0˜95):

d t =I ×(95−(( i× 5)mod 96))   (1)

In equation (1), l is the time interleaving length, and each transmission mode provides a plurality of time interleaving lengths l (as shown in Table-1). In practice, the time de-interleaving process of the convolutional de-interleaving circuits 110 may be achieved through writing/reading a memory. The memory size corresponding to each path is directly proportional to the delay length of the path. Assume that the data size (i.e., the code-word length) of each set of data DX p, q (where X is the number of the convolutional de-interleaving circuit 110 , p is a path number in one convolutional de-interleaving circuit 110 , and q represents the order of the set of data in the section) is 21 bits (e.g., in orthogonal frequency-division multiplexing (OFDM), the in-phase component occupies 7 bits, the quadrature component occupies 7 bits and the channel state information (CSI) occupies 7 bits). When a memory is implemented by a dynamic random access memory (DRAM) having a bit width of 128 bits or by a synchronous dynamic random access memory (SDRAM), and each set of data DX p, q is written, a waste of 107 bits (=128−21) of the memory is caused, which may result in a severe issue in an integrated system where memory resources are valuable.

It is an object of the present invention to provide a time de-interleaving circuit and method to more effectively utilize a memory.

The present invention discloses a time de-interleaving method that performs a time de-interleaving process through writing and reading a plurality of sets of interleaved data into and from a storage circuit. The time de-interleaving method includes: selecting K sets of de-interleaving data from a plurality of sets of de-interleaved data, the K sets of de-interleaved data having a same delay length, K being an integer greater than 1; generating data to be written, the data to be written including the K sets of time de-interleaved data; and in a same writing operation, writing the data to be written into the storage circuit. A bit width of the storage circuit is greater than or equal to a data size of the data to be written.

The present invention further discloses a time de-interleaving circuit. The time de-interleaving circuit includes: a buffer circuit, buffering a plurality of sets of time interleaved data; a storage circuit; and a control circuit, coupled to the buffer circuit and the storage circuit, selecting K sets of time de-interleaved data from the buffer circuit to form data to be written, and writing the data to be written into the storage circuit in a same writing operation. The K sets of data have a same delay length, K is an integer greater than 1, and a bit width of the storage circuit is greater than or equal to a data size of the data to be written.

The present invention further discloses a time de-interleaving method that performs a time de-interleaving process through writing and reading a plurality of sets of interleaved data into and from a first memory and a second memory. The method includes: selecting a set of first time interleaved data and a set of second time interleaved data from the sets of time interleaved data, the set of first time interleaved data and the set of second time interleaved data having a same delay length; writing the set of first time interleaved data into the first memory; and writing the set of second time interleaved data into the second memory. The first memory utilizes a bit width as an access unit, and the second memory has an access unit smaller than the bit width.

The present invention further discloses a time de-interleaving circuit. The time de-interleaving circuit includes: a buffer circuit, buffering a plurality sets of time interleaved data; a first memory, utilizing a bit width as an access unit; a second memory, having an access unit smaller than the bit width; and a control circuit, coupled to the buffer circuit, the first memory and the second memory, selecting a set of first time interleaved data and a set of second time interleaved data from the buffer circuit, and writing the set of first time interleaved data into the first memory and the set of second time interleaved data into the second memory. The set of first time interleaved data and the set of second time interleaved data have a same delay length.

In the time de-interleaving circuit and method of the present invention, time interleaved data having the same delay length forms data to be written, which is written into a memory in a same writing operation. Therefore, the memory may be more efficiently utilized to reduce the waste in memory space. Further, two memories are applied in the present invention to store time interleaved data, and the access unit of one of the memories is a fixed data size while the access unit of the other is not limited.

The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a time de-interleaving process;

FIG. 2 is a block diagram of a time de-interleaving circuit according to an embodiment of the present invention; and

FIG. 3 and FIG. 4 are flowcharts of a time de-interleaving method according to an embodiment of the present invention.

The disclosure of the present invention includes a time de-interleaving circuit and method. In possible implementation, one person skilled in the art my select equivalent elements or steps to achieve the present invention based on the disclosure of the application; that is, the implementation of the present invention is not limited to the embodiments below.

FIG. 2 shows a block diagram of a time de-interleaving circuit according to an embodiment of the present invention. FIG. 3 and FIG. 4 show flowcharts of a time de-interleaving method according to an embodiment of the present invention. A time de-interleaving circuit 220 receives time interleaved data (i.e., the foregoing data DX p, q ) from a frequency de-interleaving circuit 210 , and buffers the time interleaved data in a buffer circuit 222 (step S 310 ). A control circuit 224 then writes and reads data into and from a storage circuit 225 to complete time de-interleaving. The data read from the storage circuit 225 is buffered in the buffer circuit 223 , and is outputted according to a normal time de-interleaving sequence. The storage circuit 225 includes a first memory 226 and a second memory 228 . The first memory 226 (e.g., DRAM or SDRAM) is accessed in a unit of one bit width each time; the second memory 228 may be a DRAM or SDRAM having a bit width smaller than the bit width of the first memory 226 , or a memory that does not have a minimum access unit (e.g., a static random access memory (SRAM)).

Referring to FIG. 1 , several of the 13 convolutional de-interleaving circuits 110 have the same time interleaving length l. For example, assuming that the 0 th convolutional de-interleaving circuit 110 - 1 and the 1 st convolutional de-interleaving circuit 110 - 1 have the same time interleaving length l, according to equation (1), data D 0 0, q and data D 1 0, q undergo the same delay length, and data D 0 1, q and data D 1 1, q undergo the same delay length, and so forth. Further, data having the same q value is generated simultaneously. That is, all of the data D 0 p, 0 , data D 1 p, 0 , . . . and data D 12 p, 0 corresponding to the parameter p in values 0 to (n-1) is simultaneously generated, all of data D 0 p, 1 , data D 1 p, 1 , . . . and data D 12 p, 1 corresponding to the parameter p in values 1 to (n-1) is simultaneously generated, and so forth.

Thus, from the buffer circuit 222 , the control circuit 224 may simultaneously obtain the data D 0 0, 0 and the data D 1 0, 0 , which both correspond to the same delay length; that is, the data D 0 0, 0 and the data D 1 0, 0 may be written into the storage circuit 225 at the same time and read from the storage circuit 225 at the same time by the control circuit 224 to complete the time de-interleaving process. Therefore, when writing into the first memory 226 , the control circuit 224 may consider these two sets of data as one group of data to be written to save the memory space. More specifically, according to the bit width W of the first memory 226 and the code-word length C of the data DX p, q , the control circuit 224 may first calculate that a group of data to be written includes k=[W/C] sets of data DX p, q (step S 320 ). According to the value k, k sets of data DX p, q having the same delay length are selected to form the set of group to be written (step S 330 ), and the group of data to be written is written into the storage circuit 225 (step S 340 ). More specifically, at this point, the group of data to be written is written into the first memory 226 . Table-2 below lists the mapping relationship between several W values and k values (taking C=21 bits for instance).

Taking actual numbers for instance (the scenario 1), assume that the transmission mode of the 13 groups of time interleaved data is 1 and the 13 groups of time interleaved data have the same time interleaving length l=16, the bit width of the first memory 226 is W=128 bits, and the code-word length of the data DX p, q is C=21 bits. Thus, the memory size (bits) that a conventional time de-interleaving method needs is:

In contrast, the time de-interleaving method of the present invention utilizes k−┐128/21┌−6 sets of data DX p, q as one group of data to be written, and so the required memory size (bits) is:

According to the embodiment of the present invention, the memory size needed is only ⅓ of that of the above conventional method.

More specifically, in the foregoing embodiment, D 0 p, q , D 1 p, q , D 2 p, q , D 3 p, q , D 4 p, q and D 5 p, q may be used as one group of data to be written T 0 p, q ; D 6 p, q , D 7 p, q , D 8 p, q , D 9 p, q , D 10 p, q and D 11 p, q may be used as one group of data to be written T 1 p, q ; D 12 p, q may be used as one group of data to be written T 2 p, q . The data DX p, q may be obtained through the buffer circuit 222 , and is the (x*108+p) th set of data at the p th time point in the buffer circuit 222 . The control circuit 224 may accordingly generate an appropriate control signal to write the data DX p, q into the storage circuit 225 . According to the delay length d i corresponding to each set of the data corresponding DX p, q , the control circuit 224 reads the data DX p, q from the storage circuit 225 at corresponding time points. In the foregoing embodiment, the data DX p, q is delayed by 16×(95−(p×5)mod 96) time units and then outputted; that is, the set of data to be outputted T 0 0, q undergoes 16×(95−(0×5)mod 96)=1520 time units in the storage circuit 225 , and is then outputted. At the time point q=1520, T 0 0, 0 is outputted, and T 0 0, 1520 may be written at a position where T 0 0, 0 is originally located in the storage circuit 225 . When T 0 1, 80 is outputted, T 0 1, 1520 is written at a position where T 0 1, 80 is originally located in the storage circuit 225 . That is, when T 0 p, 1520−16 * (95−(p * 5)mod96) is outputted, T 0 p, 1520 is written at a position where T 0 p, 1520−16 * (95−(p * 5)mod96) is originally located in the storage circuit 225 . The control circuit 224 stores the data DX p, q in the buffer circuit 223 after reading the data DX p, q from the storage circuit 225 . It is known from the foregoing reading sequence that, in the buffer circuit 223 , the data DX p, q is sequentially D 0 0, 0 , D 1 0, 0 , D 2 0, 0 , D 3 0, 0 , D 4 0, 0 , D 5 0, 0 , D 0 1, 80 , D 1 1, 80 , D 2 1, 80 , D 3 1, 80 , D 4 1, 80 , D 5 1, 80 , . . . , D 0 p, 1520−16 * (95−(p * 5)mod96) , D 1 p, 1520−16 * (95−(p * 5)mod96) , D 2 p, 1520−16 * (95−(p * 5)mod96) , D 3 p, 1520−16 * (95−(p * 5)mod96) , D 4 p, 1520−16 * (95−(p * 5)mod96) , D 5 p, 1520−16 * (95−(p * 5)mod96) , . . . , D 12 0, 0 , D 12 1, 80 , . . . , D 12 p, 1520−16 * (95−(p * 5)mod96) , . . . , D 12 94, 1376 and D 12 95, 1456 . Next, by adjusting the sequence of outputting the data DX p, q from the buffer circuit 223 , the data DX p, q is outputted into the sequence D 0 0, 0 , D 0 1, 80 , D 0 2, 160 , . . . , D 0 p, 1520−16 * (95−(p * 5)mod96) , . . . , D 0 94, 1376 , D 0 95, 1456, D 1 0, 0 , D 1 1, 80 , D 1 2, 160 , . . . , D 1 p, 1520−16 * (95−(p * 5)mod96) , . . . , D 1 94, 1376 , D 1 95, 1456 , D 2 0, 0 , D 2 1, 80 , D 2 2, 160 , . . . , D 2 p, 1520−16 * (95−(p * 5)mod96) , . . . , D 11 94, 1376 , D 11 95, 1456 , D 12 0, 0 , D 12 1, 80 , D 12 2, 160 , . . . , D 12 p, 1520−16 * (95−(p * 5)mod96) , . . . , D 12 94, 1376 and D 12 95, 1456 .

The 13 groups of time interleaved data may correspond to multiple time interleaving lengths l (the scenario 2). For example, the l value is 16 for four of the groups, 8 for eight of the groups, and 4 for the remaining one group. When the control circuit 224 determines the group of data to be written (step S 330 ) (k=6 in continuation of the above example), the data DX p, q of the four groups with l=16 may form 1 (=┌4/6┐) group of data to be written A, the data DX p, q of the eight groups with l=8 may form 2 (=┌8/6┐) groups of data to be written (respectively data to be written B (including six sets of data) and data to be written C (including two sets of data)), and the remaining one group of data DX p, q form 1 (=┌1/6┐) group of data to be written D. It is discovered that, two of the four groups of data to be written (the data to be written C and the data to be written D) in fact include only one set and two sets of the time interleaved data DX p, q , respectively. Such occurrence results a waste in the first memory 226 . Thus, when the control circuit 224 writes the group of data to be written to the storage circuit 225 (step S 340 ), a detailed process in FIG. 4 is further included.

In step S 342 , the control circuit 224 determines whether a difference between the bit width W of the first memory 226 and the data size of the group of data to be written is greater than the data size of one set of the time-interleaved data DX p, q . If so, the group of data to be written is written into the first memory 226 or the second memory 228 according to a determination condition (step S 346 ). If not, the group of data to be written is written into the first memory 226 (step S 344 ). In continuation of the above scenario 2, the data to be written B is written into the first memory 226 (step S 344 ), and the control circuit 224 then determines to write the data to be written C into the first memory 226 or the second memory 228 according to the determination condition. For example, the determination condition may be (1) whether the actual data size of the group of data to be written exceeds one-half of the bit width W; or (2) the group of data to be written includes only one set of the data DX p, q . For the condition (1), the actual data size of the data to be written A exceeds one-half of the bit width W, and is thus written into the first memory, and the data to be written C and the data to be written D are written into the second memory 228 . For the condition (2), the data to be written A and the data to be written C are written into the first memory 226 , and the data to be written D is written into the second memory 228 . For either the condition (1) or the condition (2), given that the second memory 228 is implemented by a DRAM or SDRAM having bit width that is smaller than the bit width of the first memory 226 , or even implemented by an SRAM, the effect of saving memory space is achieved. Further, in continuation of the scenario (1), whether determination is performed based on the condition (1) or the condition (2), the control circuit 224 writes the data to be written that includes only one set of data DX p, q into the second memory 228 (an SRAM for example). At this point, the space (in bits) used by the first memory 226 is:

And the space (in bits) used by the second memory space 228 is:

Thus, it is equivalently exchanging a space having 1,532,160 bits in the second memory 228 for a space having 9,338,880 (=28,016,640−18,677,760) bits in the first memory 226 . Such design effectively enhances the memory utilization efficiency.

More specifically, in the embodiment in the scenario 2, D 0 p, q , D 1 p, q , D 2 p, q and D 3 p, q may be used as one group of data to be written T 0 p, q , D 4 p, q , D 5 p, q , D 6 p, q and D 7 p, q may be used as one group of data to be written T 1 p, q , D 8 p, q and D 9 p, q may be used as one group of data to be written T 2 p, q , and D 12 p, q may be used as one group of data to be written T 3 p, q . The data DX p, q may be obtained through the buffer circuit 222 , and is the (x*108+p) th set of data at the p th time point in the buffer circuit 222 . Similarly, the control circuit 224 reads the data DX p, q from the storage circuit 225 according to the time points respectively corresponding to the respective delay lengths Di of the sets of the DX p, q . The data of D 0 ˜ 3 p, q is delayed by 16×(95−(p×5)mod 96) time units in the storage circuit 225 and outputted; that is, T 0 0, q undergoes 16×(95−(0×5)mod 96)=1520 time units in the storage circuit 225 and is then outputted. The data of D 4 ˜ 11 p, q is delayed by 8×(95−(p×5)mod 96) time units in the storage circuit 225 and outputted; that is, T 1 0, q and T 2 0, q undergo 8×(95−(0×5)mod 96)=760 time units in the storage circuit 225 and are then outputted. The data of D 12 p, q is delayed by 4×(95(p×5)mod 96) time units in the storage circuit 225 and outputted; that is, T 3 0, q undergoes 4×(95−(p×5)mod 96)=380 time units in the storage circuit 225 and is then outputted. After reading the data DX p, q from the storage circuit 225 , the control circuit 224 stores the data DX p, q in the buffer circuit 223 . Next, through adjusting the sequence of outputting the data data DX p, q from the buffer circuit 223 , the control circuit 224 outputs the data DX p, q to complete the time de-interleaving process.

In an example below, spaces that the first memory 226 and the second memory 228 may occupy for different bit widths of the first memory 226 are listed (taking the scenario 1 for instance):

Bit Width W=64 Bits

Ratio of numbers of sets of Space (in bits) used data DX p,q in first memory Space (in bits) used by second memory 226 and second memory 228 by first memory 226 228 13:0  23,347,200 0 12:1  18,677,760 1,532,160 9:4 14,008,320 6,128,640 6:7 9,338,880 10,725,120  3:10 4,669,440 15,321,600  0:13 0 19,918,080

Bit Width W=128 Bits

Ratio of numbers of sets of Space (in bits) used data DX p,q in first memory Space (in bits) used by second memory 226 and second memory 228 by first memory 226 228 13:0 28,016,640 0 12:1 18,677,760 1,532,160  6:7 9,338,880 10,725,120  0:13 0 19,918,080

Bit Width W=256 Bits

One person skilled in the art may understand implementation details and variations of the present invention with reference to the disclosure of the device in FIG. 2 and the disclosure of the method in FIG. 3 and FIG. 4 . While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.