Display device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2016-033989, filed Feb. 25, 2016, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a display device.

In a display device for use in signage, for the purpose of display scale-up, a multi-display system in which a plurality of display devices are arranged like tiles for display is known. In such a multi-display system, a display image becomes discontinuous at a frame-shaped non-display portion (i.e., a frame) which exists between the display devices. Thus, improvement of the display quality is required. Because of the above requirement, there is a demand for achieving narrower frame structure in each of the display devices.

FIG. 1 is a plan view showing a configuration example of a display device DSP.

FIG. 2 is an enlarged plan view showing a configuration example of area A in the display device DSP shown in FIG. 1 .

FIG. 3 is an illustration showing a cross-section of a display panel PNL.

FIG. 4 is an enlarged plan view showing another configuration example of area A in the display device DSP shown in FIG. 1 .

FIG. 5 is an enlarged plan view showing yet another configuration example of area A in the display device DSP shown in FIG. 1 .

FIG. 6 is an illustration showing a configuration example of a segment SG.

FIG. 7 is an illustration showing a timing chart for describing the operation of the segment SG shown in FIG. 6 .

FIG. 8 is a plan view showing a configuration example of a main pixel PX.

FIG. 9 is a plan view for describing a positional relationship between a pixel electrode and a color filter in the main pixel PX shown in FIG. 8 .

FIG. 10 is an illustration showing a cross-section of a first substrate SUB 1 shown in FIG. 3 .

FIG. 11 is a plan view showing a configuration example of a pixel block B.

FIG. 12 is a plan view for describing a positional relationship between a reflective electrode and a color filter in pixel blocks B 11 to B 13 shown in FIG. 11 .

FIG. 13A is a plan view showing a configuration example of a corner portion CN shown in FIG. 2 .

FIG. 13B is a plan view showing another configuration example of the corner portion CN shown in FIG. 2 .

FIG. 14 is a plan view showing yet another configuration example of the corner portion CN shown in FIG. 2 .

FIG. 15 is a plan view showing a configuration example of the main pixel PX.

FIG. 16 is a plan view for describing a positional relationship between a pixel electrode and a color filter in the main pixel PX shown in FIG. 15 .

FIG. 17 is a plan view showing a configuration example of the pixel block B.

FIG. 18 is a plan view for describing a positional relationship between a reflective electrode and a color filter in pixel blocks B 11 and B 12 shown in FIG. 17 .

FIG. 19 is a plan view for describing a positional relationship between a reflective electrode and a color filter in pixel blocks B 21 and B 22 shown in FIG. 2 .

FIG. 20A is a plan view showing a configuration example of the corner portion CN shown in FIG. 2 .

FIG. 20B is a plan view showing another configuration example of the corner portion CN shown in FIG. 2 .

FIG. 21 is a plan view showing yet another configuration example of the corner portion CN shown in FIG. 2 .

FIG. 22 is an illustration showing a configuration example of a multi-display system.

In general, according to one embodiment, a display device includes: a main pixel comprising a plurality of sub-pixels which exhibit different colors, respectively; a first pixel block adjacent to the main pixel; a second pixel block adjacent to the first pixel block, and electrically connected to the first pixel block; and a driver which drives the main pixel and the first pixel block, wherein the main pixel, the first pixel block, and the second pixel block are located in a display area which displays an image, the display area includes an outer edge portion, the first pixel block is closer to the outer edge portion than the main pixel is, and the second pixel block is closer to the outer edge portion than the first pixel block is, and the second pixel block overlaps the driver in planar view.

Embodiments will be described hereinafter with reference to the accompanying drawings. The disclosure is merely an example, and proper changes within the spirit of the invention, which are easily conceivable by a skilled person, are included in the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are schematically illustrated in the drawings, compared to the actual modes. However, the schematic illustration is merely an example, and adds no restrictions to the interpretation of the invention. In the drawings, reference numbers of continuously arranged elements equivalent or similar to each other may be omitted in some cases. Besides, in the specification and drawings, the structural elements, which have functions identical or similar to the functions described in connection with preceding drawings, are denoted by the same reference numbers, and a duplicated detailed description thereof may be arbitrarily omitted.

FIG. 1 is a plan view showing a configuration example of a display device DSP. In the drawing, a first direction X and a second direction Y intersect each other, and in one example, they are orthogonal to each other. Further, viewing the display device DSP from a normal direction orthogonal to an X-Y plane which is defined by the first direction X and the second direction Y is referred to as a planar view.

The display device DSP includes a display panel PNL, a driver DR, etc. In one example, the display panel PNL is formed in a rectangular shape having a pair of short sides S 1 and S 2 along the first direction X, and a pair of long sides L 1 and L 2 along the second direction Y. However, the shape is not limited to the example illustrated, and the display panel PNL may have the other shape such as a polygonal, circular, or elliptical shape.

The display panel PNL includes a first substrate SUB 1 and a second substrate SUB 2 . The first substrate SUB 1 and the second substrate SUB 2 are bonded to each other by a seal SE. The seal SE is arranged along each of the short sides S 1 and S 2 , and the long sides L 1 and L 2 . The display panel PNL includes a display area DA in which an image is displayed at the inner side with respect to the seal SE. The display area DA includes a main pixel, and a pixel block which functions as a display pixel in a pseudo manner, which will be described in detail later. The first substrate SUB 1 includes a signal line S, a scanning line G, and a conductive line, a power line, etc., not shown, for supplying various voltages, in the display area DA. Signal lines S are arranged in the first direction X. Scanning lines G are arranged in the second direction Y.

The driver DR has the function of driving the main pixel and the pixel block. The driver DR includes peripheral circuits Cr 1 to Cr 4 located at the inner side surrounded by the seal SE. The peripheral circuits Cr 1 to Cr 4 are arranged on the first substrate SUB 1 , and are located on a peripheral portion within the display area DA. In one example, the peripheral circuit Cr 1 is arranged along the short side S 1 , and comprises a signal line drive circuit and the like. The peripheral circuit Cr 2 is arranged along the long side L 1 , and comprises a scanning line drive circuit, a polarity inversion circuit, a common drive circuit, and the like. The peripheral circuit Cr 3 is arranged along the short side S 2 , and comprises a protection circuit and the like. The peripheral circuit Cr 4 is arranged along the long side L 2 , and comprises a scanning line drive circuit, a polarity inversion circuit, a common drive circuit, and the like. The signal lines S are electrically connected to the peripheral circuits Cr 1 and Cr 3 . The scanning lines G are electrically connected to the peripheral circuit Cr 2 or Cr 4 . Note that the driver DR may further include a drive timing generation circuit and a power supply circuit, for example.

In the example illustrated, the display panel PNL comprises a driving IC chip CP. The driving IC chip CP is mounted on a mounting portion MT of the first substrate SUB 1 along the short side S 1 . The driving IC chip CP includes parts of various circuits which constitute the driver DR.

FIG. 2 is an enlarged plan view showing a configuration example of area A in the display device DSP shown in FIG. 1 .

In the display area DA, main pixels PX and pixel blocks B are arranged. In the drawing, each of the main pixels PX and the pixel blocks B is shown in a square shape. The main pixels PX and a part of the pixel blocks B in which a circle is illustrated in the square outline include pixel circuits which are driven by the driver DR. Since pixel blocks B not having a circle in their respective square outlines do not include a pixel circuit, they are electrically connected to the pixel blocks B including the pixel circuits.

The main pixels PX are indicated as white squares in the drawing, and are arranged in a matrix in the first direction X and the second direction Y.

The pixel blocks B include, for example, pixel blocks B 11 to B 13 , pixel blocks B 21 to B 23 , pixel blocks B 31 to B 36 , and pixel blocks B 41 to B 46 .

The pixel blocks B 11 to B 13 are represented as squares with oblique lines sloped downward to the right in the drawing, are arranged in the first direction X, and are electrically connected to each other. The pixel block B 11 corresponds to a pixel block comprising pixel circuits (hereinafter may be simply referred to as a first pixel block), and is adjacent to the main pixel PX. The pixel blocks B 12 and B 13 are located on the side closer to the seal SE (or an outer edge portion of the display area DA) than the pixel block B 11 is. The pixel blocks B 12 and B 13 both correspond to pixel blocks not including pixel circuits (hereinafter may be referred to as a second pixel block and a third pixel block in order to distinguish them from the first pixel block). The pixel block B 12 is adjacent to the pixel block B 11 , and the pixel block B 12 and the pixel block B 11 are connected to each other. The pixel block B 13 is adjacent to the pixel block B 12 , and the pixel block B 13 and the pixel block B 12 are connected to each other. In the example illustrated, the pixel block B 11 is closer to an outer edge portion DAX of the display area DA than the main pixel PX is, the pixel block B 12 is closer to the outer edge portion DAX than the pixel block B 11 is, and the pixel block B 13 is closer to the outer edge portion DAX than the pixel block B 12 is. Note that each of the outer edge portions DAX and DAY corresponds to an inner peripheral portion BMA which faces the display area DA of the seal SE.

The pixel blocks B 21 to B 23 are represented as squares with oblique lines sloped upward to the right in the drawing, are arranged in the second direction Y, and are electrically connected to each other. The pixel block B 21 corresponds to the first pixel block, and is adjacent to the main pixel PX. The pixel blocks B 22 and B 23 are located on the side closer to the seal SE than the pixel block B 21 is. The pixel blocks B 22 and B 23 correspond to the second pixel block and the third pixel block, respectively. The pixel block B 22 is adjacent to the pixel block B 21 , and the pixel block B 22 and the pixel block B 21 are connected to each other. Further, the pixel block B 23 is adjacent to the pixel block B 22 , and the pixel block B 23 and the pixel block B 22 are connected to each other. In the example illustrated, the pixel block B 21 is closer to the outer edge portion DAY of the display area DA than the main pixel PX, the pixel block B 22 is closer to the outer edge portion DAY than the pixel block B 21 , and the pixel block B 23 is closer to the outer edge portion DAY than the pixel block B 22 .

In a corner portion CN of the display area DA, the pixel blocks B 31 to B 36 are electrically connected to each other. The pixel block B 31 corresponds to the first pixel block including the pixel circuits, and the pixel blocks B 32 to B 36 all correspond to the pixel blocks not including the pixel circuits. For example, the pixel block B 32 corresponds to the second pixel block, and the pixel block B 33 or B 34 corresponds to the third pixel block. The pixel blocks B 31 to B 33 are arranged in the first direction X, and are electrically connected to each other. The pixel blocks B 32 and B 34 are adjacent to each other in the second direction Y, and are electrically connected to each other. The pixel blocks B 33 and B 35 are adjacent to each other in the second direction Y, and the pixel block B 35 is electrically connected to each of the pixel blocks B 33 and B 34 . The pixel blocks B 35 and B 36 are adjacent to each other in the second direction Y, and are electrically connected to each other.

The pixel blocks B 41 to B 46 are electrically connected to each other. The pixel block B 41 corresponds to the first pixel block including the pixel circuits, and the pixel blocks B 42 to B 46 all correspond to the pixel blocks not including the pixel circuits. For example, the pixel block 42 corresponds to the second pixel block, and the pixel block B 43 or B 44 corresponds to the third pixel block. The pixel blocks B 41 to B 43 are arranged in the second direction Y, and are electrically connected to each other. The pixel blocks B 42 and B 44 are adjacent to each other in the first direction X, and are electrically connected to each other. The pixel blocks B 44 and B 45 are adjacent to each other in the second direction Y, and the pixel block B 45 is electrically connected to each of the pixel blocks B 43 and B 44 . The pixel blocks B 45 and B 46 are adjacent to each other in the first direction X, and are electrically connected to each other.

Parts of the peripheral circuits Cr 1 and Cr 2 are located in the display area DA. The pixel blocks B 12 and B 13 overlap the peripheral circuit Cr 2 in planar view. Also, the pixel blocks B 22 and B 23 overlap the peripheral circuit Cr 1 in planar view. In the corner portion CN, in the example illustrated, the pixel blocks B 32 and B 33 overlap the peripheral circuit Cr 2 , and the pixel blocks B 42 to B 45 overlap the peripheral circuit Cr 1 .

In the example illustrated, a dummy electrode DM is arranged between the display area DA and the seal SE. The dummy electrode DM is arranged on the first substrate SUB 1 shown in FIG. 1 , and is electrically connected to a power line of a constant potential which is not illustrated. Here, the power line is, for example, a power line of a common potential connected to the common drive circuit. In the example illustrated, the dummy electrode DM overlaps the peripheral circuits Cr 1 and Cr 2 in planar view. Also, the dummy electrode DM is located between the seal SE and the outer edge portion DAX or DAY. While such a dummy electrode DM is arranged in order to capture ionic impurities, for example, it may be omitted.

A light-shielding layer BM is arranged on the second substrate SUB 2 shown in FIG. 1 , and overlaps the seal SE and the dummy electrode DM. However, the light-shielding layer BM does not overlap any of the pixel blocks B.

Next, a configuration example of the display panel PNL which constitutes the display device DSP of the present embodiment will be described. In the present embodiment, as an example of the display device DSP, a reflective liquid crystal display device will be described. The reflective liquid crystal display device displays an image by selectively reflecting light which enters from a display surface side, such as external light and auxiliary light.

FIG. 3 is an illustration showing a cross-section of the display panel PNL. Here, in the cross-section of the display panel PNL in the display area DA, only the structures necessary for explanation are illustrated. The display panel PNL includes the first substrate SUB 1 , the second substrate SUB 2 , a liquid crystal layer LC, and an optical element OD.

The first substrate SUB 1 includes a first insulating substrate 10 , a pixel electrode PE, a first alignment film AL 1 , etc. The pixel electrode PE is located on the first insulating substrate 10 at the side opposed to the second substrate SUB 2 . The pixel electrode PE corresponds to a reflective electrode and includes a reflective layer formed of a light reflective metal material such as aluminum or silver. A structure in which a transparent conductive layer, in addition to the reflective layer, is stacked is applicable to the pixel electrode PE. The transparent conductive layer is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). In the following, the pixel electrode may be referred to as the reflective electrode. The first alignment film AL 1 covers the pixel electrode PE. Although not illustrated, the first substrate SUB 1 includes various circuits such as the above-described peripheral circuits and pixel circuits, in addition to various conductive lines such as the scanning lines and the signal lines, between the first insulating substrate 10 and the pixel electrode PE. That is, the pixel electrode PE is located on various conductive lines and circuits.

The second substrate SUB 2 includes a second insulating substrate 20 , the light-shielding layer BM, a color filter layer CF, an overcoat layer OC, a common electrode CE, a second alignment film AL 2 , etc. The light-shielding layer BM is located on the second insulating substrate 20 at the side opposed to the first substrate SUB 1 . The light-shielding layer BM is opposed to a gap between adjacent pixel electrodes PE in the display area DA illustrated. Also, the light-shielding layer BM is disposed outside the display area DA as shown in FIG. 2 . The color filter layers CF are located on the second insulating substrate 20 at the side opposed to the first substrate SUB 1 , and parts of the color filter layers CF overlap the light-shielding layer BM. The color filter layers CF include a red color filter, a green color filter, a blue color filter, and the like. The red color filter is arranged in a region including a sub-pixel which exhibits red. The green color filter is arranged in a region including a sub-pixel which exhibits green. The blue color filter is arranged in a region including a sub-pixel which exhibits blue. Note that the color filter layers CF may include a color filter of another color, and in one example, the color filter layers CF may include a white color filter arranged in a sub-pixel which exhibits white, or include a transparent layer. The overcoat layer OC covers the color filter layers CF. The common electrode CE is located on the overcoat layer OC at the side opposed to the first substrate SUB 1 . The common electrode CE is opposed to a plurality of pixel electrodes PE. The common electrode CE is formed of a transparent conductive material such as ITO or IZO. The second alignment film AL 2 covers the common electrode CE.

Further, in the second substrate SUB 2 , since the transmissivity can be reduced by stacking color filters of different colors at a boundary between the sub-pixels exhibiting different colors, the light-shielding layer BM may be omitted. In the display panel PNL of the monochrome display type, the color filter layers CF are omitted.

The liquid crystal layer LC is held between the first substrate SUB 1 and the second substrate SUB 2 , and includes liquid crystal molecules LM disposed between the first alignment film AL 1 and the second alignment film AL 2 .

The optical element OD is disposed on a side opposite to a surface of the second substrate SUB 2 , which is in contact with the liquid crystal layer LC. The optical element OD includes, for example, a scattering layer FS, a retardation film RT, and a polarizer PL. The scattering layer FS is adhered to the second insulating substrate 20 , the retardation film RT is stacked on the scattering layer FS, and the polarizer PL is stacked on the retardation film RT. Note that the structure of the optical element OD is not limited to the example illustrated.

The scattering layer FS is an anisotropic scattering layer which scatters incident light from a particular direction. In the example illustrated, the scattering layer FS has the function of mostly passing the incident light from a light source LS in the figure without scattering it, and scattering light from a particular direction, that is, the light reflected by the pixel electrodes PE. It is desirable to stack a plurality of scattering layers FS in order to extend the range of scattering, prevent iridescent color, and the like. The retardation film RT functions as a quarter-wave plate. In one example, the retardation film RT is a stacked layer body constituted by a quarter-wave plate and a half-wave plate. Therefore, a wavelength dependency can be reduced, and a desired phase difference within a wavelength range used for color display can be obtained.

In such a display panel PNL, the side close to the light source LS corresponds to a display surface side. In the example illustrated, the surface of the optical element OD corresponds to a display surface, and if a cover member is disposed on the surface of the optical element OD, the surface of the cover member corresponds to the display surface.

Both the main pixel PX and the pixel block B shown in FIG. 2 include the pixel electrode PE and the color filter layer CF described above. For example, when the pixel block B 12 shown in FIG. 2 comprises the pixel electrode PE shown in the drawing, the peripheral circuit Cr 2 is located between the first insulating substrate 10 and the pixel electrode PE. Although the pixel electrode at a position which overlaps the peripheral circuit is not directly connected to the pixel circuits, such the pixel electrode is connected to another pixel electrode connected to the pixel circuits at a position not overlapping the peripheral circuit. Accordingly, even if the pixel electrode is at a position which overlaps the peripheral circuits, that pixel electrode can be driven via an adjacent pixel electrode.

As can be seen, since the pixel electrode, which is the reflective electrode, is arranged at a position which overlaps the peripheral circuit, also in an area which overlaps the peripheral circuit, light which enters from the display surface side can be selectively reflected, which contributes to display. Accordingly, the display area DA can be broadened not only to an area which does not overlap the peripheral circuit, but also to an area overlapping the peripheral circuit which is closer to the seal SE. Thereby, narrowing of the frame of the display device DSP is enabled.

FIG. 4 is an enlarged plan view showing another configuration example of area A in the display device DSP shown in FIG. 1 .

The configuration example shown in FIG. 4 is different from the configuration example illustrated in FIG. 2 in that a dummy electrode is not provided. Pixel blocks B 11 to B 14 arranged in the first direction X are electrically connected to each other. Pixel blocks B 21 to B 24 arranged in the second direction Y are electrically connected to each other. The pixel blocks B 14 and B 24 are both arranged at positions adjacent to the seal SE.

Pixel blocks B 31 to B 39 are electrically connected to each other. Note that the relationship of connection regarding the pixel blocks B 31 to B 36 is as described referring to FIG. 2 . The pixel blocks B 33 and B 37 are adjacent to each other in the first direction X, and are electrically connected to each other. The pixel blocks B 35 and B 38 are adjacent to each other in the first direction X, and the pixel block B 38 is electrically connected to each of the pixel blocks B 35 and B 37 . The pixel blocks B 38 and B 39 are adjacent to each other in the second direction Y, and are electrically connected to each other. The pixel blocks B 37 to B 39 are all arranged at positions adjacent to the seal SE.

Pixel blocks B 41 to B 50 are electrically connected to each other. Note that the relationship of connection regarding the pixel blocks B 41 to B 46 is as described referring to FIG. 2 . The pixel blocks B 43 and B 47 are adjacent to each other in the second direction Y, and are electrically connected to each other. The pixel blocks B 45 and B 48 are adjacent to each other in the second direction Y, and the pixel block B 48 is electrically connected to each of the pixel blocks B 45 and B 47 . The pixel blocks B 48 , B 49 , and B 50 are arranged in the first direction X, and are electrically connected to each other. The pixel blocks B 47 to B 50 are all arranged at positions adjacent to the seal SE.

The pixel blocks B 12 to B 14 , B 32 , B 33 , and B 37 overlap the peripheral circuit Cr 2 in planar view. The pixel blocks B 22 to B 24 , B 42 to B 45 , B 47 , and B 48 overlap the peripheral circuit Cr 1 in planar view. The light-shielding layer BM overlaps the seal SE, but does not overlap any of the pixel blocks B 11 to B 14 , B 21 to B 24 , B 31 to B 39 , and B 41 to B 50 . The width of the light-shielding layer BM is greater than or equal to the width of the seal SE, and in the example illustrated, the light-shielding layer BM is wider than the seal SE. However, the width of the light-shielding layer BM in the illustrated configuration example is less than that of the configuration example illustrated in FIG. 2 . That is, the outer edge portions DAX and DAY of this configuration example are closer to the seal SE as compared to the configuration example illustrated in FIG. 2 . Among the pixel blocks located in the display area DA, pixel blocks located at the outermost end, i.e., the pixel blocks B 37 to B 39 , and B 47 to B 50 , are closer to the seal SE as compared to those in the configuration example illustrated in FIG. 2 . An interval between these outermost pixel blocks and the seal SE is less than a width of one pixel block.

According to such a configuration example, the display area DA can further be broadened to an area even more close to the seal SE.

FIG. 5 is an enlarged plan view showing yet another configuration example of area A in the display device DSP shown in FIG. 1 .

The configuration example shown in FIG. 5 is different from the configuration example illustrated in FIG. 4 in that a light-shielding layer is not provided. The positional relationship between the pixel block and the peripheral circuit is similar to that of the configuration example shown in FIG. 4 .

According to this configuration example, the display area DA can be broadened similarly to the configuration example shown in FIG. 4 .

Next, a configuration example of a segment SG which constitutes the above-described main pixel PX and pixel block B will be described referring to FIG. 6 . It is assumed that the pixel block B in this explanation corresponds to the first pixel block comprising the pixel circuits among the pixel blocks described above. The segment SG corresponds to the smallest unit which is independently driven in each of the main pixel PX and the first pixel block B. For example, the main pixel PX comprises sub-pixels which exhibit red, green, and blue, respectively, and each of the sub-pixels is constituted of a plurality of segments SG whose areas are different. The first pixel block B is similarly constituted of a plurality of segments SG whose areas are different.

The segment SG includes a liquid crystal capacitance CLC and a pixel circuit CR. The liquid crystal capacitance CLC is a capacitance component of the liquid crystal layer produced between the pixel electrode PE and the common electrode CE. The pixel electrode PE is electrically connected to the pixel circuit CR. The common electrode CE is opposed to the pixel electrode PE and is electrically connected to the common drive circuit not shown, and a common voltage Vcom is applied to the common electrode CE.

The pixel circuit CR includes three switch portions SW 1 to SW 3 and a latch portion LT. For example, the switch portion SW 1 is a single n-channel MOS transistor. In the switch portion SW 1 , one end is electrically connected to the signal line S, and the other end is electrically connected to the latch portion LT. On/Off of the switch portion SW 1 is controlled by a scanning signal supplied from the scanning line G. That is, the switch portion SW 1 is turned on (closed) as a scanning signal ϕV is given from the scanning line drive circuit included in the peripheral circuit Cr 2 or Cr 4 shown in FIG. 1 through the scanning line G, and takes in data (signal potential corresponding to gradation) SIG supplied from the signal line drive circuit included in the peripheral circuit Cr 1 or Cr 3 shown in FIG. 1 through the signal line S.

The latch portion LT includes inverters IV 1 and IV 2 connected in parallel to be opposite to each other. For example, each of the inverters IV 1 and IV 2 is a CMOS inverter. The latch portion LT holds (latches) a potential corresponding to the data SIG taken in by the switch portion SW 1 . That s, the latch portion LT functions as a memory portion capable of holding data.

Although each of the switch portions SW 2 and SW 3 is, for example, a transfer switch in which an re-channel MOS transistor and a p-channel MOS transistor are connected in parallel, a transistor of the other structure can be used. To one end of the switch portion SW 2 , a voltage XFRP which is in opposite phase to the common voltage Vcom is applied. To one end of the switch portion SW 3 , a voltage FRP which is in phase with the common voltage Vcom is applied. The other ends of the switch portions SW 2 and SW 3 are connected to each other, and are also electrically connected to the pixel electrode PE to function as an output node Nout of the pixel circuit CR. Either the switch portion SW 2 or the switch portion SW 3 is turned on depending on the polarity of the holding potential of the latch portion LT. Thereby, the in-phase voltage FRP or the opposite-phase voltage XFRP is applied to the pixel electrode PE in the liquid crystal capacitance CLC in which the common voltage Vcom is applied to the common electrode CE.

FIG. 7 is an illustration showing a timing chart for describing the operation of the segment SG shown in FIG. 6 . In the following, a case where a normally black mode is adopted, that is, black is displayed in a state in which a voltage is not applied to the liquid crystal layer LC, will be explained.

In the pixel circuit CR, the data SIG supplied to the signal line S is taken in at the timing when the scanning signal ϕV is given to the switch portion SW 1 , and a potential corresponding to the taken data SIG is held by the latch portion LT. When the data SIG corresponding to logic 0 is taken in, the holding potential of the latch portion LT becomes negative polarity. In this case, the switch portion SW 2 is turned off (opened) and the switch portion SW 3 is turned on (closed), and the voltage FRP which is in phase with the common voltage Vcom is applied to the pixel electrode PE. Thereby, a pixel potential of the pixel electrode PE becomes equal to the common voltage Vcom of the common electrode CE. Accordingly, no voltage is applied to the liquid crystal layer LC, and the segment SG displays black.

Meanwhile, in the pixel circuit CR, when the data SIG corresponding to logic 1 is taken in, the holding potential of the latch portion LT become positive polarity. In this case, the switch portion SW 3 is turned off (opened) and the switch portion SW 2 is turned on (closed), and the voltage XFRP which is in opposite phase to the common voltage Vcom is applied to the pixel electrode PE. Thereby, a potential difference between the pixel potential of the pixel electrode PE and the common voltage Vcom of the common electrode is created. That is, a voltage is applied to the liquid crystal layer LC. Thus, since light passing through the liquid crystal layer LC is modulated and part of the light contributes to display, the segment SG displays white.

In the above example, a case where a static random access memory (SRAM) is used as a memory portion incorporated in the segment SG has been described. However, the memory portion is not limited to this example, and the other structures such as a dynamic random access memory (DRAM) may be applied.

As described above, in the present embodiment, the segment SG includes a memory portion capable of holding data in the pixel circuit CR, and such a structure may be referred to as a memory-in-pixel (MIP) scheme. According to this structure, the memory portion can store binary data (logic 1/logic 0), and gradation expression can be implemented digitally based on the binary data. As a gradation expression method using such binary data, in the present embodiment, an area gradation method is applied. In the area gradation method, a single sub-pixel includes several segments SG, and the gradation display is realized by a combination of areas of the segments SG. The area gradation method is, for example, a gradation expression method of expressing 2 n gradation levels by N segments SG obtained by weighing the area proportion as 2 0 , 2 1 , 2 2 , . . . , 2 n-1 .

According to such an MIP scheme, since the gradation of a sub-pixel is expressed by using the data held in the memory portion, an operation of writing a signal potential on which the gradation is reflected for each pixel does not need to be executed in a frame period. Therefore, power consumption of the display device DSP can be reduced.

Also, there is a need for rewriting only a part of the main pixels PX in the display screen displayed in the display area DA. In this case, the signal potential of each of the segments SG which partially constitute the main pixel PX may be rewritten. That is, data is transferred to only the main pixel PX which needs to be rewritten, and there is no need to transfer data to the main pixel PX not needing a rewrite. Accordingly, since a data transfer amount can be reduced, there is also an advantage of being able to further reduce power of the display device DSP.

Also, in the structure to which the MIP scheme is applied, either the switch portion SW 2 or SW 3 is turned on depending on the polarity of the holding potential of the latch portion LT, and thus, either the in-phase voltage FRP or the reverse-phase voltage XFRP is applied to the pixel electrode PE. Thereby, since a fixed voltage is constantly applied to the segment SG, shading can be suppressed.

Next, a configuration example of the main pixel PX applicable in the present embodiment will be described.

FIG. 8 is a plan view showing a configuration example of the main pixel PX. The main pixel PX has the shape of a square in which the length in the first direction X and the length in the second direction Y are substantially the same. The main pixel PX comprises four sub-pixels P 1 to P 4 . Areas of the sub-pixels P 1 to P 4 are substantially the same. In the example illustrated, each of the sub-pixels P 1 to P 4 has the shape of a square in which the length in the first direction X and the length in the second direction Y are substantially the same. The sub-pixel P 1 and the sub-pixel P 2 are arranged in the first direction X. The sub-pixel P 3 and the sub-pixel P 4 are arranged in the first direction X. Also, the sub-pixel P 1 and the sub-pixel P 3 are arranged in the second direction Y. The sub-pixel P 2 and the sub-pixel P 4 are arranged in the second direction Y. The sub-pixels P 1 to P 4 exhibit different colors. In one example, the sub-pixel P 1 exhibits green (G), the sub-pixel P 2 exhibits red (R), the sub-pixel P 3 exhibits blue (B), and the sub-pixel P 4 exhibits white (W). Note that the colors corresponding to the sub-pixels P 1 to P 4 shown in FIG. 8 are only an example, and different colors may be adopted for the corresponding sub-pixels. However, the blue (B) and white (W) sub-pixels should preferably be adjacent to each other. Further, the red (R) and green (G) sub-pixels should preferably be adjacent to each other.

In the main pixel PX, the sub-pixels P 1 to P 4 have similar structures. The structure of each of the sub-pixels will be described in detail below. Here, an explanation will be given by taking the sub-pixel P 1 as an example, and detailed explanations of the other sub-pixels will be omitted.

That is, the sub-pixel P 1 comprises three segments SG 11 to SG 13 for performing 3-bit gradation display. The segment SG 11 corresponds to a rectangular region located at the central portion of the sub-pixel P 1 . The segment SG 12 is located closer to the central side of the main pixel PX than the segment SG 11 is. The segment SG 12 corresponds to an L-shaped region including a portion which is adjacent to the sub-pixel P 2 and extends in the second direction Y, and a portion which is adjacent to the sub-pixel P 3 and extends in the first direction X. The area of the segment SG 12 is greater than the area of the segment S 11 . The segment SG 13 is located closer to the peripheral edge of the main pixel PX than the segment SG 11 is. The segment SG 13 corresponds to an L-shaped region including portions extending in the first direction X and the second direction Y, respectively, along the segments SG 11 and SG 12 . The area of the segment SG 13 is greater than the area of the segment S 12 . The ratio of the areas of segment SG 11 , segment SG 12 , and segment SG 13 is, for example, 1:2:4 (=2 0 :2 1 :2 2 ). Note that the combination of the ratio of the areas of the segments SG 11 to SG 13 is not limited to the above example. The segment SG 11 is a display area corresponding to the least significant bit (for example, 2 0 ) in the 3-bit area gradation. The segment SG 13 is a display area corresponding to the most significant bit (for example, 2 2 ) in the 3-bit area gradation. The segment SG 12 is a display area corresponding to the intermediate bit (for example, 2 1 ) in the 3-bit area gradation. By the combination of these segments SG 11 to SG 13 , the 3-bit area gradation display is enabled.

Similarly, the sub-pixel P 2 comprises segments SG 21 to 23 , the sub-pixel P 3 comprises segments SG 31 to 33 , and the sub-pixel P 4 comprises segments SG 41 to 43 .

Next, an example of the layout of the pixel circuit CR corresponding to each segment SG will be described. It is assumed that the pixel circuit CR is formed in an area represented by a one-dot chain line in the drawing. Although the specific structure thereof is not illustrated, the pixel circuit CR may be structured in any way as long as it can realize the equivalent circuit shown in FIG. 6 . Also, the pixel circuits CR illustrated all have the same structure. In one example, although one pixel circuit CR is formed in an area defined by two adjacent signal lines S and two adjacent scanning lines G, the location is not limited to this example. That is, the area may be defined by the other lines such as conductive lines for supplying the voltage FRP or voltage XFRP.

In the example illustrated, pixel circuits CR 11 to CR 13 and pixel circuits CR 21 to CR 23 are arranged in the first direction X. The pixel circuits CR 11 to CR 13 are disposed to correspond to the sub-pixel P 1 , and the pixel circuits CR 21 to CR 23 are disposed to correspond to the sub-pixel P 2 . Pixel circuits CR 31 to CR 33 and pixel circuits CR 41 to CR 43 are arranged in the first direction X. The pixel circuits CR 31 to CR 33 are disposed to correspond to the sub-pixel P 3 , and the pixel circuits CR 41 to CR 43 are disposed to correspond to the sub-pixel P 4 .

Next, the relationship of connection between each pixel circuit CR and the pixel electrode PE will be described. The sub-pixel P 1 comprises pixel electrodes PE 11 to PE 13 located in the segments SG 11 to SG 13 , respectively. The pixel electrode PE 11 has a rectangular shape corresponding to the shape of the segment SG 11 , and is electrically connected to the pixel circuit CR 12 via a connection portion CT 11 . The pixel electrode PE 12 has an L-shaped form corresponding to the shape of the segment SG 12 , and is electrically connected to the pixel circuit CR 13 via a connection portion CT 12 . The pixel electrode PE 13 has an L-shaped form corresponding to the shape of the segment SG 13 , and is electrically connected to the pixel circuit CR 11 via a connection portion CT 13 . The ratio of the areas of pixel electrode PE 11 , pixel electrode PE 12 , and pixel electrode PE 13 is, for example, 1:2:4 (=2 0 :2 1 :2 2 ).

Similarly, in the sub-pixel P 2 , a pixel electrode PE 21 is electrically connected to the pixel circuit CR 22 via a connection portion CT 21 , a pixel electrode PE 22 is electrically connected to the pixel circuit CR 21 via a connection portion CT 22 , and a pixel electrode PE 23 is electrically connected to the pixel circuit CR 23 via a connection portion CT 23 . In the sub-pixel P 3 , a pixel electrode PE 31 is electrically connected to the pixel circuit CR 32 via a connection portion CT 31 , a pixel electrode PE 32 is electrically connected to the pixel circuit CR 33 via a connection portion CT 32 , and a pixel electrode PE 33 is electrically connected to the pixel circuit CR 31 via a connection portion CT 33 . In the sub-pixel P 4 , a pixel electrode PE 41 is electrically connected to the pixel circuit CR 42 via a connection portion CT 41 , a pixel electrode PE 42 is electrically connected to the pixel circuit CR 41 via a connection portion CT 42 , and a pixel electrode PE 43 is electrically connected to the pixel circuit CR 43 via a connection portion CT 43 .

FIG. 9 is a plan view for describing the positional relationship between the pixel electrode and the color filter in the main pixel PX shown in FIG. 8 .

The sub-pixel P 1 includes color filters CF 11 to CF 13 opposed to the pixel electrodes PE 11 to PE 13 , respectively. The color filters CF 11 to CF 13 are green color filters.

Similarly, the sub-pixel P 2 includes color filters CF 21 to CF 23 opposed to the pixel electrodes PE 21 to PE 23 , respectively, the sub-pixel P 3 includes color filters CF 31 to CF 33 opposed to the pixel electrodes PE 31 to PE 33 , respectively, and the sub-pixel P 4 includes color filters CF 41 to CF 43 opposed to the pixel electrodes PE 41 to PE 43 , respectively. The color filters CF 21 to CF 23 are red color filters, the color filters CF 31 to CF 33 are blue color filters, and the color filters CF 41 to CF 43 are white color filters or transparent layers. A light-shielding layer BM represented by hatching in the drawing is disposed between the respective color filters.

If the colors of the sub-pixels P 1 to P 4 are different from the colors shown in FIG. 8 , as described above, the colors of their respective color filters may be changed.

FIG. 10 is an illustration showing a cross-section of the first substrate SUB 1 shown in FIG. 3 . The illustration shows a cross-section of the switch portion SW 1 shown in FIG. 6 , a node electrode EN which serves as the output node Nout, and the pixel electrode PE.

The switch portion SW 1 includes a semiconductor layer SC, a gate electrode GE, and a first electrode E 11 and a second electrode E 12 corresponding to a source and a drain. The semiconductor layer SC is located on the first insulating substrate 10 , and is covered with a first insulating film 11 . The gate electrode GE is located on the first insulating film 11 , and is covered with a second insulating film 12 . The first electrode E 11 and the second electrode E 12 are located on the second insulating film 12 , are in contact with the semiconductor layer SC, and is covered with a third insulating film 13 . The gate electrode GE, the first electrode E 11 , and the second electrode E 12 are electrically connected to the scanning line G, the signal line S, and the latch portion LT, respectively.

The node electrode EN is an electrode connected to the other ends of the switch portions SW 2 and SW 3 shown in FIG. 6 . The node electrode EN is located on the second insulating film 12 , and is covered with the third insulating film 13 . The pixel electrode PE is located on the third insulating film 13 , and is covered with the first alignment film AL 1 . The pixel electrode PE is in contact with the node electrode EN through a contact hole CH which penetrates the third insulating film 13 . A portion at which the pixel electrode PE and the node electrode EN contact each other through the contact hole CH corresponds to the connection portion CT explained referring to FIG. 8 .

The first insulating film 11 and the second insulating film 12 are formed of an inorganic material such as silicon nitride or silicon oxide. The third insulating film 13 is formed of an organic material such as resin. Note that the pixel circuit CR including not only the switch portion SW 1 but also the node electrode EN is located between the first insulating substrate 10 and the third insulating film 13 . Also, although the details of the peripheral circuits Cr 1 to Cr 4 are omitted, they include an re-channel MOS transistor and a p-channel MOS transistor likewise the switch portion SW 1 , and are located between the first insulating substrate 10 and the third insulating film 13 . Further, in the example illustrated, while the switch portion SW 1 is of a top-gate type in which the gate electrode GE is located above the semiconductor layer SC, it may be of a bottom-gate type in which the gate electrode GE is located below the semiconductor layer SC. Furthermore, although the switch portion SW 1 illustrated in the drawing is of a single-gate structure in which one gate electrode GE is opposed to the semiconductor layer SC, it may be of a double-gate structure in which two gate electrodes GE are opposed to the semiconductor layer SC.

Next, a configuration example of the pixel block B applicable in the present embodiment will be described.

FIG. 11 is a plan view showing a configuration example of the pixel block B. Here, a configuration example of the pixel blocks B 11 to B 13 shown in FIG. 2 will be described. In the example illustrated in FIG. 11 , the pixel block B 11 corresponds to the first pixel block, the pixel block B 12 corresponds to the second pixel block, and the pixel block B 13 corresponds to the third pixel block.

The pixel block B 11 comprises pixel circuits CR 51 to CR 53 , and reflective electrodes RE 1 to RE 3 . Here, it is assumed that the pixel circuits CR 51 to CR 53 are formed in areas, each represented by a one-dot chain line in the drawing. Although the specific structures of the pixel circuits are not illustrated, the structures can be any as long as they can each realize the equivalent circuit shown in FIG. 6 . In the example illustrated, the pixel circuits CR 51 to CR 53 have the same structure as the structures of the pixel circuits CR 41 to CR 43 of the sub-pixel P 4 which exhibits white shown in FIG. 8 , and are configured to hold data for white display. That is, the pixel block B 11 is driven based on gradation data of a white sub-pixel, the color of which has the highest reflectivity among green, red, blue, and white.

The reflective electrode RE 1 is located at the central portion of the pixel block B 11 , and has a square shape, and a part EA of the same extends to an area which overlaps the pixel circuit CR 52 . The reflective electrode RE 1 is electrically connected to the pixel circuit CR 52 via a connection portion CT 1 . The reflective electrode RE 2 is located outside the reflective electrode RE 1 , surrounds the reflective electrode RE 1 , and has a C-shaped form having an opening OP 2 at a position adjacent to the pixel block B 12 . The reflective electrode RE 2 is electrically connected to the pixel circuit CR 51 via a connection portion CT 2 . The reflective electrode RE 3 is located outside the reflective electrode RE 2 (in other words, at a peripheral portion of the pixel block B 11 ), surrounds the reflective electrode RE 2 , and has a C-shaped form having an opening OP 3 between the pixel block B 12 and the opening OP 2 . The reflective electrode RE 3 is electrically connected to the pixel circuit CR 53 via a connection portion CT 3 . In the pixel block B 11 described above, the ratio of the areas of reflective electrode RE 1 , reflective electrode RE 2 , and reflective electrode RE 3 is, for example, 1:2:4 (=2 0 :2 1 :2 2 ).

The pixel block B 12 does not include a pixel circuit, but includes reflective electrodes RE 4 to RE 6 . The reflective electrode RE 4 is located at the central portion of the pixel block B 12 , and has a square shape. The reflective electrode RE 5 is located outside the reflective electrode RE 4 , surrounds the reflective electrode RE 4 , and has openings OP 5 at positions adjacent to the pixel blocks B 11 and B 13 , respectively. The reflective electrode RE 6 is located outside the reflective electrode RE 5 (in other words, at a peripheral portion of the pixel block B 12 ), surrounds the reflective electrode RE 5 , and has openings OP 6 at positions adjacent to the pixel blocks B 11 and B 13 , respectively. In the pixel block B 12 described above, the ratio of the areas of reflective electrode RE 4 , reflective electrode RE 5 , and reflective electrode RE 6 is, for example, 1:2:4 (=2 0 :2 1 :2 2 ).

The reflective electrodes RE 3 and RE 6 are connected to each other via a connection portion C 36 extending between the pixel block 311 and the pixel block B 12 . The reflective electrodes RE 2 and RE 5 are connected to each other via a connection portion C 25 which passes through the opening OP 3 of the pixel block B 11 and the opening OP 6 of the pixel block B 12 . The reflective electrodes RE 1 and RE 4 are connected to each other via a connection portion C 14 which passes through the openings OP 2 and OP 3 of the pixel block B 11 and the openings OP 5 and OP 6 of the pixel block B 12 .

Similarly, the pixel block B 13 does not include a pixel circuit, but includes reflective electrodes RE 7 to RE 9 . Although the details are omitted, the reflective electrodes RE 6 and RE 9 are connected to each other via a connection portion C 69 extending between the pixel block B 12 and the pixel block B 13 . The reflective electrodes RE 5 and RE 8 are connected to each other via a connection portion C 58 which passes through the opening OP 6 of the pixel block B 12 and an opening OP 9 of the pixel block B 13 . The reflective electrodes RE 4 and R 7 are connected to each other via a connection portion C 47 which passes through the openings OP 5 and OP 6 of the pixel block B 12 and openings OP 8 and OP 9 of the pixel block B 13 .

Note that the above-described relationship of connection regarding the pixel blocks B 11 to B 13 can be applied to that of the pixel blocks B 21 to B 23 .

FIG. 12 is a plan view for describing the positional relationship between the reflective electrode and the color filter in the pixel blocks B 11 to B 13 shown in FIG. 11 .

The pixel block B 11 is divided into four substantially equal areas, and includes color filters CF 1 to CF 4 in the respective regions. In one example, the color filters CF 1 to CF 4 are color filters of green (G), red (R), blue (B), and white (W), respectively. In the pixel block B 11 illustrated, the color filter CF 1 is located at the upper left region, the color filter CF 2 is located at the upper right region, the color filter CF 3 is located at the lower left region, and the color filter CF 4 is located at the lower right region. These color filters CF 1 to CF 4 are all opposed to the reflective electrodes RE 1 to RE 3 .

Similarly, in each of the pixel blocks B 12 and B 13 , the color filters CF 1 to CF 4 are arranged. The color filters CF 1 to CF 4 of the pixel block B 12 are all opposed to the reflective electrodes RE 4 to RE 6 , and the color filters CF 1 to CF 4 of the pixel block B 13 are all opposed to the reflective electrodes RE 7 to RE 9 . The light-shielding layer BM represented by hatching in the drawing is disposed between the respective pixel blocks, and between the respective color filters.

As described above, according to the configuration examples illustrated in FIGS. 11 and 12 , in the pixel block B 11 including the pixel circuits, the entire pixel block B 11 is driven based on gradation data similar to that of the white sub-pixel, as described above. Each of the color filters CF 1 to CF 4 disposed in the pixel block B 11 has an area equal to one another, and is opposed to the reflective electrodes RE 1 to RE 3 . Accordingly, the pixel block B 11 can implement gradation display of an achromatic color such as white, black or gray. Also, each of the reflective electrodes in the pixel blocks B 12 and B 13 not including the pixel circuits is electrically connected to the corresponding one of the reflective electrodes of the pixel block B 11 , and is driven similarly to the pixel block B 11 based on the gradation data supplied to the pixel circuits of the pixel block B 11 . Accordingly, the pixel blocks B 12 and B 13 can implement gradation display of an achromatic color likewise the pixel block B 11 .

FIG. 13A is a plan view showing a configuration example of the corner portion CN shown in FIG. 2 , and is a figure for explaining the positional relationship between the reflective electrode and the color filter in the pixel blocks B 31 , B 32 , and B 34 . In the example illustrated in FIG. 13A , the pixel block B 31 corresponds to the first pixel block, the pixel block B 32 corresponds to the second pixel block, and the pixel block B 34 corresponds to the third pixel block.

The pixel blocks B 31 and B 32 are adjacent to each other in the first direction X, and the pixel blocks B 32 and B 34 are adjacent to each other in the second direction Y.

Though not described in detail, the pixel block B 31 is structured similarly to the pixel block B 11 shown in FIG. 11 , and includes the pixel circuits not shown, and reflective electrodes RE 11 to RE 13 . The shapes of the reflective electrodes RE 11 to RE 13 are the same as those of the reflective electrodes RE 1 to RE 3 shown in FIG. 11 . Though not described in detail, the pixel block B 32 is structured similarly to the pixel block B 12 shown in FIG. 11 , and includes reflective electrodes RE 14 to RE 16 . The shapes of the reflective electrodes RE 14 to RE 16 are the same as those of the reflective electrodes RE 4 to RE 6 shown in FIG. 11 .

The pixel block B 34 includes a single reflective electrode RE 17 . That is, the reflective electrode RE 17 has a square shape corresponding to the shape of the pixel block B 34 . The reflective electrode RE 17 is electrically connected to the reflective electrode RE 16 having the greatest area (that is, the area corresponding to the most significant bit) in the adjacent pixel block B 32 . The reflective electrodes RE 16 and RE 17 are connected to each other via a connection portion C 1617 extending between the pixel block B 32 and the pixel block B 34 .

The pixel block B 34 is divided into four substantially equal areas, and includes the color filters CF 1 to CF 4 in the respective regions. These color filters CF 1 to CF 4 are all opposed to the reflective electrode RE 17 . The color filters CF 1 to CF 4 are substantially equal to each other in terms of the area in which the color filters CF 1 to CF 4 are opposed to the reflective electrode RE 17 .

Note that the pixel blocks B 35 and B 36 are structured similarly to the pixel block B 34 .

According to such a configuration example, in the pixel block B 34 not including the pixel circuits, since the reflective electrode RE 17 is connected to the reflective electrode RE 16 corresponding to the most significant bit in the adjacent pixel block B 32 , the reflective electrode RE 17 is driven similarly to the reflective electrode RE 16 . That is, the pixel block B 34 can implement one-bit gradation display in accordance with the most significant bit of the pixel block B 32 .

As described above, in the corner portion CN, the electrical connection between the pixel blocks not including the pixel circuits can be complicated. However, as in the present configuration example, since one pixel block includes a single reflective electrode, and this reflective electrode is connected to the reflective electrode corresponding to the most significant bit in the adjacent pixel block, gradation display of at least one bit can be implemented, and it is possible to cause the single reflective electrode to contribute to display in the display area DA.

FIG. 13B is a plan view showing another configuration example of the corner portion CN shown in FIG. 2 , and is a figure for explaining the positional relationship between the reflective electrode and the color filter in the pixel blocks B 31 , B 32 , and B 44 . Note that in the example illustrated in FIG. 2 , the pixel block B 44 is connected to the pixel block B 42 . However, in this example, it is assumed that the pixel block B 44 is connected to the pixel block B 31 . In the example illustrated in FIG. 13B , the pixel block B 31 corresponds to the first pixel block, the pixel block B 32 corresponds to the second pixel block, and the pixel block B 44 corresponds to the third pixel block.

The pixel blocks B 31 and B 32 are adjacent to each other in the first direction X, and the pixel blocks B 31 and B 44 are adjacent to each other in the second direction Y. Explanation of the pixel blocks B 31 and B 32 is omitted.

The pixel block B 44 includes a single reflective electrode RE 18 . That is, the reflective electrode RE 18 has a square shape corresponding to the shape of the pixel block B 44 . The reflective electrode RE 18 is electrically connected to the reflective electrode RE 13 having the greatest area (that is, the area corresponding to the most significant bit) in the adjacent pixel block B 31 . The reflective electrodes RE 13 and RE 18 are connected to each other by a connection portion C 1318 extending between the pixel block B 31 and the pixel block B 44 .

The pixel block B 44 is divided into four substantially equal areas, and includes the color filters CF 1 to CF 4 in the respective regions. These color filters CF 1 to CF 4 are all opposed to the reflective electrode RE 18 . The color filters CF 1 to CF 4 are substantially equal to each other in terms of the area in which the color filters CF 1 to CF 4 are opposed to the reflective electrode RE 18 .

Note that the pixel blocks B 45 and B 46 are structured similarly to the pixel block B 44 .

Also in this configuration example, the same advantages as those of the configuration example shown in FIG. 13A can be obtained.

FIG. 14 is a plan view showing yet another configuration example of the corner portion CN shown in FIG. 2 , and is a figure for explaining the positional relationship between the reflective electrode and the color filter in the pixel blocks B 41 , B 42 , and B 44 . In the example illustrated in FIG. 14 , the pixel block B 41 corresponds to the first pixel block, the pixel block B 42 corresponds to the second pixel block, and the pixel block B 44 corresponds to the third pixel block.

The pixel blocks B 41 and B 42 are adjacent to each other in the second direction Y, and the pixel blocks B 42 and B 44 are adjacent to each other in the first direction X.

Though not described in detail, the pixel block B 41 is structured similarly to the pixel block B 31 shown in FIG. 13A , and includes the pixel circuits not shown, and reflective electrodes RE 11 to RE 13 . The pixel block B 42 includes the reflective electrodes RE 14 to RE 16 , though not described in detail. The reflective electrode RE 14 is connected to the reflective electrode RE 11 , the reflective electrode RE 15 is connected to the reflective electrode RE 12 , and the reflective electrode RE 16 is connected to the reflective electrode RE 13 .

The pixel block B 44 includes a single reflective electrode RE 18 . That is, the reflective electrode RE 18 has a square shape corresponding to the shape of the pixel block B 44 . The reflective electrode RE 18 is electrically connected to the reflective electrode RE 16 having the greatest area (that is, the area corresponding to the most significant bit) in the adjacent pixel block B 42 . The reflective electrodes RE 16 and RE 18 are connected to each other by a connection portion C 1618 extending between the pixel block B 42 and the pixel block B 44 .

The pixel block B 44 is divided into four substantially equal areas, and includes the color filters CF 1 to CF 4 in the respective regions. These color filters CF 1 to CF 4 are all opposed to the reflective electrode RE 18 . The color filters CF 1 to CF 4 are substantially equal to each other in terms of the area in which the color filters CF 1 to CF 4 are opposed to the reflective electrode RE 18 .

Also in this configuration example, the same advantages as those of the configuration example shown in FIG. 13A can be obtained.

In Embodiment 1, a case where the main pixel PX and the pixel block B both have a structure corresponding to 3 bits has been described. In the present embodiment, an example of a case where a main pixel PX and a pixel block B both have a structure corresponding to 2 bits will be described. Note that the structures of the present embodiment similar to those of Embodiment 1 will not be described, and elements with the same reference numbers as those of Embodiment 1 denote the same elements.

First, a configuration example of the main pixel PX will be described.

FIG. 15 is a plan view showing a configuration example of the main pixel PX. The main pixel PX has the shape of a square in which the length in the first direction X and the length in the second direction Y are substantially the same. The main pixel PX comprises three sub-pixels P 1 to P 3 . The sub-pixels P 1 to P 3 are arranged in the first direction X. Areas of the sub-pixels P 1 to P 3 are substantially the same. In each of the sub-pixels P 1 to P 3 , the ratio of the length in the first direction X to the length in the second direction Y is 1:3. The sub-pixels P 1 to P 3 exhibit different colors. In one example, the sub-pixel P 1 exhibits red (R), the sub-pixel P 2 exhibits green (G), and the sub-pixel P 3 exhibits blue (B).

In the main pixel PX, each of the sub-pixels P 1 to P 3 has a structure similar to the structure for implementing 2-bit gradation display. The structure of each of the sub-pixels will be described in detail below. Here, an explanation will be given by taking the sub-pixel P 1 as an example, and detailed explanations of the other sub-pixels will be omitted.

The sub-pixel P 1 comprises pixel circuits CR 61 and CR 62 , and pixel electrodes PE 611 , PE 62 , and PE 612 . Here, each of the pixel circuits CR 61 and CR 62 is indicated by a one-dot chain line in the drawing. Each of the pixel electrodes PE 611 , PE 62 , and PE 612 has an area equal to one another, and those pixel electrodes are arranged in the second direction Y. The pixel electrodes PE 611 and PE 612 are electrically connected to each other by a relay electrode RL 61 . The relay electrode RL 61 is electrically connected to the pixel circuit CR 61 via a connection portion CT 61 . The pixel electrode PE 62 is electrically connected to the pixel circuit CR 62 via a connection portion CT 62 . That is, in the sub-pixel P 1 , of the three pixel electrodes arranged in the second direction Y, the pixel electrode PE 62 located in the middle and the two pixel electrodes PE 611 and PE 612 located at the both ends are driven independently. The ratio of a total area of the pixel electrode PE 611 and the pixel electrode PE 612 to the area of the pixel electrode PE 62 is, for example, 2:1 (=2 1 :2 0 ).

Similarly, in the sub-pixel P 2 , a relay electrode RL 63 electrically connects pixel electrodes PE 631 and PE 632 to each other, and is electrically connected to a pixel circuit CR 63 via a connection portion CT 63 . A pixel electrode PE 64 is electrically connected to a pixel circuit CR 64 via a connection portion CT 64 . In the sub-pixel P 3 , a relay electrode RL 65 electrically connects pixel electrodes PE 651 and PE 652 to each other, and is electrically connected to a pixel circuit CR 65 via a connection portion CT 65 . A pixel electrode PE 66 is electrically connected to a pixel circuit CR 66 via a connection portion CT 66 .

FIG. 16 is a plan view for describing the positional relationship between the pixel electrode and the color filter in the main pixel PX shown in FIG. 15 .

The sub-pixel P 1 includes color filters CF 1 opposed to the pixel electrodes PE 611 , PE 62 , and PE 612 , respectively. The sub-pixel P 2 includes color filters CF 2 opposed to the pixel electrodes PE 631 , PE 64 , and PE 632 , respectively. The sub-pixel P 3 includes color filters CF 3 opposed to the pixel electrodes PE 651 , PE 66 , and PE 652 , respectively. The color filter CF 1 is a red color filter, the color filter CF 2 is a green color filter, and the color filter CF 3 is a blue color filter. A light-shielding layer BM represented by hatching in the drawing is disposed between the respective color filters.

Next, a configuration example of the pixel block B will be described.

FIG. 17 is a plan view showing a configuration example of the pixel block B. Here, a configuration example of the pixel blocks B 11 and B 12 shown in FIG. 2 will be described.

The pixel block B 11 comprises pixel circuits CR 71 and CR 72 , reflective electrodes RE 111 to RE 113 , RE 121 to RE 123 , and RE 131 to RE 133 , and a relay electrode RL 71 . Here, each of the pixel circuits CR 71 and CR 72 is indicated by a one-dot chain line in the drawing. In the example illustrated, the pixel circuits CR 71 and CR 72 have the same structures as the structures of the pixel circuits CR 63 and CR 64 of the sub-pixel P 2 which exhibits green shown in FIG. 15 , and are configured to hold data for green display. That is, the pixel block B 11 is driven based on gradation data of a green sub-pixel, the color of which has the highest reflectivity among green, red, and blue.

In the pixel block B 11 , the reflective electrodes RE 111 to RE 113 are located on the upper side of the drawing, the reflective electrodes RE 121 to RE 123 are located at the central portion of the drawing, and the reflective electrodes RE 131 to RE 133 are located on the lower side of the drawing. Each of the reflective electrodes RE 111 to RE 113 , RE 121 to RE 123 , and RE 131 to RE 133 has the same shape, and the same area. The reflective electrodes RE 111 to RE 113 are arranged in the first direction X, and are connected to each other. The reflective electrodes RE 121 to RE 123 are arranged in the first direction X, and are connected to each other. The reflective electrodes RE 131 to RE 133 are arranged in the first direction X, and are connected to each other.

The relay electrode RL 71 electrically connects the reflective electrode RE 112 and RE 132 to each other, and is electrically connected to the pixel circuit CR 71 via a connection portion CT 71 . The reflective electrode RE 122 is electrically connected to the pixel circuit CR 72 via a connection portion CT 72 . In the pixel block B 11 described above, the ratio of a total area of the reflective electrodes RE 111 to RE 113 and RE 131 to RE 133 to the area of the reflective electrodes RE 121 to RE 123 is, for example, 2:1 (=2 1 :2 0 ).

The pixel block B 12 does not include a pixel circuit, but includes reflective electrodes RE 141 to RE 143 , RE 151 to RE 153 , and RE 161 to RE 163 . The reflective electrodes RE 141 to RE 143 are arranged in the first direction X, and are connected to each other, and the reflective electrodes RE 141 to RE 143 and the reflective electrodes RE 111 to RE 113 are located on the same straight line. The reflective electrode RE 143 is connected to the reflective electrode RE 111 . The reflective electrodes RE 151 to RE 153 are arranged in the first direction X, and are connected to each other, and the reflective electrodes RE 151 to RE 153 and the reflective electrodes RE 121 to RE 123 are located on the same straight line. The reflective electrode RE 153 is connected to the reflective electrode RE 121 . The reflective electrodes RE 161 to RE 163 are arranged in the first direction X, and are connected to each other, and the reflective electrodes RE 161 to RE 163 and the reflective electrodes RE 131 to RE 133 are located on the same straight line. The reflective electrode RE 163 is connected to the reflective electrode RE 131 . In the pixel block B 12 described above, the ratio of a total area of the reflective electrodes RE 141 to RE 143 and RE 161 to RE 163 to the area of the reflective electrodes RE 151 to RE 153 is, for example, 2:1 (=2 1 :2 0 ).

FIG. 18 is a plan view for describing the positional relationship between the reflective electrode and the color filter in the pixel blocks B 11 and B 12 shown in FIG. 17 .

The pixel block B 11 is divided into three substantially equal areas, and includes color filters CF 1 to CF 3 in the respective regions. In one example, the color filters CF 1 to CF 3 are color filters of red (R), green (G), and blue (B), respectively. In the pixel block B 11 illustrated, the color filter CF 1 is located at the left region, the color filter CF 3 is located at the right region, and the color filter CF 2 is located between the color filters CF 1 and CF 3 . The color filter CF 1 is opposed to the reflective electrodes RE 111 , RE 121 , and RE 131 . The color filter CF 2 is opposed to the reflective electrodes RE 112 , RE 122 , and RE 132 . The color filter CF 3 is opposed to the reflective electrodes RE 113 , RE 123 , and RE 133 .

Similarly, in the pixel block B 12 , each of the color filters CF 1 to CF 3 is arranged. The color filter CF 1 is opposed to the reflective electrodes RE 141 , RE 151 , and RE 161 . The color filter CF 2 is opposed to the reflective electrodes RE 142 , RE 152 , and RE 162 . The color filter CF 3 is opposed to the reflective electrodes RE 143 , RE 153 , and RE 163 . The light-shielding layer BM represented by hatching in the drawing is disposed between the respective pixel blocks, and between the respective color filters.

As described above, according to the configuration examples illustrated in FIGS. 17 and 18 , in the pixel block B 11 including the pixel circuits, the entire pixel block B 11 is driven based on gradation data similar to that of the green sub-pixel, as described above. Each of the color filters CF 1 to CF 3 disposed in the pixel block B 11 has an area equal to one another, and is opposed to the reflective electrodes. Accordingly, the pixel block B 11 can implement gradation display of an achromatic color such as white, black or gray. Also, each of the reflective electrodes in the pixel block B 12 not including the pixel circuits is connected to the corresponding one of the reflective electrodes of the pixel block B 11 , and is driven similarly to the pixel block B 11 based on the gradation data supplied to the pixel circuits of the pixel block B 11 . Accordingly, the pixel blocks B 12 can implement gradation display of an achromatic color likewise the pixel block B 11 .

FIG. 19 is a plan view for describing the positional relationship between the reflective electrode and the color filter in the pixel blocks B 21 and B 22 shown in FIG. 2 .

The pixel block B 21 includes pixel circuits CR 81 to CR 83 , reflective electrodes RE 211 to RE 213 , RE 221 to RE 223 , and RE 231 to RE 233 . Here, each of the pixel circuits CR 81 to CR 83 is indicated by a one-dot chain line in the drawing, and each of the reflective electrodes RE 211 to RE 213 , RE 221 to RE 223 , and RE 231 to RE 233 is indicated by a dotted line in the drawing. The pixel circuits CR 81 to CR 83 are structured to be the same as the pixel circuits CR 61 , CR 63 , and CR 65 shown in FIG. 15 . That is, the pixel block B 21 is driven based on gradation data of the most significant bit for each of green, red, and blue.

In the pixel block B 21 , the reflective electrodes RE 211 to RE 213 are located on the left side of the drawing, the reflective electrodes RE 221 to RE 223 are located at the central portion of the drawing, and the reflective electrodes RE 231 to RE 233 are located on the right side of the drawing. Each of the reflective electrodes RE 211 to RE 213 , RE 221 to RE 223 , and RE 231 to RE 233 has the same shape, and the same area. The reflective electrodes RE 211 to RE 213 are arranged in the second direction Y, are connected to each other, and are electrically connected to the pixel circuit CR 81 via a connection portion CT 81 . The reflective electrodes RE 221 to RE 223 are arranged in the second direction Y, are connected to each other, and are electrically connected to the pixel circuit CR 82 via a connection portion CT 82 . The reflective electrodes RE 231 to RE 233 are arranged in the second direction Y, are connected to each other, and are electrically connected to the pixel circuit CR 83 via a connection portion CT 83 .

The pixel block B 22 does not include a pixel circuit, but includes reflective electrodes RE 241 to RE 243 , RE 251 to RE 253 , and RE 261 to RE 263 . The reflective electrodes RE 241 to RE 243 are arranged in the second direction Y, and are connected to each other, and the reflective electrodes RE 241 to RE 243 and the reflective electrodes RE 211 to RE 213 are located on the same straight line. The reflective electrode RE 241 is connected to the reflective electrode RE 213 . The reflective electrodes RE 251 to RE 253 are arranged in the second direction Y, and are connected to each other, and the reflective electrodes RE 251 to RE 253 and the reflective electrodes RE 221 to RE 223 are located on the same straight line. The reflective electrode RE 251 is connected to the reflective electrode RE 223 . The reflective electrodes RE 261 to RE 263 are arranged in the second direction Y, and are connected to each other, and the reflective electrodes RE 261 to RE 263 and the reflective electrodes RE 231 to RE 233 are located on the same straight line. The reflective electrode RE 261 is connected to the reflective electrode RE 233 .

In the pixel block B 21 , the color filter CF 1 is opposed to the reflective electrodes RE 211 to RE 213 , the color filter CF 2 is opposed to the reflective electrodes RE 221 to RE 223 , and the color filter CF 3 is opposed to the reflective electrodes RE 231 to RE 233 .

In the pixel block B 22 , the color filter CF 1 is opposed to the reflective electrodes RE 241 to RE 243 , the color filter CF 2 is opposed to the reflective electrodes RE 251 to RE 253 , and the color filter CF 3 is opposed to the reflective electrodes RE 261 to RE 263 . The light-shielding layer BM represented by hatching in the drawing is disposed between the respective pixel blocks, and between the respective color filters.

According to such a configuration example, in the pixel block B 21 including the pixel circuits CR 81 to CR 83 corresponding to green, red, and blue, a color can be displayed with an 8-level gradation. Also, each of the reflective electrodes in the pixel block B 22 not including the pixel circuits is connected to the corresponding one of the reflective electrodes of the pixel block B 21 , and is driven similarly to the pixel block B 21 based on the gradation data supplied to the pixel circuits CR 81 to CR 83 of the pixel block B 21 . Accordingly, the pixel block B 22 can display a color with an 8-level gradation likewise the pixel block B 21 .

FIG. 20A is a plan view showing a configuration example of the corner portion CN shown in FIG. 2 , and is a figure for explaining the positional relationship between the reflective electrode and the color filter in the pixel blocks B 31 , B 32 , and B 34 . In the example illustrated in FIG. 20A , the pixel block B 31 corresponds to the first pixel block, the pixel block B 32 corresponds to the second pixel block, and the pixel block B 34 corresponds to the third pixel block.

The pixel blocks B 31 and B 32 are adjacent to each other in the first direction X, and the pixel blocks B 32 and B 34 are adjacent to each other in the second direction Y.

Though not described in detail, the pixel block B 31 is structured similarly to the pixel block B 11 shown in FIG. 17 , and includes the pixel circuits not shown, and reflective electrodes RE 311 to RE 313 , RE 321 to RE 323 , and RE 331 to RE 333 . Though not described in detail, the pixel block B 32 is structured similarly to the pixel block B 12 shown in FIG. 17 , and includes reflective electrodes RE 341 to RE 343 , RE 351 to RE 353 , and RE 361 to RE 363 .

The pixel block B 34 includes reflective electrodes RE 371 to RE 379 . The reflective electrodes RE 371 to RE 379 function as a substantially single reflective electrode RE 37 as the electrodes adjacent to one another in the first direction X and the second direction Y are mutually connected. The reflective electrode RE 374 is connected to the reflective electrode RE 362 corresponding to the most significant bit in the adjacent pixel block B 32 .

In the pixel block B 34 , the color filter CF 1 is opposed to the reflective electrodes RE 371 to RE 373 , the color filter CF 2 is opposed to the reflective electrodes RE 374 to RE 376 , and the color filter CF 3 is opposed to the reflective electrodes RE 377 to RE 379 .

Note that the pixel blocks B 35 and B 36 are structured similarly to the pixel block B 34 .

According to such a configuration example, in the pixel block B 34 not including the pixel circuits, since the reflective electrode RE 37 is connected to the reflective electrode RE 362 corresponding to the most significant bit in the adjacent pixel block B 32 , the reflective electrode RE 37 is driven similarly to the reflective electrode RE 362 . That is, the pixel block B 34 can implement one-bit gradation display in accordance with the most significant bit of the pixel block B 32 .

FIG. 20B is a plan view showing another configuration example of the corner portion CN shown in FIG. 2 , and is a figure for explaining the positional relationship between the reflective electrode and the color filter in the pixel blocks B 31 , B 32 , and B 44 . Note that in the example illustrated in FIG. 2 , the pixel block B 44 is connected to the pixel block B 42 . However, in this example, it is assumed that the pixel block B 44 is connected to the pixel block B 31 . In the example illustrated in FIG. 20B , the pixel block B 31 corresponds to the first pixel block, the pixel block B 32 corresponds to the second pixel block, and the pixel block B 44 corresponds to the third pixel block.

The pixel blocks B 31 and B 32 are adjacent to each other in the first direction X, and the pixel blocks B 31 and B 44 are adjacent to each other in the second direction Y. Explanation of the pixel blocks B 31 and B 32 is omitted.

The pixel block B 44 includes the reflective electrodes RE 381 to RE 389 . The reflective electrodes RE 381 to RE 389 function as a substantially single reflective electrode RE 38 as the electrodes adjacent to one another in the first direction X and the second direction Y are mutually connected. The reflective electrode RE 384 is electrically connected to a reflective electrode RE 332 corresponding to the most significant bit in the adjacent pixel block B 31 .

In the pixel block B 44 , the color filter CF 1 is opposed to the reflective electrodes RE 381 to RE 383 , the color filter CF 2 is opposed to the reflective electrodes RE 384 to RE 386 , and the color filter CF 3 is opposed to the reflective electrodes RE 387 to RE 389 .

Note that the pixel blocks B 45 and B 46 are structured similarly to the pixel block B 44 .

Also in this configuration example, the same advantages as those of the configuration example shown in FIG. 20A can be obtained.

FIG. 21 is a plan view showing yet another configuration example of the corner portion CN shown in FIG. 2 , and is a figure for explaining the positional relationship between the reflective electrode and the color filter in the pixel blocks B 41 , B 42 , and B 44 . In the example illustrated in FIG. 21 , the pixel block B 41 corresponds to the first pixel block, the pixel block B 42 corresponds to the second pixel block, and the pixel block B 44 corresponds to the third pixel block.

The pixel blocks B 41 and B 42 are adjacent to each other in the second direction Y, and the pixel blocks B 42 and B 44 are adjacent to each other in the first direction X.

Though not described in detail, the pixel block B 41 is structured similarly to the pixel block B 31 shown in FIG. 20A , and includes the reflective electrodes RE 311 to RE 313 , RE 321 to RE 323 , and RE 331 to RE 333 .

The pixel block B 44 includes the reflective electrodes RE 381 to RE 389 . The reflective electrodes RE 381 to RE 389 function as a substantially single reflective electrode RE 38 as the electrodes adjacent to one another in the first direction X and the second direction Y are mutually connected.

The pixel block B 42 includes reflective electrodes RE 391 to RE 399 . The reflective electrodes RE 391 to RE 399 function as a substantially single reflective electrode RE 39 as the electrodes adjacent to one another in the first direction X and the second direction Y are mutually connected.

The reflective electrode RE 394 is electrically connected to the reflective electrode RE 332 corresponding to the most significant bit in the adjacent pixel block B 41 . The reflective electrode RE 388 is electrically connected to the reflective electrode RE 392 .

In the pixel block B 42 , the color filter CF 1 is opposed to the reflective electrodes RE 391 to RE 393 , the color filter CF 2 is opposed to the reflective electrodes RE 394 to RE 396 , and the color filter CF 3 is opposed to the reflective electrodes RE 397 to RE 399 . In the pixel block B 44 , the color filter CF 1 is opposed to the reflective electrodes RE 381 to RE 383 , the color filter CF 2 is opposed to the reflective electrodes RE 384 to RE 386 , and the color filter CF 3 is opposed to the reflective electrodes RE 387 to RE 389 .

Also in this configuration example, the same advantages as those of the configuration example shown in FIG. 20A can be obtained.

In the present embodiment, application examples of the display devices DSP explained in Embodiments 1 and 2 will be described.

FIG. 22 is an illustration showing a configuration example of a multi-display system. The multi-display system illustrated in the drawing comprises a video signal output device VD, and display devices DSP 1 to DSP 4 . The video signal output device VD is connected to each of the display devices DSP 1 to DSP 4 via a cable. Each of the display devices DSP 1 to DSP 4 is structured to be the same as the display device DSP of the present embodiments described above. The display devices DSP 1 to DSP 4 include display areas DA 1 to DA 4 , and mounting portions MT 1 to MT 4 , respectively.

In the example illustrated, the display devices DSP 1 to DSP 4 are arranged in such a way that their respective mounting portions are not disposed between the adjacent display devices. That is, the display devices DSP 1 and DSP 2 are arranged in the first direction X, the display devices DSP 3 and DSP 4 are arranged in the first direction X, the display devices DSP 1 and DSP 3 are arranged in the second direction Y, and the display devices DSP 2 and DSP 4 are arranged in the second direction Y. However, the display devices DSP 1 and DSP 3 are arranged such that their display areas DA 1 and DA 3 are adjacent to each other, and neither the mounting portion MT 1 nor MT 3 is arranged between the display areas DA 1 and DA 3 . Similarly, the display devices DSP 2 and DSP 4 are arranged such that their display areas DA 2 and DA 4 are adjacent to each other.

According to such a configuration example, the display areas DA 1 to DA 4 of the display devices DSP 1 to DSP 4 are adjacent to each other in close proximity. Further, since a narrower frame structure is achieved in each of the display devices DSP 1 to DSP 4 as described above, an interval between the adjacent display areas in the display areas DA 1 to DA 4 can be reduced. Accordingly, discontinuity of a display image between the display areas in the display areas DA 1 to DA 4 can be made hard to be visually recognized, and the display quality can be improved.

As described above, according to the present embodiment, a display device with a narrower frame structure can be provided.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

An example of the display device which can be obtained from the structure disclosed in the present specification is noted as follows:

(1) A display device comprising:

at least a main pixel comprising a plurality of sub-pixels which exhibit different colors, respectively;

a first pixel block adjacent to the main pixel;

a second pixel block adjacent to the first pixel block, and electrically connected to the first pixel block; and

a driver which drives the main pixel and the first pixel block, in which

the main pixel, the first pixel block, and the second pixel block are located in a display area which displays an image, in which:

the display area includes an outer edge portion,

the first pixel block is closer to the outer edge portion than the main pixel is, and the second pixel block is closer to the outer edge portion than the first pixel block is, and

the second pixel block overlaps the driver in planar view.

(2) The display device of (1), in which:

the first pixel block comprises a pixel circuit, and a first reflective electrode electrically connected to the pixel circuit; and

the second pixel block comprises a second reflective electrode electrically connected to the first reflective electrode.

(3) The display device of (1), in which:

the first pixel block comprises a first pixel circuit, a second pixel circuit, a first reflective electrode electrically connected to the first pixel circuit, and a second reflective electrode electrically connected to the second pixel circuit; and

the second pixel block comprises a third reflective electrode electrically connected to the first reflective electrode, and a fourth reflective electrode electrically connected to the second reflective electrode.

(4) The display device of (3), in which an area of the second reflective electrode is greater than an area of the first reflective electrode.

(5) The display device of (4), in which an area of the fourth reflective electrode is greater than an area of the third reflective electrode.

(6) The display device of (3), further comprising a third pixel block which is adjacent to the second pixel block in the display area, and is electrically connected to the second pixel block, in which:

the third pixel block, the second pixel block, and the first pixel block are arranged along a single direction;

the third pixel block is closer to the outer edge portion than the second pixel block is;

the third pixel block comprises a fifth reflective electrode electrically connected to the fourth reflective electrode; and

an area of the fourth reflective electrode is greater than an area of the third reflective electrode.

(7) The display device of (3), further comprising a third pixel block which is adjacent to the second pixel block in the display area, and is electrically connected to the second pixel block, in which:

the second pixel block is adjacent to the first pixel block along a first direction, and the third pixel block is adjacent to the second pixel block along a second direction intersecting the first direction;

the third pixel block comprises a fifth reflective electrode electrically connected to the fourth reflective electrode; and

an area of the fourth reflective electrode is greater than an area of the third reflective electrode.

(8) The display device of (7), in which the fourth reflective electrode is closer to the fifth reflective electrode than the third reflective electrode is.

(9) The display device of (3), further comprising a third pixel block which is adjacent to the first pixel block in the display area, and is electrically connected to the first pixel block, in which:

the second pixel block is adjacent to the first pixel block along a first direction, and the third pixel block is adjacent to the first pixel block along a second direction intersecting the first direction;

the third pixel block comprises a fifth reflective electrode electrically connected to the second reflective electrode; and

an area of the second reflective electrode is greater than an area of the first reflective electrode.

(10) The display device of (9), in which the second reflective electrode is closer to the fifth reflective electrode than the first reflective electrode is.

(11) The display device of (3), in which each of the first pixel circuit and the second pixel circuit comprises a memory portion capable of holding data corresponding to binary gradation.

(12) The display device of (3), in which:

the first reflective electrode is located at a central portion of the first pixel block;

the second reflective electrode is located outside the first reflective electrode, and comprises an opening adjacent to the second pixel block; and

the first reflective electrode is electrically connected to the third reflective electrode through the opening.

(13) The display device of (3), in which:

the first reflective electrode is located at a central portion of the first pixel block;

the second reflective electrode is located outside the first reflective electrode, and comprises a first opening adjacent to the second pixel block;

the third reflective electrode is located at a central portion of the second pixel block;

the fourth reflective electrode is located outside the third reflective electrode, and comprises a second opening adjacent to the first opening; and

the display device further comprises a connection portion which is located in the first opening and the second opening, and electrically connects the first reflective electrode and the third reflective electrode to each other.

(14) The display device of (1), further comprising:

a first substrate comprising the driver;

a second substrate opposed to the first substrate; and

a seal which bonds the first substrate and the second substrate to each other, in which:

the driver is located at an inner side surrounded by the seal; and

the second pixel block is located closer to the seal than the first pixel block is.

(15) The display device of (14), in which the second substrate comprises a light-shielding layer at a position which overlaps the seal, and does not overlap the second pixel block.

(16) The display device of (14), further comprising at least a dummy electrode which is electrically connected to a power line of a constant potential between the outer edge portion and the seal.