Semiconductor device

The present application is a continuation of U.S. application Ser. No. 14/837,153, filed Aug. 27, 2015, which is a continuation of PCT/JP2014/054406 filed Feb. 25, 2014, which claims priority to JP Application No. 2013-079960, filed Apr. 5, 2013, and JP Application No. 2013-039379, filed Feb. 28, 2013, the entire contents of each of which are incorporated herein by reference.

The present invention relates to a semiconductor device including a rewiring layer on a semiconductor substrate with a functional element formed.

An ESD (Electro-Static-Discharge) protection device as a type of semiconductor devices. The ESD protection device protects semiconductor ICs, etc. from static electricity, etc. Various electronic devices including mobile communication terminals, digital cameras, and laptop PCs are provided with semiconductor integrated circuits constituting logic circuits, memory circuits, etc. Such semiconductor integrated circuits are low-voltage drive circuits composed of micro wiring patterns formed on semiconductor substrates, and thus generally fragile against electrostatic discharge such as surge. Therefore, ESD protection devices are used for protecting such semiconductor integrated circuits from surge.

When an ESD protection device is provided in a high-frequency circuit, there is the problem of being affected by parasitic capacitance of a diode. More specifically, the insertion of the ESD device into the signal line shifts impedance under the influence of the parasitic capacitance of the diode, and as a result, loss of signal may be caused. In particular, ESD protection devices for use in high-frequency circuits are required to be low in parasitic capacitance, in order not to decrease high-frequency characteristics of signal lines connected or integrated circuits to be protected. Thus, Patent Document 1 discloses an ESD protection device with circuit characteristic degradation suppressed by reducing the influence of the parasitic capacitance of a diode.

Patent Document 1: WO 2012/023394 A.

In Patent Document 1, on a surface of a semiconductor substrate with an ESD protection circuit, an inorganic insulating layer of SiO 2 is provided as a protection film, and the inorganic insulating layer is provided with an in-plane wiring of Cu. For this reason, Patent Document 1 has problems such as failure to prevent the capacitance of the ESD protection device itself from being increased, due to the fact that it is not possible to suppress the parasitic capacitance generated between the in-plane wiring and the semiconductor substrate even when it is possible to reduce the influence of parasitic capacitance of the diode.

In addition, in Patent Document 1, because the inorganic insulating layer is formed by a thin-film formation method such as sputtering, asperity appears at the surface of the inorganic insulating layer under the influence of the circuit pattern of the ESD protection circuit formed in the semiconductor substrate. For this reason, when the inorganic insulating layer with surface asperity is provided with the in-plane wiring, parasitic capacitance varies which is generated between the in-plane wiring and the semiconductor substrate. The generation of the varying parasitic capacitance causes problems such as difficulty in adjusting the shift in impedance for high-frequency circuits.

Therefore, an object of the present invention is to provide a semiconductor device which can reduce the generation of parasitic capacitance, and eliminates variation in parasitic capacitance generated.

A semiconductor device according to the present invention includes: a semiconductor substrate formed with a functional element; a metallic film formed on the surface of the semiconductor substrate and electrically connected to the functional element; and a rewiring layer including a wiring electrode opposed to the surface of the semiconductor substrate, and a contact hole that electrically connects the metallic film and a part of the wiring electrode, and characteristically, the rewiring layer includes a protection film layer formed on the surface of the semiconductor substrate to cover a part of the metallic film except a region in contact with the contact hole, and a resin layer that is lower in dielectric constant than the protection film layer, and formed between the protection film layer and the wiring electrode.

Typically, the protection film layer is sputtered onto the semiconductor substrate of the semiconductor device. In this case, asperity appears at the surface of the protection film layer, and thus, when a wiring electrode is formed on the surface of the protection film layer, the distance varies between the wiring electrode and the semiconductor substrate. Therefore, in the configuration according to the present invention, the distance between the wiring electrode and the semiconductor substrate can be equalized in such a way that the resin layer is formed between the protection film layer and the wiring electrode to achieve smoothing (leveling) of the surface on which the wiring electrode is formed. For this reason, variation can be eliminated in magnitude of parasitic capacitance generated between the wiring electrode and the semiconductor substrate. Furthermore, the parasitic capacitance generated between the wiring electrode and the semiconductor substrate can be suppressed by making the dielectric constant of the resin layer lower than that of the protection film layer.

The protection film layer is preferably formed to be thicker with increasing distance from the contact hole, whereas the resin layer is preferably formed to be thinner with increasing distance from the contact hole.

In this configuration, leveling the surface on which the wiring electrode is formed can equalize the distance between the wiring electrode and the semiconductor substrate. There is a need to form an opening in the protection film layer in order to form the contact hole for electrical connection to the metallic film, and in the formation of the protection film layer by sputtering, the protection film layer around the opening (metallic film) may undergo a decrease in thickness. For this reason, the distance between the wiring electrode and the semiconductor substrate can be equalized in such a way that the resin layer is made thicker around the contact hole, and thinner with increasing distance from the contact hole. As a result, even when parasitic capacitance is generated between the wiring electrode and the semiconductor substrate, the variation in capacitance magnitude can be reduced.

The wiring electrode is preferably shaped such that the area opposed to the semiconductor substrate is smaller with increasing distance from a region in contact with the contact hole.

In this configuration, the parasitic capacitance generated between the wiring electrode and the semiconductor substrate can be reduced by reducing the opposed area.

According to the present invention, the parasitic capacitance generated between the semiconductor substrate and the rewiring layer can be reduced, and variation in parasitic capacitance generated can be reduced.

FIG. 1 is a front cross-sectional view of an ESD protection device according to Embodiment 1.

FIG. 2 is a plan view of respective layers of the ESD protection device.

FIG. 3 is a diagram illustrating an ESD protection circuit formed on a Si substrate.

FIG. 4 is a diagram illustrating a first structure example in the formation of an ESD protection circuit on a Si substrate.

FIG. 5 is a pattern diagram of the Si substrate of the first structure example shown in FIG. 4 .

FIG. 6 is a plan view of respective layers of an ESD protection device including the Si substrate of the first structure example shown in FIG. 4 .

FIG. 7 is a plan view of respective layers of an ESD protection device as another example differently from FIG. 6 .

FIG. 8 is a diagram illustrating a second structure example in the formation of an ESD protection circuit on a Si substrate.

FIG. 9 is a plan view of respective layers of an ESD protection device including the Si substrate of the second structure example shown in FIG. 8 .

FIG. 10A is a diagram illustrating an example of connecting the ESD protection device according to Embodiment 1.

FIG. 10B is a diagram illustrating an example of connecting the ESD protection device according to Embodiment 1.

FIG. 11 is a diagram for explaining a principle for operation of the ESD protection device according to Embodiment 1.

FIG. 12 is a diagram for explaining a principle for operation of the ESD protection device according to Embodiment 1.

FIG. 13 is a diagram illustrating a process for manufacturing an ESD protection device.

FIG. 14 is a front cross-sectional view of an ESD protection device according to Embodiment 2.

FIG. 15 is a plan view of respective layers of the ESD protection device.

FIG. 16 is a plan view illustrating an example of intermediate wiring electrodes in different shapes.

FIG. 17 is a diagram illustrating a modification example of the ESD protection device according to Embodiment 2.

FIG. 18 is a diagram illustrating a modification example of the ESD protection device according to Embodiment 2.

FIG. 19 is a diagram illustrating a modification example of the ESD protection device according to Embodiment 2.

Hereinafter, the semiconductor device according to the present invention will be described with reference to ESD protection devices as examples.

FIG. 1 is a front cross-sectional view of an ESD protection device 1 according to Embodiment 1. FIG. 2 is a plan view of respective layers of the ESD protection device 1 . The ESD protection device 1 is a CSP (Chip Size Package) type device, where a rewiring layer 20 including multiple resin layers, etc. is formed on a Si substrate 10 configured to have an ESD protection circuit 10 A including a diode and a zener diode. While the Si substrate 10 corresponds to a semiconductor substrate according to the present invention, the semiconductor substrate according to the present invention is not limited to any Si substrate, but may be a GaAs substrate or the like.

FIG. 3 is a diagram illustrating the ESD protection circuit 10 A formed in the Si substrate 10 . The Si substrate 10 will be described with reference to FIGS. 1 to 3 .

The Si substrate 10 has, on a surface thereof, element forming regions 11 , 12 , and 13 provided. Specifically, a p-epitaxial layer is formed in a p+ type substrate, n wells and p wells are sequentially formed in the p-epitaxial layer, and the wells and a p-diffusion layer or an n-diffusion layer form diodes and zener diodes in the Si substrate 10 . In the present embodiment, formed are respective diodes D 1 , D 2 , D 3 , D 4 that each have three diodes aligned in the forward direction and connected in parallel, and a zener diodes Dz, as shown in FIG. 3 . The diodes D 1 , D 2 , D 3 , D 4 and the zener diodes Dz correspond to functional elements according to the present invention.

The diodes D 1 , D 2 are aligned in the forward direction and connected in series, whereas the diodes D 3 , D 4 are aligned in the forward direction and connected in series. In addition, the diodes D 1 , D 2 and the diodes D 3 , D 4 are each aligned in the forward direction, and connected in parallel with the zener diode Dz. Furthermore, the zener diode Dz is formed between the forming regions of the diodes D 1 , D 4 , and between the forming regions of the diodes D 2 , D 3 .

The Si substrate 10 has Al pads (hereinafter, referred to as pads) P 1 , P 2 formed. The pad P 1 is formed in a position extended from the connection point between the diodes D 1 , D 2 , whereas the pad P 2 is formed in a position extended from the connection point between the diodes D 3 , D 4 . The pads P 1 , P 2 refers to input/output terminals for the ESD protection circuits 10 A, and correspond to metallic films according to the present invention.

Returning to FIG. 1 , the rewiring layer 20 formed on the surface layer of the Si substrate 10 includes a SiN protection film (protection film layer) 21 formed on the surface of the Si substrate 10 so as to partially cover the pads P 1 , P 2 . The SiN protection film 21 , which is made by sputtering on the surface of the Si substrate 10 , has openings formed by etching. The SiN protection film 21 formed by sputtering has surface asperity appearing in deposition principle. It is to be noted that the SiN protection film 21 has a relatively high relative permittivity of 7 to 8.

Furthermore, the rewiring layer 20 includes a resin layer 22 formed on the Si substrate 10 . This resin layer 22 has openings (contact holes) 22 A, 22 B (see FIG. 2 ) in the positions of the openings formed in the SiN protection film 21 . The pads P 1 , P 2 are exposed from the openings 22 A, 22 B, and electrically connected to electrodes formed in the openings 22 A, 22 B. The resin layer 22 has an epoxy (or polyimide) resin that is lower in dielectric constant than the SiN protection film 21 , and has a relative permittivity of 2 to 6. The surface of the resin layer 22 on which electrodes are to be formed as will be described later can be subjected to smoothing (leveling) by forming the resin layer 22 so as to cover the SiN protection film 21 with surface asperity.

In addition, the SiN protection film 21 is formed by sputtering, thus in the case of forming openings, small in thickness around the openings, and closer to a smooth state with increasing distance from the openings (contact holes) in a planar direction. More specifically, the SiN protection film 21 is small in thickness around the pads P 1 , P 2 (around the contact holes), and thicker with increasing distance from the pads P 1 , P 2 (contact holes) in a planar direction. Further, the resin layer 22 formed so as to cover the SiN protection film 21 is thick around the pads P 1 , P 2 (around the contact holes), and thinner with increasing distance from the pads P 1 , P 2 (contact holes) in a planar direction.

The rewiring layer 20 includes Cu/Ti electrodes 23 A, 23 B and Au/Ni electrodes 24 A, 24 B. The Cu/Ti electrodes 23 A, 23 B and Au/Ni electrodes 24 A, 24 B are deposited by sputtering, and formed on the surface of the resin layer 22 , and in the openings 22 A, 22 B. Among the Cu/Ti electrodes 23 A, 23 B and the Au/Ni electrodes 24 A, 24 B, the parts formed in the openings 22 A, 22 B have electrical connection to the pads P 1 , P 2 . Hereinafter, the Cu/Ti electrode 23 A and the Au/Ni electrode 24 A, as well as the Cu/Ti electrode 23 B and the Au/Ni electrode 24 B are respectively referred to as terminal electrodes 25 A, 25 B. The terminal electrodes 25 A, 25 B are input/output electrodes of the ESD protection device 1 .

The rewiring layer 20 includes a resin layer 26 further formed on the resin layer 22 . The resin layer 26 is, for example, a layer of low-dielectric-constant epoxy resin. Parts of the resin layer 26 , which are opposed to parts of the terminal electrodes 25 A, 25 B treated as input/output terminals of the ESD protection device 1 , have rectangular openings 26 A, 26 B formed.

Thus, in the ESD protection device 1 , parasitic capacitance is generated between the Si substrate 10 (or the ESD protection circuit 10 A) and the terminal electrodes 25 A, 25 B. However, the parasitic capacitance generated can be suppressed, because the low-dielectric-constant resin layer 22 is formed between the Si substrate 10 and the terminal electrodes 25 A, 25 B. Furthermore, variation in distance can be eliminated between the Si substrate 10 and the terminal electrodes 25 A, 25 B, because the SiN protection film 21 with asperity appearing on the surface thereof is subjected to leveling with the resin layer 22 . For this reason, variation in parasitic capacitance generated can be suppressed. As a result, the shift in impedance can be reduced for a high-frequency circuit provided with the ESD protection device 1 , and loss of signal can be reduced for the high-frequency circuit.

It is to be noted that while an example of forming the zener diode Dz and the like in the Si substrate 10 to constitute the ESD protection circuit 10 A has been provided in the present embodiment, for example, a variable-capacitance element and the like may be formed in the Si substrate 10 to constitute a circuit with the use of the element.

An example of the structure of the Si substrate 10 will be described below in the formation of an ESD protection circuit in the Si substrate 10 . The structure shown in FIG. 2 has the diodes D 1 to D 4 formed at the surface of the Si substrate 10 , and the zener diode Dz formed in the thickness direction of the Si substrate 10 .

FIG. 4 is a diagram illustrating a first structure example in the formation of an ESD protection circuit in the Si substrate 10 . FIG. 5 is a pattern diagram of the Si substrate 10 of the first structure example shown in FIG. 4 .

In this first structure example, the Si substrate 10 is a p+ type substrate, and the p+ type substrate has element separation films 110 formed by a STI (Shallow Trench Isolation) method. The diodes D 1 to D 4 and the zener diode Dz are formed in the respective regions formed by the element separation film 110 . Specifically, an n-epitaxial layer is formed and n+ diffusion layers form the diodes D 2 , D 4 in the thickness direction of the Si substrate 10 . In addition, a p well is formed, and an n+ diffusion layer forms the zener diode Dz in the thickness direction of the Si substrate 10 . Furthermore, n wells are formed in the n-epitaxial layers, and p+ diffusion layers and n+ diffusion layers form the diodes D 1 , D 3 at the surface of the Si substrate 10 .

On the surface of the Si substrate 10 , a SiO 2 film 111 is formed, and the pad P 1 is formed to bridge the regions with the diodes D 1 , D 2 formed, whereas the pad P 2 is formed so as to bridge the regions with the diodes D 3 , D 4 formed. Furthermore, an Al electrode 10 B is formed on the diodes D 1 , D 3 , and the surface of the Si substrate 10 , except the regions with the pads P 1 , P 2 formed. The Al electrode 10 B is formed so as to bridge the regions with the diodes D 1 , D 3 and the zener diode Dz.

The thus formed ESD protection circuit is equivalent to that in FIG. 3 . It is to be noted that while the diodes D 1 to D 4 each have three diodes aligned in the forward direction and connected in parallel in FIG. 3 , the diodes D 1 to D 4 each have one diode in FIG. 4 .

FIG. 6 is a plan view of respective layers of an ESD protection device including the Si substrate 10 of the first structure example shown in FIG. 4 . The resin layer 22 included in the rewiring layer 20 formed on the Si substrate 10 has openings (contact holes) 22 A, 22 B formed. The pads P 1 , P 2 are exposed from the openings 22 A, 22 B, and electrically connected to electrodes formed in the openings 22 A, 22 B.

Furthermore, the rewiring layer 20 includes terminal electrodes 25 A, 25 B formed on the surface of the resin layer 22 and the openings 22 A, 22 B. The terminal electrodes 25 A, 25 B include Cu/Ti electrodes and Au/Ni electrodes as described with FIG. 1 . The terminal electrodes 25 A, 25 B are formed so as to cover the zener diode formed in the Si substrate 10 in the thickness direction of the ESD protection device 1 . Thus, noise from the zener diode is prevented from being radiated. Parts of the resin layer 26 of the rewiring layer 20 , which are opposed to parts of the terminal electrodes 25 A, 25 B treated as input/output terminals of the ESD protection device 1 , have rectangular openings 26 A, 26 B formed.

It is to be noted that the terminal electrodes 25 A, 25 B may be shaped as shown in FIG. 7 . FIG. 7 is a plan view of respective layers of an ESD protection device as another example differently from FIG. 6 . In this example, the terminal electrodes 25 A, 25 B cover the Al electrode 10 B almost entirely (the region with the zener diode formed). In this case, noise from the zener diode is further prevented from being radiated, as compared with the case in FIG. 6 .

FIG. 8 is a diagram illustrating a second structure example in the formation of an ESD protection circuit in the Si substrate 10 . In this second structure example, the diodes D 2 , D 4 and the zener diode Dz are formed in the thickness direction of the Si substrate 10 , as in the first structure example. In addition, the diodes D 1 a, D 1 b (diode D 1 ) and the diodes D 3 a, D 3 b (diode D 3 ) are formed at the surface of the Si substrate 10 . Furthermore, the pads P 1 , P 2 and the Al electrode 10 B are formed at the surface of the Si substrate 10 .

The thus formed ESD protection circuit is equivalent to that in FIG. 3 . It is to be noted that while the diodes D 1 to D 4 each have three diodes aligned in the forward direction and connected in parallel in FIG. 3 , in FIG. 8 , the diodes D 1 , D 3 each have two diodes, whereas the diodes D 1 , D 4 each have one diode.

FIG. 9 is a plan view of respective layers of an ESD protection device including the Si substrate 10 of the second structure example shown in FIG. 8 . The resin layer 22 included in the rewiring layer 20 formed on the Si substrate 10 has openings (contact holes) 22 A, 22 B formed. The pads P 1 , P 2 are exposed from the openings 22 A, 22 B, and electrically connected to electrodes formed in the openings 22 A, 22 B.

Furthermore, the rewiring layer 20 includes terminal electrodes 25 A, 25 B formed on the surface of the resin layer 22 and the openings 22 A, 22 B. The terminal electrodes 25 A, 25 B include Cu/Ti electrodes and Au/Ni electrodes as described with FIG. 1 . The terminal electrodes 25 A, 25 B are formed so as to cover the zener diode formed in the Si substrate 10 in the thickness direction of the ESD protection device 1 . Thus, noise from the zener diode is prevented from being radiated. Parts of the resin layer 26 of the rewiring layer 20 , which are opposed to parts of the terminal electrodes 25 A, 25 B treated as input/output terminals of the ESD protection device 1 , have rectangular openings 26 A, 26 B formed.

In the first structure example and second structure example, the diodes and the zener diodes are formed in the thickness direction of the Si substrate 10 , and the ESL component can be thus reduced as compared with the case of the diodes formed at the surface of the Si substrate 10 .

Connection examples and a principle for operation will be described below with the ESD protection device 1 according to the present embodiment.

FIGS. 10A and 10B are diagrams illustrating examples of connecting the ESD protection device 1 according to the present embodiment. The ESD protection device 1 is mounted on an electronic device. Examples of the electronic device include laptop PCs, tablet terminals, cellular phones, digital cameras, and portable music players.

FIG. 10A shows an example of connecting the ESD protection device 1 between a signal line connecting an I/O port 100 and an IC 101 to be protected, and GND.

The I/O port 100 is, for example, a port to which an antenna is connected. The ESD protection device 1 according to the present embodiment is bidirectional, and any of the first input/output terminal and second input/output terminal may serve as an input terminal. For example, when the first input/output terminal is treated as an input terminal, the first input/output terminal is connected to the signal line, whereas the second input/output terminal is connected to the GND.

FIG. 10B shows an example of connecting the ESD protection devices 1 between signal lines connecting a connector 102 and an IC 101 , and a GND line. The signal lines in this example are, for example, high-speed transmission lines (differential transmission lines), and the ESD protection device 1 is connected between each of the multiple signal lines and the GND line.

FIGS. 11 and 12 are diagrams for explaining a principle for operation of the ESD protection device according to the present embodiment.

FIG. 11 is a diagram for explaining a case of electric current flowing from the pad P 1 connected to the first input/output terminal (terminal electrode 25 A), to the pad P 2 connected to the second input/output terminal (terminal electrode 25 B). When a surge voltage in excess of the zener voltage of the zener diode Dz is applied, a surge current coming from the first input terminal flows through a pathway from the pad P 1 to the diode D 1 , the zener diode Dz, and the diode D 4 , and is discharged from the pad P 2 to the ground, as indicated by a dashed line in the figure.

FIG. 12 is a diagram for explaining a case of electric current flowing from the pad 2 connected to the second input/output terminal (terminal electrode 25 B), to the pad P 1 connected to the first input/output terminal (terminal electrode 25 A). In this case, as indicated by a dashed line in the figure, a surge current coming from the second input terminal flows through a pathway from the pad P 2 to the diode D 3 , the zener diode Dz, and the diode D 2 , and is discharged from the pad P 1 to the ground.

It is to be noted that capacitance is generated between the Al electrode 10 B and the terminal electrodes 25 A, 25 B in the ESD protection device which has the first structure example shown in FIG. 6 and the second structure example shown in FIG. 8 . This capacitance bypasses a high-frequency voltage applied to the zener diode, from the Al electrode 10 B through the terminal electrode 25 A (or 25 B) and the pad P 1 (or P 2 ) to the ground. The bypass of the high-frequency voltage can lower the peak voltage of the ESD.

A process for manufacturing the ESD protection device will be described below.

FIG. 13 is a diagram illustrating a process for manufacturing the ESD protection device 1 . It is to be noted that the illustration of asperity appearing at the surface of the SiN protection film 21 during the formation thereof is omitted in FIG. 13 .

The ESD protection device 1 is manufactured in accordance with the following process.

(A) First, on the Si substrate 10 with the ESD protection circuit 10 A formed therein, the pads P 1 , P 2 electrically connected to the ESD protection circuit 10 A are formed by photolithography. Further, the SiN protection film 21 is made by sputtering onto the substrate surface, and openings 21 A, 21 B are formed by etching.

It is to be noted that the reduced areas of the pads P 1 , P 2 can reduce the parasitic capacitance formed between the pads and the opposed substrate (ESD protection circuit 10 A). The shift of the impedance can be suppressed by reducing the parasitic capacitance, and as a result, the loss in the signal line can be reduced.

(B) Next, the Si substrate 10 is subjected to spin coating with an epoxy solder resist to form the resin layer 22 , and the openings 22 A, 22 B are formed. The formation of the resin layer 22 can achieve leveling of the surfaces on which the terminal electrodes 25 A, 25 B are formed.

(C) On the surface of the resin layer 22 , a Cu/Ti electrode 23 is deposited by sputtering to be approximately 1.0 μm/0.1 μm in thickness, and thereafter, the Au/Ni electrodes 24 A, 24 B are deposited by sputtering to be approximately 0.1 μm/5.0 μm in thickness. It is to be noted that the Au/Ni electrodes 24 A, 24 B are only partially formed by masking.

(D) Subsequently, the Cu/Ti electrode 23 is subjected to wet etching to form the Cu/Ti electrodes 23 A, 23 B. Thus, the terminal electrodes 25 A, 25 B are formed.

(E) Thereafter, the surface of the resin layer 22 is subjected to spin coating with an epoxy solder resist to form the resin layer 26 , and the openings 26 A, 26 B are formed.

An ESD protection device according to Embodiment 2 will be described below only in terms of the difference from Embodiment 1.

FIG. 14 is a front cross-sectional view of an ESD protection device 2 according to Embodiment 2. FIG. 15 is a plan view of respective layers of the ESD protection device 2 . It is to be noted that the specific configuration of an ESD protection circuit 10 A formed in a Si substrate 10 is omitted in FIG. 15 .

The ESD protection device 2 has a rewiring layer 30 formed on the Si substrate 10 .

The Si substrate 10 , the ESD protection circuit 10 A formed in the Si substrate 10 , and the pads P 1 , P 2 are equivalent to those in Embodiment 1.

On the Si substrate 10 , a SiN protection film 21 is formed. The rewiring layer 30 includes a resin layer 22 for leveling asperity of the SiN protection film 21 . As in Embodiment 1, the SiN protection film 21 is small in thickness around contact holes (openings 22 A, 22 B), and thicker with increasing distance from the contact holes in a planar direction. Further, the resin layer 22 formed so as to cover the SiN protection film 21 is thick around the contact holes, and thinner with increasing distance from the contact holes in a planar direction.

Intermediate wiring electrodes 27 A, 27 B electrically connected to the pads P 1 , P 2 are formed in the openings formed in the SiN protection film 21 and the resin layer 22 , and on the surface of the resin layer 22 . The intermediate wiring electrodes 27 A, 27 B are Ti/Cu/Ti electrodes. The intermediate wiring electrodes 27 A, 27 B are shaped to be smaller in width with increasing distance from parts overlapped with the pads P 1 , P 2 in a planar direction in planar view in FIG. 14 . In addition, the intermediate wiring electrodes 27 A, 27 B are deposited and formed by sputtering.

The rewiring layer 30 includes a resin layer 28 and terminal electrodes 29 A, 29 B further formed on the resin layer 22 . This resin layer 28 also has, as in the resin layer 22 , openings 28 A, 28 B formed at sites corresponding to ends of the intermediate wiring electrodes 27 A, 27 B, which are smaller in width (hereinafter, referred to as small width parts). The terminal electrodes 29 A, 29 B are deposited by sputtering Cu/Ti electrodes and Au/Ni electrodes, and formed on the surface of the resin layer 28 and in the openings (via holes) 28 A, 28 B of the resin layer 28 . Parts of the terminal electrodes 29 A, 29 B, which are formed in the openings 28 A, 28 B, have electrical connection to the small width parts of the intermediate wiring electrodes 27 A, 27 B. The terminal electrodes 29 A, 29 B are input/output electrodes of the ESD protection device 2 .

Moreover, the rewiring layer 30 includes a resin layer 31 further formed on the resin layer 28 . The resin layer 31 is a layer of low-dielectric-constant epoxy resin. Parts of the resin layer 31 , which are opposed to parts of the terminal electrodes 29 A, 29 B, have rectangular openings 31 A, 31 B, 31 C, and 31 D formed. These resin layers 28 , 31 are formed from and by the same material and production method as the resin layers 22 , 26 .

It is to be noted that the openings 31 A, 31 B, 31 C, and 31 D are preferably formed to be kept away from the positions of the via holes in the resin layer 28 . Parts of the terminal electrodes 29 A, 29 B in the via holes may have depressions (omitted in FIG. 14 ) caused in the manufacturing process. When the depressions are exposed from the openings 31 A, 31 B, 31 C, and 31 D, there is a possibility that soldering in the openings 31 A, 31 B, 31 C, and 31 D will cause air to be accumulated in the depressions, thereby decreasing the connection reliability. For this reason, the decrease in connection reliability can be prevented by forming the openings 31 A, 31 B, 31 C, and 31 D to be kept away from the positions of the via holes.

Thus, in the ESD protection device 2 , as in Embodiment 1, parasitic capacitance can be reduced which is generated between the Si substrate 10 (or ESD protection circuit 10 A) and the intermediate wiring electrodes 27 A, 27 B, and variation in parasitic capacitance generated can be reduced. Moreover, due to the interposition of the low-dielectric-constant resin layer 22 therebetween, even parasitic capacitance can be suppressed which is generated between the Si substrate 10 and the terminal electrodes 29 A, 29 B.

In addition, the intermediate wiring electrodes 27 A, 27 B according to the present embodiment are shaped to be smaller in width with increasing distance from the parts overlapped with the pads P 1 , P 2 in planar view. Therefore, as compared with the case of being constant in width, for example, rectangular, the opposed areas are reduced between the Si substrate 10 and the intermediate wiring electrodes 27 A, 27 B, and the parasitic capacitance is also reduced. For this reason, the low-dielectric-constant resin layer 22 is reduced in thickness with increasing distance from the contact holes (openings 22 A, 22 B) in a planar direction, while reducing the opposed areas between the Si substrate 10 and the intermediate wiring electrodes 27 A, 27 B can suppress an increase in parasitic capacitance.

It is to be noted that the shapes of the intermediate wiring electrodes 27 A, 27 B for reducing the areas opposed to the Si substrate 10 is not limited to the shapes in FIG. 15 . FIG. 16 is a plan view illustrating an example of intermediate wiring electrodes in different shapes. The intermediate wiring electrodes 27 C, 27 D shown in FIG. 16 have circular contact hole parts electrically connected to the pads P 1 , P 2 and circular via hole parts electrically connected to the terminal electrodes 29 A, 29 B, and thin wire electrodes connecting the contact hole parts and the via hole parts. Thus, the opposed areas are reduced between the Si substrate 10 and the intermediate wiring electrodes 27 C, 27 D, and the parasitic capacitance is reduced. It is to be noted that the intermediate wiring electrodes 27 C, 27 D are formed by sputtering as Ti/Cu/Ti electrodes, as with the intermediate wiring electrodes 27 A, 27 B.

The ESD protection device 2 according to Embodiment 2 has the same principle for operation and manufacturing process as in Embodiment 1, and descriptions of the principle and process will be thus omitted.

Various modification examples of the ESD protection device 2 according to Embodiment 2 will be sequentially described below. FIGS. 17, 18, and 19 are diagrams illustrating respective modification examples of the ESD protection device according to Embodiment 2. FIGS. 17, 18 , and 19 schematically show configurations for the ESD protection circuit 10 A formed in the Si substrate 10 .

The specific configurations are identical to the configuration shown in FIG. 2 .

FIG. 17 shows an example in which the positional relationship between the contact holes and the via holes in the case of planar view is different from the case shown in FIG. 14 . Intermediate wiring electrodes 27 E, 27 F have the same shapes as the intermediate wiring electrodes 27 A, 27 B, but widths reduced inward from outer edges of the ESD protection device. More specifically, the contact holes for the intermediate wiring electrodes 27 E, 27 F are formed to be inner with respect to the via holes for the terminal electrodes 29 C, 29 D. Further, parts of the resin layer 31 , which are opposed to parts of the terminal electrodes 29 C, 29 D, have rectangular openings 31 E and 31 F formed.

FIG. 18 shows an example in which the number of resin layers of a rewiring layer 40 formed on the Si substrate 10 is increased from the case shown in FIG. 14 . In this example, the rewiring layer 40 includes intermediate wiring electrodes 27 G, 27 H formed in the openings 28 A, 28 B of the resin layer 28 and on the surface thereof. The intermediate wiring electrodes 27 G, 27 H have the same shapes as the intermediate wiring electrodes 27 A, 27 B and have small width parts electrically connected to the intermediate wiring electrodes 27 A, 27 B.

Furthermore, the rewiring layer 40 includes a resin layer 32 formed on the resin layer 28 . This resin layer 32 has openings 32 A, 32 B formed, and terminal electrodes 29 E, 29 F are formed in the openings 32 A, 32 B and on the surface of the resin layer 32 . The terminal electrodes 29 E, 29 F have electrical connection to the intermediate wiring electrodes 27 G, 27 H. Furthermore, a resin layer 34 with openings 34 A, 34 B formed therein is further formed on the resin layer 32 . The openings 34 A, 34 B are formed in positions opposed to parts of the terminal electrodes 29 E, 29 F.

FIG. 19 shows an example in which intermediate wiring electrodes have different shapes from the intermediate wiring electrodes 27 A, 27 B shown in FIG. 14 . The rewiring layer 50 shown in this example includes intermediate wiring electrodes 35 A, 35 B. The intermediate wiring electrodes 35 A, 35 B are formed in the openings 22 A, 22 B of the resin layer 22 and on the surface of the resin layer 22 . The intermediate wiring electrodes 35 A, 35 B have contact holes in central parts thereof, and electrical connection to the pads P 1 , P 2 . In addition, the intermediate wiring electrodes 35 A, 35 B have, at both ends thereof, small width parts.

The resin layer 28 formed on the resin layer 22 has four openings 28 C, 28 D, 28 E, 28 F formed. A terminal electrode 29 G is formed in the openings 28 C, 28 E and on the surface of the resin layer 28 , whereas a terminal electrode 29 H is formed in the openings 28 D, 28 F and on the surface of the resin layer 28 . Parts of the terminal electrodes 29 G, 29 H, which are formed in the openings 28 C, 28 D, 28 E, 28 F, have electrical connection to the intermediate wiring electrodes 35 A, 35 B.

The ESD protection devices in FIGS. 17 to 19 as described above also have, as in Embodiments 1 and 2, the SiN protection film 21 formed on the Si substrate 10 , and the resin layer 22 lower in dielectric constant than the SiN protection film 21 . For this reason, parasitic capacitance can be reduced which is generated between the Si substrate 10 and the intermediate wiring electrodes. Furthermore, the elimination of variation in the distance between the Si substrate 10 and the intermediate wiring electrodes can also suppress variation in parasitic capacitance generated. As a result, the shift in impedance can be reduced for high-frequency circuits provided with the ESD protection devices, and loss of signal can be reduced for the high-frequency circuits.

It is to be noted that the intermediate wiring electrodes 27 E, 27 F, 27 G, 27 H, 35 A, 35 B are formed by sputtering as Ti/Cu/Ti electrodes in FIGS. 17 to 19 , as with the intermediate wiring electrodes 27 A, 27 B. In addition, the terminal electrodes 29 C, 29 D, 29 E, 29 F, 29 G, 29 H are different in shape from the terminal electrodes 29 A, 29 B, but formed from and by the same material and production method as the terminal electrodes 29 A, 29 B. The respective resin layers 31 , 32 , and 34 are formed by the same production methods as the resin layers 22 , 26 .

Furthermore, while the ESD protection devices including the zener diodes are described in the embodiments described above, the ESD protection devices are not limited to the embodiments, but may include, for example, a PNP-type semiconductor or an NPN-type semiconductor.

1 , 2 ESD protection device (semiconductor device)

10 Si substrate (semiconductor substrate)

10 A ESD protection circuit

11 , 12 , 13 element forming region

20 , 30 , 40 , 50 rewiring layer

21 SiN protection film

22 , 26 , 28 , 31 , 32 , 34 resin layer

22 A, 22 B opening

23 A, 23 B Cu/Ti electrode

24 A, 24 B Au/Ni electrode

25 A, 25 B terminal electrode

26 A, 26 B opening

27 A, 27 B, 27 C, 27 D, 27 E, 27 F, 27 G, 27 H intermediate wiring electrode

28 A, 28 B, 28 C, 28 D, 28 E, 28 F opening

29 A, 29 B, 29 C, 29 D, 29 E, 29 F, 29 G, 29 H terminal electrode

31 A, 31 B, 31 C, 31 D, 31 E, 31 F opening

32 A, 32 B opening

34 A, 34 B opening

35 A, 35 B intermediate wiring electrode

D 1 , D 2 , D 3 , D 4 diode (functional element)

Dz zener diode (functional element)

P 1 port (metallic film)

P 2 port (metallic film)