Display apparatus

This application claims the priority benefit of China application serial no. 201611119967.7, filed on Dec. 8, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The invention relates to an electronic apparatus and more particularly, to a display apparatus.

With advances in display technology, displays have played an important role in everyday life. Currently, for artistic demands, most displays require large display areas, and therefore, a development trend toward narrow-frame technology is formed.

Taking a liquid crystal display (LCD) panel for example, it is mainly composed of an active device array substrate, an opposite substrate, and a liquid crystal layer sandwiched between the active device array substrate and the opposite substrate. The active device array substrate may be divided into a display region and a non-display region, where a plurality of pixel units are arranged in an array on the display region, and each of the pixel units includes a thin-film transistor (TFT) and a pixel electrode connected with the TFT. In addition, a plurality of scan lines and a plurality of data lines are disposed in the display region, and the TFT of each pixel unit is electrically connected with its corresponding scan lines and data lines. In the non-display region, signal lines, source drivers and gate drivers are disposed.

When an image screen is displayed on the LCD panel, pixels of each row in the display panel have to be sequentially turned on through the gate drivers, and when being turned on, the pixels of each row receive data voltages provided by the corresponding source drivers. In this way, liquid crystal molecules in the pixels of each row are adaptively arranged according to the received data voltages. However, along with the increase of a resolution of the LCD panel, the numbers of the signals, the gate drivers and the source drivers in the non-display region have to be correspondingly increased, and as a result, an area of the non-display region (or referred to as a frame) is increased. Moreover, production cost of the LCD panel is increased along with the increase of the numbers pf the gate drivers and the source drivers.

The invention provides a display apparatus capable of effectively reducing a frame area and production cost of a display apparatus.

According to an embodiment of the invention, a display apparatus including a plurality of scan lines, a plurality of data line, k clock signal lines and a plurality of pixel groups, where k is an integer greater than 1. The pixel groups are driven by the k clock signal lines, the data lines and their corresponding scan lines. Each of the pixel groups includes a plurality of pixel units respectively disposed at intersections of the corresponding scan lines and the corresponding data lines. Each of the pixel units includes a first switch, a second switch, a third switch, a fourth switch, a first pixel electrode and a second pixel electrode. The first pixel electrode is coupled to a common data line shared with the second pixel electrode through the first switch and the second switch. The second pixel electrode is coupled to the common data line through the third switch and the fourth switch. A turn-on state of the first switch is controlled by the scan line corresponding to the first switch. A turn-on state of the second switch is controlled by a first clock signal line. A turn-on state of the third switch is controlled by the scan line corresponding to the third switch or a former of the scan lines adjacent to the third switch. When the turn-on state of the third switch is controlled by the corresponding scan line, a turn-on state of the fourth switch is controlled by the second clock signal line, and when the turn-on state of the third switch is controlled by the former of the scan lines adjacent to the third switch, the turn-on state of the fourth switch is controlled by the scan line corresponding to the fourth switch or the first clock signal line.

In an embodiment according to the invention, k is equal to 4. There is a ¼-cycle phase difference between clock signals of adjacent clock signal lines. The scan line corresponding to the first switch is the n th scan line. The first clock signal line is the m th clock signal line. When a remainder of n divided by 4 is not 0, m is equal to the remainder of n divided by 4, and when the remainder of n divided by 4 is 0, m is equal to 4, where m and n are positive integers.

In an embodiment according to the invention, the turn-on state of the third switch is controlled by an (n−1) th scan line, and the turn-on state of the fourth switch is controlled by the n th scan line.

In an embodiment according to the invention, the turn-on state of the third switch is controlled by the (n−1) th scan line, and the turn-on state of the fourth switch is controlled by the m th clock signal line.

In an embodiment according to the invention, the first switch, the second switch, the third switch and the fourth switch are transistor switches.

In an embodiment according to the invention, k is equal to 8. There is a ⅛-cycle phase difference between clock signals of adjacent clock signal lines. The scan line corresponding to the first switch is the n th scan line. The first clock signal line the m th clock signal line, where m is equal to 2 multiplied by v. When a remainder of n divided by 4 is not 0, v is equal to the remainder of n divided by 4, where m and n are positive integers, and when the remainder of n divided by 4 is 0, v is equal to 4. The turn-on state of the third switch is controlled by the n th scan line, and the turn-on state of the fourth switch is controlled by an (m−1) th clock signal line.

In an embodiment according to the invention, k is equal to 8. There is a ⅛-cycle phase difference between clock signals of adjacent clock signal lines. The scan line corresponding to the first switch is the n th scan line. The first clock signal line is the m th clock signal line, where m is equal to 4 multiplied by v. When a remainder of n divided by 2 is not 0, v is equal to the remainder of n divided by 2, where m and n are positive integers, and when the remainder of n divided by 2 is 0, v is equal to 2. The turn-on state of the third switch is controlled by the n th scan line, and the turn-on state of the fourth switch is controlled by an (m−1) th clock signal line.

In an embodiment according to the invention, each of the pixel units further includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a third pixel electrode and a fourth pixel electrode. The third pixel electrode is coupled to the common data line through the fifth switch and the sixth switch. The fourth pixel electrode is coupled to the common data line through the seventh switch and the eighth switch. A turn-on state of the fifth switch is controlled by the n th scan line. A turn-on state of the sixth switch is controlled by the (m−2) th clock signal line. A turn-on state of the seventh switch is controlled by the n th scan line. A turn-on state of the eighth switch is controlled by the (m−3) th scan line.

In an embodiment according to the invention, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch and the eighth switch are transistor switches.

In an embodiment according to the invention, a driving circuit is coupled to the scan lines and drives the pixel groups through the scan lines, the data lines and the k clock signal lines.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, several embodiments accompanied with figures are described in detail below.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram illustrating a display apparatus according to an embodiment of the invention.

FIG. 2 is a schematic diagram illustrating a pixel circuit according to an embodiment of the invention.

FIG. 3 is a schematic waveform diagram illustrating the scan signals, the data signal and the clock signals according to an embodiment of the invention.

FIG. 4 is a schematic diagram illustrating a pixel circuit according to another embodiment of the invention.

FIG. 5 is a schematic waveform diagram illustrating the scan signals, the data signal and the clock signals according to an embodiment of the invention.

FIG. 6 is a schematic diagram illustrating a display apparatus according to another embodiment of the invention.

FIG. 7 is a schematic diagram illustrating a pixel circuit according to another embodiment of the invention.

FIG. 8 is a schematic waveform diagram illustrating the scan signals, the data signal and the clock signals according to another embodiment of the invention.

FIG. 9 is a schematic diagram illustrating a display apparatus according to another embodiment of the invention.

FIG. 10 is a schematic diagram illustrating a pixel circuit according to another embodiment of the invention.

FIG. 11 is a schematic waveform diagram illustrating the scan signals, the data signal and the clock signals according to another embodiment of the invention.

Reference will now be made in detail to the exemplary embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram illustrating a display apparatus according to an embodiment of the invention. Referring to FIG. 1 , a display apparatus is, for example, a liquid crystal display (LCD) apparatus or an electronic paper display apparatus, but the invention is not limited thereto. The display apparatus includes a plurality of scan lines G( 0 ), G( 1 ), G( 2 ) . . . and G(n+2), a plurality of data lines DL 1 to DLM, k clock signal lines CK( 1 ) to CK(k), a plurality of pixel groups PG 1 , PG 2 . . . and PGn+2 and a driving circuit 102 , where n and m are positive integers, and k is an integer greater than 1. In the present embodiment, k is 4, but the invention is not limited thereto. The driving circuit 102 is coupled to the scan lines G( 0 ) to G(n+2), the data lines DL 1 to DLM and the k clock signal lines CK( 1 ) to CK(k) and drives the pixel groups PG 1 to PGn+2 through the scan lines G( 0 ) to G(n+2), the data lines DL 1 to DLM and the k clock signal lines CK( 1 ) to CK(k). The pixel groups are respectively driven by the clock signal lines CK( 1 ) to CK(k), the data lines DL 1 to DLM and the corresponding scan lines. For example, the pixel group PG 1 is driven by the clock signal lines CK( 1 ) to CK(k), the data lines DL 1 to DLM and the scan lines G( 0 ) and G( 1 ), the pixel group PG 2 is driven by the clock signal lines CK( 1 ) to CK(k), the data lines DL 1 to DLM and the scan lines G( 1 ) and G( 2 ). It should be noted that FIG. 1 shows two scan lines G( 1 ) may be coupled to a signal output pin of the driving circuit 102 and driven by a scan signal output by the same signal output pin.

Furthermore, each pixel group may include a plurality of pixel units, and the pixel units may be respectively disposed at intersections of the corresponding scan lines and the corresponding data lines. For example, FIG. 2 is a schematic diagram illustrating a pixel circuit according to an embodiment of the invention. Referring to FIG. 2 , in the embodiment illustrated in FIG. 2 , the display apparatus includes 4 clock signal lines CK( 1 ) to CK( 4 ), i.e., k is 4. There is a ¼-cycle phase difference between clock signals of adjacent clock signal lines. Each pixel unit P 1 in the pixel group includes switches SW 1 to SW 4 and pixel electrodes PE 1 and PE 2 . The switches SW 1 to SW 4 may be implemented by, for example, transistor switches, but the invention is not limited thereto. The pixel electrode PE 1 is coupled to a common data line DLC 1 shared with the pixel electrode PE 2 through the switches SW 1 and SW 2 . The common data line DLC 1 is the data line corresponding to the pixel unit P 1 , and as the pixel unit P 1 varies, the common data line DLC 1 may become one of the data lines DL 1 to DLM. The pixel electrode PE 2 is coupled to the common data line DLC 1 through the switches SW 3 and SW 4 . A turn-on state of the switch SW 1 is controlled by the scan line corresponding to the switch SW 1 (which is the n th scan line G(n), for example, in an assumption that the pixel unit P 1 of the present embodiment belongs to the n th pixel group). A turn-on state of the switch SW 2 is controlled by the clock signal line CK(m). When a remainder of n divided by 4 is not 0, m is equal to the remainder of n divided by 4, and when the remainder of n divided by 4 is 0, m is equal to 4, where m and n are positive integers. A turn-on state of the switch SW 3 is controlled by the former of the scan lines adjacent to the switch SW 3 (which is the (n−1) th scan line G(n−1), for example). A turn-on state of the switch SW 4 is controlled by the scan line corresponding to the switch SW 4 (which is the n th scan line G(n), for example).

The driving circuit 102 may respectively output scan signals SG 0 to SGn+2, data signals SD 1 to SDM and clock signals SC 1 to SCk through the scan lines G( 0 ) to G(n+2), the data lines DL 1 to DLM and the k clock signal lines CK( 1 ) to CK(k) to drive the pixel groups PG 1 to PGn+2. For example, FIG. 3 is a schematic waveform diagram illustrating the scan signals, the data signal and the clock signals according to an embodiment of the invention. Referring to FIG. 3 , for descriptive convenience, only the scan signals SG 0 to SG 8 on the scan lines G( 0 ) to G( 8 ), the data signal SD on the common data line DLC 1 and the clock signals SC 1 to SC 4 on the clock signal lines CK( 1 ) to CK( 4 ) are illustrated for description. As illustrated in FIG. 3 , there is a ¼-cycle phase difference between the clock signals of adjacent clock signal lines. For example, an interval between two rising edges of the clock signal SC may be divided into 8 equal parts, and a phase delay time of the clock signal SC 2 later than the clock signal SC 1 is two equal parts of the aforementioned interval. Thus, there is the ¼-cycle phase difference between the clock signal SC 1 and the clock signal SC 2 . When the scan signals SG 0 and SG 1 are at high voltage levels, the pixel electrode PE 2 of the pixel unit P 1 in the pixel group PG 1 may receive the data signal SD from the common data line DLC 1 through the switches SW 3 and SW 4 . When the clock signal SC 1 and the scan signal SG 1 are at high voltage levels, the pixel electrode PE 1 of the pixel unit P 1 in the pixel group PG 1 may receive the data signal SD from the common data line DLC 1 through the switches SW 1 and SW 2 (in this case, n=1, and m=1). When the scan signals SG 1 and SG 2 are at high voltage levels, the pixel electrode PE 2 of the pixel unit P 1 in the pixel group PG 2 may receive the data signal SD from the common data line DLC 1 through the switches SW 3 and SW 4 . When the clock signal SC 2 and the scan signal SG 2 are at high voltage levels, the pixel electrode PE 1 of the pixel unit P 1 in the pixel group PG 2 may receive the data signal SD from the common data line DLC 1 through the switches SW 1 and SW 2 (in this case, n=2, and m=2). With inference by analogy, the switches of the pixel unit P 1 in each of the pixel groups P 3 to PG 8 may be controlled by the corresponding scan signals and clock signals to change their turn-on states, such that the pixel groups PG 3 to PG 8 may sequentially receive the data signal SD to display an image screen corresponding to the data signal SD.

In this way, as the turn-on state of each switch coupled to the common data line is controlled through the scan lines in cooperation with the clock signal lines, only 4 clock signal lines has to be additionally disposed, without additionally disposed scan lines. As such, the number of the data lines may be reduced by a half, and output signals of the driving circuit (which may be implemented by a chip, for example) may be effectively reduced. Thereby, a circuit layout area may be reduced in favor of implementing a narrow-frame display apparatus and reducing production cost of the display apparatus. Taking a display apparatus with a resolution of 240×1440 as an example, if the structure of the present embodiment is applied, the output signal lines of the driving circuit 102 may include only 241 scan lines, 720 data lines and 4 clock signal lines, thereby decreasing 715 output signal lines (calculated by (240+1440)−(241+720+4)=750).

FIG. 4 is a schematic diagram illustrating a pixel circuit according to another embodiment of the invention. Referring to FIG. 4 , the difference between a pixel circuit of the present embodiment and the pixel circuit of the embodiment illustrated in FIG. 2 lies in that the turn-on state of the switch SW 4 is controlled by the clock signal line CK(m) in the present embodiment. In the present embodiment, when the remainder of n divided by 4 is not 0, m is equal to the remainder of n divided by 4, and when the remainder of n divided by 4 is 0, m is equal to 4, where m and n are positive integers. The schematic waveform diagram of the scan signals, the data signal and the clock signals corresponding to the embodiment depicted in FIG. 4 may be as illustrated in FIG. 5 . When the scan signal SG 0 and the clock signal SC 1 are at high voltage levels, the pixel electrode PE 2 of the pixel unit P 1 in the pixel group PG 1 may receive the data signal SD from the common data line DLC 1 through the switches SW 3 and SW 4 . When the clock signal SC 1 and the scan signal SG 1 are at high voltage levels, the pixel electrode PE 1 of the pixel unit P 1 in the pixel group PG 1 may receive the data signal SD from the common data line DLC 1 through the switches SW 1 and SW 2 (in this case, n=1, and m=1). When the scan signal SG 1 and the clock signal SC 2 are at high voltage levels, the pixel electrode PE 2 of the pixel unit P 1 in the pixel group PG 2 may receive the data signal SD from the common data line DLC 1 through the switches SW 3 and SW 4 . When the clock signal SC 2 and the scan signal SG 2 are at high voltage levels, the pixel electrode PE 1 of the pixel unit P 1 in the pixel group PG 2 may receive the data signal SD from the common data line DLC 1 through the switches SW 1 and SW 2 (in this case, n=2, and m=2). With inference by analogy, the switches of the pixel unit P 1 in each of the pixel groups P 3 to PG 8 may be controlled by the corresponding scan signals and clock signals to change their turn-on states, such that the pixel groups PG 3 to PG 8 may sequentially receive the data signal SD to display the image screen corresponding to the data signal SD.

Similarly, the present embodiment may also contribute to effectively reducing the output signal lines of the driving circuit, the circuit layout area and the production cost of the display apparatus. If the structure of the present embodiment is applied, taking the display apparatus with the resolution of 240×1440 as an example, the effect of decreasing 715 output signal lines (calculated by (240+1440)−(241+720+4)=715) may also be achieved.

FIG. 6 is a schematic diagram illustrating a display apparatus according to another embodiment of the invention. Referring to FIG. 6 , the difference between the present embodiment and the embodiment illustrated in FIG. 1 lies in that k is 8 in the present embodiment, and there is a ⅛-cycle phase difference between clock signals of adjacent clock signal lines (but the invention is not limited thereto). Additionally, each pixel group in the embodiment illustrated in FIG. 1 is driven respectively by two corresponding scan lines in cooperation with one clock signal line, while in the present embodiment, each pixel group is driven respectively by one corresponding scan line in cooperation with two clock signal lines. For example, the pixel group PG 1 of the present embodiment is driven by the scan line G( 1 ) and the clock signal lines CK( 1 ) and CK( 2 ). FIG. 7 is a schematic diagram illustrating a pixel circuit according to another embodiment of the invention. Referring to FIG. 7 , furthermore, the pixel circuit corresponding to each pixel unit in the pixel groups in the embodiment illustrated in FIG. 6 may be as illustrated in FIG. 7 . The difference between the pixel circuit of the embodiment illustrated in FIG. 7 and the pixel circuit of the embodiment illustrated in FIG. 2 lies in that the turn-on state of the switch SW 3 is controlled by the scan line corresponding to the switch SW 3 (which is the n th scan line G(n), for example, in an assumption that the pixel unit P 1 of the present embodiment belongs to the n th pixel group), and the turn-on state of the switch SW 4 is controlled by the clock signal line CK(m−1) in the present embodiment. In the present embodiment, m is equal to 2 multiplied by v. When the remainder of n divided by 4 is not 0, v is equal to the remainder of n divided by 4, where m and n are positive integers, and when the remainder of n divided by 4 is 0, v is equal to 4.

A driving circuit 602 may respectively output the scan signals, the data signals and the clock signals to drive the pixel groups PG 1 to PGn+2 through the scan lines G( 1 ) to G(n+2), the data lines DL 1 to DLM and the k clock signal lines CK( 1 ) to CK(k). For example, FIG. 8 is a schematic waveform diagram illustrating the scan signals, the data signal and the clock signals according to another embodiment of the invention. The schematic waveform diagram of the scan signals, the data signals and the clock signals corresponding to the embodiments depicted in FIG. 6 and FIG. 7 may be as illustrated in FIG. 8 . When the scan signal SG 1 and the clock signal SC 1 are at high voltage levels, the pixel electrode PE 2 of the pixel unit P 1 in the pixel group PG 1 may receive the data signal SD from the common data line DLC 1 through the switches SW 3 and SW 4 . When the clock signal SC 2 and the scan signal SG 1 are at high voltage levels, the pixel electrode PE 1 of the pixel unit P 1 in the pixel group PG 1 may receive the data signal SD from the common data line DLC 1 through the switches SW 1 and SW 2 (in this case, n=1, and m=2). When the scan signal SG 2 and the clock signal SC 3 are at high voltage levels, the pixel electrode PE 2 of the pixel unit P 1 in the pixel group PG 2 may receive the data signal SD from the common data line DLC 1 through the switches SW 3 and SW 4 . When the clock signal SC 4 and the scan signal SG 2 are at high voltage levels, the pixel electrode PE 1 of the pixel unit P 1 in the pixel group PG 2 may receive the data signal SD from the common data line DLC 1 through the switches SW 1 and SW 2 (in this case, n=2, and m=4). With inference by analogy, the switches of the pixel unit P 1 in each of the pixel groups P 3 to PG 8 may be controlled by the corresponding scan signals and clock signals to change their turn-on states, such that the pixel groups PG 3 to PG 8 may sequentially receive the data signal SD to display the image screen corresponding to the data signal SD.

Similarly, the present embodiment may also contribute to effectively reducing the output signal lines of the driving circuit, the circuit layout area and the production cost of the display apparatus. If the structure of the present embodiment is applied, taking the display apparatus with the resolution of 240×1440 as an example, the output signal lines of the driving circuit 602 may include only 240 scan lines, 720 data lines and 8 clock signal lines, thereby decreasing 712 output signal lines (calculated by (240+1440)−(240+720+8)=712).

FIG. 9 is a schematic diagram illustrating a display apparatus according to another embodiment of the invention. Referring to FIG. 9 , in the present embodiment, k is 8, and there is a ⅛-cycle phase difference between clock signals of adjacent clock signal lines (but the invention is not limited thereto). The difference between the present embodiment and the embodiment illustrated in FIG. 1 lies in that each pixel group in the embodiment illustrated in FIG. 1 is driven respectively by one corresponding scan line in cooperation with two clock signal lines, while in the present embodiment, each pixel group is driven respectively by one corresponding scan line in cooperation with four clock signal lines. For example, the pixel group PG 1 of the present embodiment is driven by the scan line G( 1 ) and the clock signal lines CK( 1 ) to CK( 4 ). FIG. 10 is a schematic diagram illustrating a pixel circuit according to another embodiment of the invention. Referring to FIG. 10 , furthermore, the pixel circuit corresponding to each pixel unit in the pixel groups in the embodiment illustrated in FIG. 9 may be as illustrated in FIG. 10 . The difference between the pixel circuit of the embodiment illustrated in FIG. 10 and the pixel circuit of the embodiment illustrated in FIG. 7 lies in a pixel unit P 1 ′ of the present embodiment further including switches SW 5 to SW 8 and pixel electrodes PE 3 and PE 4 . The switches SW 5 to SW 8 may also be implemented by, for example, transistor switches, but the invention is not limited thereto. The pixel electrode PE 3 is coupled to the common data line DLC 1 shared with the pixel electrode PE 3 through the switches SW 5 and SW 6 , and the pixel electrode PE 4 is coupled to the common data line DLC 1 through the switches SW 7 and SW 8 . A turn-on state of the switch SW 5 is controlled by the scan line corresponding to the switch SW 5 (which is the n th scan line G(n), for example, in an assumption that the pixel unit P 1 of the present embodiment belongs to the n th pixel group). A turn-on state of the switch SW 6 is controlled by the clock signal line CK(m−2). In the present embodiment, m is equal to 4 multiplied by v. When the remainder of n divided by 2 is not 0, v is equal to the remainder of n divided by 2, where m and n are positive integers, and when the remainder of n divided by 2 is 0, v is equal to 2. A turn-on state of the switch SW 7 is controlled by the scan line corresponding to the switch SW 7 (which is the n th scan line G(n)). A turn-on state of the switch SW 8 is controlled by the clock signal line CK(m−3).

The driving circuit 902 may respectively output the scan signals, the data signals and the clock signals to drive the pixel groups PG 1 to PGn+2 through the scan lines G( 1 ) to G(n+2), the data lines DL 1 to DLM and 8 clock signal lines CK( 1 ) to CK( 8 ). FIG. 11 is a schematic waveform diagram illustrating the scan signals, the data signal and the clock signals according to another embodiment of the invention. The schematic waveform diagram of the scan signals, the data signals and the clock signals corresponding to the embodiments depicted in FIG. 9 and FIG. 10 may be as illustrated in FIG. 11 . When the scan signal SG 1 and the clock signal SC 1 are at high voltage levels, the pixel electrode PE 4 of the pixel unit P 1 ′ in the pixel group PG 1 may receive the data signal SD from the common data line DLC 1 through the switches SW 7 and SW 8 . When the clock signal SC 2 and the scan signal SG 1 are at high voltage levels, the pixel electrode PE 3 of the pixel unit P 1 ′ in the pixel group PG 1 may receive the data signal SD from the common data line DLC 1 through the switches SW 5 and SW 6 . When the scan signal SG 1 and the clock signal SC 3 are at high voltage levels, the pixel electrode PE 2 of the pixel unit P 1 ′ in the pixel group PG 1 may receive the data signal SD from the common data line DLC 1 through the switches SW 3 and SW 4 . When the clock signal SC 4 and the scan signal SG 1 are at high voltage levels, the pixel electrode PE 1 of the pixel unit P 1 ′ in the pixel group PG 1 may receive the data signal SD from the common data line DLC 1 through the switches SW 1 and SW 2 (in this case, n=1, and m=4). With inference by analogy, the switches of the pixel unit P 1 ′ in the pixel group PG 2 may be controlled by the corresponding scan signals and clock signals to change their turn-on states, such that the pixel group PG 2 may sequentially receive the data signal SD to display the image screen corresponding to the data signal SD.

Similarly, the present embodiment may also contribute to effectively reducing the output signal lines of the driving circuit, the circuit layout area and the production cost of the display apparatus. If the structure of the present embodiment is applied, taking the display apparatus with the resolution of 240×1440 as an example, the output signal lines of the driving circuit 602 may include only 240 scan lines, 360 data lines and 8 clock signal lines, so as to achieve the effect of decreasing 1072 output signal lines (calculated by (240+1440)−(240+360+8)=1072).

Based on the above, in the embodiments of the invention, the turn-on states of the switches coupled to the common data line are controlled by the scan lines in cooperation with the clock signal lines, which can contribute to effectively reducing the output signal lines of the driving circuit and the circuit layout area in favor of achieving the narrow-frame display apparatus and the reduction in the production cost of the display apparatus.

Finally, it should be noted that the embodiments above are merely used for describing the technical features of the invention, instead of limiting the invention. Although the invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions.