Electronic device including two-dimensional material

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0099620, filed on Aug. 4, 2016, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

1. Field

The present disclosure relates to electronic devices including a two-dimensional (2D) material layer having a p-type or an ambipolar characteristic.

2. Description of the Related Art

With the development of electronic device industries, research into miniaturization and integration of electronic devices has been conducted. Interest in two-dimensional (2D) materials has increased.

2D materials denote materials having a single-layer or a half-layer structure in which atoms form a desired and/or alternatively predetermined crystal structure. The 2D material has drawn attention as a material that can overcome certain limitations of existing materials. Also, 2D materials may be applied to various devices. However, there are also certain considerations in applying the 2D materials to electronic devices.

Provided are electronic devices including a two-dimensional (2D) material layer having a p-type or an ambipolar characteristic.

Provided are methods of manufacturing electronic devices including a 2D material layer having a p-type or an ambipolar characteristic.

Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

According to some example embodiments, an electronic device may include: a gate electrode; a gate insulating layer on the gate electrode; a 2D material layer on the gate insulating layer above the gate electrode; an insulating layer on the 2D material layer; and an electrode layer contacting an edge of the 2D material layer. The electrode layer has a high work function.

In some example embodiments, the electrode layer may have a work function in a range from 5.0 eV to 6.5 eV.

In some example embodiments, the insulating layer may include an opening that exposes the 2D material layer, the electrode layer may directly contact the edge of the 2D material layer through the opening in the insulating layer, and the electrode layer may be on a surface of the gate insulating layer.

In some example embodiments, the electrode layer may include first and second electrode layers respectively. The opening in the insulating layer may include a first opening and a second opening. The first electrode layer and the second electrode layer may directly contact edges of the 2D material layer on the surface of the gate insulating layer.

In some example embodiments, the 2D material layer may include a transition metal chalcogenide based material.

In some example embodiments, the 2D material layer may include one of MoS 2 , MoSe 2 , MoTe 2 , WS 2 , WSe 2 , WTe 2 , ZrS 2 , ZrSe 2 , HfS 2 , HfSe 2 , NbSe 2 , and ReSe 2 .

In some example embodiments, the insulating layer may include a 2D material layer including one of h-BN and Al 2 O 3 .

According to some example embodiments, an electronic device may include a gate electrode; a gate insulating layer on the gate electrode; a 2D material layer on the gate insulating layer above the gate electrode; an insulating layer on the 2D material layer; and electrode layers contacting edges of the 2D material layer and having work functions different from each other.

In some example embodiments, the electrode layers may include a first electrode layer and a second electrode layer. The first electrode layer may have a work function greater than 3 eV and less than 5 eV. The second electrode layer may have a work function in a range from 5.0 eV to 6.5 eV.

In some example embodiments, the first electrode layer may include a 1-1 electrode layer and a 1-2 electrode layer, the second electrode layer may include a 2-1 electrode layer and a 2-2 electrode layer, the 1-1 electrode layer may be arranged on a first region of the electronic device, the 2-2 electrode layer may be arranged on a second region of the electronic device, and the 1-2 electrode layer and the 2-1 electrode layer may be arranged on a third region of the electronic device between the first and second regions.

In some example embodiments, an n-type contact region may be on a region where the first electrode layer contacts one of the edges of the 2D material layer, and a p-type contact region may be on a region where the second electrode layer contacts one of the edges of the 2D material layer.

These and/or other aspects will become apparent and more readily appreciated from the following description of some example embodiments, taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic cross-sectional view of an electronic device including a two-dimensional (2D) material layer, according to some example embodiments;

FIGS. 2A and 2B are magnified views of a region A 1 of the electronic device including a 2D material layer of FIG. 1 ;

FIGS. 3A through 3E are cross-sectional views illustrating a method of manufacturing an electronic device including a 2D material layer, according to some example embodiments;

FIG. 4 is a schematic cross-sectional view of an ambipolar electronic device including a 2D material layer, according to some example embodiments;

FIG. 5 is a circuit diagram of an electronic device including a 2D material layer according to some example embodiments of FIG. 4 ; and

FIG. 6 is graph illustrating electrical characteristics of an electronic device according to some example embodiments.

Electronic devices including a two-dimensional (2D) material layer according to some example embodiments will now be described in detail with reference to the accompanying drawings. In the drawings, widths and thicknesses of layers and regions may be exaggerated for clarity of the specification and like reference numerals refer to like elements throughout. It will also be understood that when an element is referred to as being “on” or “above” another element, the element may be in direct contact with the other element or other intervening elements may be present.

FIG. 1 is a schematic cross-sectional view of an electronic device 100 including a 2D material layer, according to some example embodiments.

Referring to FIG. 1 , the electronic device 100 to some example embodiments may include a gate electrode 11 on a lower structure 10 , a gate insulating layer 12 on the gate electrode 11 , a 2D material layer 13 on the gate insulating layer 12 , and an insulating layer 14 on the 2D material layer 13 . Also, a surface material layer 15 may be optionally formed on the insulating layer 14 . Also, the electronic device 100 may include a first electrode layer 16 a and a second electrode layer 16 b respectively formed in contact with edges of the 2D material layer 13 on a surface of the gate insulating layer 12 by opening the 2D material layer 13 , the insulating layer 14 , and the surface material layer 15 .

The first electrode layer 16 a and the second electrode layer 16 b respectively may be a source layer and a drain layer. At least one of the first electrode layer 16 a and the second electrode layer 16 b may be formed to directly contact a side surface of the 2D material layer 13 .

FIGS. 2A and 2B are magnified views of a region A 1 of the electronic device including a 2D material layer of FIG. 1 . Here, the region A 1 clearly shows a contact region between the 2D material layer 13 and the second electrode layer 16 b.

Referring to FIG. 2A , a edge of the 2D material layer 13 is formed by directly contacting the second electrode layer 16 b on the gate electrode 11 and the gate insulating layer 12 . The 2D material layer 13 may be formed by including a 2D material. The 2D material may have a single-layer or a half-layer structure in which atoms form a desired and/or alternatively predetermined crystal structure. However, the 2D material is not limited thereto, and may have a plurality of atom layers. The 2D material layer 13 and the second electrode layer 16 b may directly contact each other at an edge region A 11 of the 2D material layer 13 .

Referring to FIG. 2B , the 2D material layer 13 may include the edge region A 11 and a plain region A 12 , and, in the electronic device 100 according to some example embodiments of FIG. 1 , the 2D material layer 13 may directly contact the first electrode layer 16 a and the second electrode layer 16 b at the edge region A 11 of the 2D material layer 13 . The 2D material layer 13 may be, for example, a MoS 2 layer.

The 2D material layer 13 of FIG. 2B is formed by a crystal structure of Mo atoms 13 a and S atoms 13 b . When the second electrode layer 16 b contacts the 2D material layer 13 at the plain region A 12 of the 2D material layer 13 , a conductive material that constitutes the second electrode layer 16 b may contact the S atoms 13 b of the 2D material layer 13 . However, when the second electrode layer 16 b contacts the 2D material layer 13 at the edge region A 11 of the 2D material layer 13 in a MoS 2 crystal structure, a conductive material that constitutes the second electrode layer 16 b may contact both of the Mo atoms 13 a and the S atoms 13 b of the 2D material layer 13 . When the second electrode layer 16 b contacts the 2D material layer 13 at the plain region A 12 of the 2D material layer 13 , it may be referred to as a 2-D contact, and when the second electrode layer 16 b contacts the 2D material layer 13 at the edge region A 11 of the 2D material layer 13 , it may be referred to as a 1-D contact.

If the first and second electrode layers 16 a and 16 b contact the 2D material layer 13 at the plain region A 12 of the 2D material layer 13 , a surface contact region between the first and second electrode layers 16 a and 16 b and the 2D material layer 13 may form a relatively weak bond. Accordingly, energy levels of the S atoms 13 a and a metal that constitutes the first and second electrode layers 16 a and 16 b may overlap with each other, and thus, a strong Fermi level pinning effect that is fixed near a Fermi level conduction band may be induced. In this case, intrinsic MoS 2 always may have an n-type semiconductor characteristic.

However, when the first and second electrode layers 16 a and 16 b contact the 2D material layer 13 at the edge region A 11 of the 2D material layer 13 , the surface contact region between the first and second electrode layers 16 a and 16 b and the 2D material layer 13 may form a relatively strong bond. Accordingly, the Fermi level pinning effect of the 2D material layer 13 may be limited and/or prevented. That is, a Fermi level depinning of a material that constitutes the 2D material layer 13 may be induced by forming the first and second electrode layers 16 a and 16 b to contact the 2D material layer 13 at the edge region A 11 of the 2D material layer 13 . In this case, the 2D material layer 13 may have a p-type or an n-type characteristic depending on the material that constitutes the first electrode layer 16 a and the second electrode layer 16 b . For example, if the first and second electrode layers 16 a and 16 b that contact the 2D material layer 13 include a material having a low work function, an n-type Schottky contact may be obtained at the edge region A 11 of the 2D material layer 13 where the first and second electrode layers 16 a and 16 b contact the 2D material layer 13 .

In some example embodiments, a material having a low work function may denote a conductive material having a work function smaller than 5 eV, and a material having a high work function may denote a conductive material having a work function greater than 5 eV. In detail, a material having a low work function may denote a material having a work function approximately greater than 3 eV and less than 5 eV, such as Al, Fe, Pb, In, Au, and Mo. Also, a material having a high work function may denote a material having a work function approximately greater than 5 eV and not more than 6.5 eV, such as Au, Pt, and Pd. Accordingly, in the electronic device 100 according to some example embodiments, the electronic device 100 may be formed as a p-type electronic device if the first and second electrode layers 16 a and 16 b are formed at the edge region A 11 of the 2D material layer 13 by using a conductive material having a high work function.

FIGS. 3A through 3E are cross-sectional views illustrating a method of manufacturing the electronic device 100 including a 2D material layer, according to some example embodiments.

Referring to FIG. 3A , the gate electrode 11 is formed on the lower structure 10 , and the gate insulating layer 12 is formed on the gate electrode 11 . Also, the 2D material layer 13 is formed on the gate insulating layer 12 , and the insulating layer 14 and the surface material layer 15 are formed on the 2D material layer 13 .

The lower structure 10 may be another material layer or a substrate, for example, a silicon layer on which the electronic device 100 is formed. The gate electrode 11 may be formed by including a conductive metal material and may include a metal, a conductive metal oxide, and a conductive metal nitride. For example, the gate electrode 11 may be formed of a conductive material, such as a metal, an alloy, a conductive oxide, or a conductive nitride. For example the gate electrode 11 may include a metal, such as Au, Ag, Cu, Pt, Al, Ti, W, Ru, or Ta or an alloy of these metals.

The gate insulating layer 12 may include a silicon oxide, a silicon nitride, a hafnium oxide, an aluminum oxide, a tantalum oxide, or a titanium oxide.

The 2D material layer 13 may be formed by including a transition metal chalcogenide based material. The transition metal chalcogenide based material may be a transition metal dichalcogenide (TMDC) material including a transition metal and a chalcogen material. The transition metal may be at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re, and the chalcogen material may be at least one of S, Se, and Te. The TMDC material may be expressed as a chemical formula of MX 2 . Here, X may be a chalcogen element, for example, S, Se, Te, etc. Also, M may be a transitional metal, for example, Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, etc. More specifically, the TMDC material may be MoS 2 , MoSe 2 , MoTe 2 , WS 2 , WSe 2 , WTe 2 , ZrS 2 , ZrSe 2 , HfS 2 , HfSe 2 , NbSe 2 , ReSe 2 , etc.

The 2D material layer 13 may be formed by additionally doping with a dopant material. The 2D material layer 13 according to some example embodiments does not include an additional dopant material, and may be formed by including a 2D material.

The insulating layer 14 formed on the 2D material layer 13 may include, for example, hexagonal-boron nitride (h-BN) or Al 2 O 3 . h-BN is a 2D material that is very flat at an atom level and has a large band gap. When h-BN is formed on the 2D material layer 13 , h-BN facilitates the contact of the first and second electrode layers 16 a and 16 b with the 2D material layer 13 at the edge region A 11 of the 2D material layer 13 when the electronic device 100 according to some example embodiments is manufactured. h-BN may be formed on the 2D material layer 13 by using a Van der Waals transfer technique.

When the electronic device 100 according to some example embodiments is manufactured, the surface material layer 15 may be a material that may be used as a photoresist, and may include poly methyl methacrylate (PMMA). The surface material layer 15 may be selectively removed in the process of manufacturing the electronic devices 100 according to some example embodiments.

Referring to FIG. 3B , the surface material layer 15 on a location where electrodes are formed is removed by patterning the surface material layer 15 . The patterning process of the surface material layer 15 may be a lithography process.

Referring to FIG. 3C , exposed insulating layers 14 a and 14 b between the patterned surface material layers 15 are etched by using the patterned surface material layer 15 as an etch mask. At this point, a dry etching process may be performed by using plasma P generated by a tool T configured to perform an inductively coupled plasma (ICP) process. The 2D material layer 13 and the insulating layer 14 on the gate insulating layer 12 may be etched by a plasma etching process. When the 2D material layer 13 includes MoS 2 , an O 2 /SF 6 plasma process may be used.

Referring to FIG. 3D , regions of the insulating layer 14 and the 2D material layer 13 exposed by the patterned surface material layer 15 may be removed by etching. Accordingly, some surface regions 12 a and 12 b of the gate insulating layer 12 may be exposed.

Referring to FIG. 3E , the first and second electrode layers 16 a and 16 b may be formed on the surface regions 12 a and 12 b of the exposed gate insulating layer 12 between the patterned surface material layers 15 by forming a conductive material so that the first and second electrode layers 16 a and 16 b contact edge regions of the 2D material layer 13 . When the first and second electrode layers 16 a and 16 b are formed of a material having a work function greater than 5.0 eV, the electronic device 100 according to some example embodiments may be formed as a p-type electronic device in which the 2D material layer 13 which is a channel layer and the first and second electrode layers 16 a and 16 b form a p-type contact.

The electronic device 100 according to some example embodiments may be formed as a p-type electronic device, for example, a transistor, by forming the electronic device 100 using a conductive material having a high work function, and also, may be formed as an ambipolar electronic device by forming the electronic device 100 using a conductive material having a low work function.

FIG. 4 is a schematic cross-sectional view of an ambipolar electronic device 200 including a 2D material layer according to some example embodiments. In FIG. 4 , an inverter structure is shown as an ambipolar electronic device. FIG. 5 is a circuit diagram of an electronic device according to some example embodiments of FIG. 4 . FIG. 6 is graph illustrating electrical characteristics of an electronic device according to some example embodiments.

Referring to FIG. 4 , the ambipolar electronic device 200 according to some example embodiments may include a gate electrode 21 on a lower structure 20 , a gate insulating layer 22 on the gate electrode 21 , a 2D material layer 23 on the gate insulating layer 22 , and an insulating layer 24 on the 2D material layer 23 . A surface material layer 25 may be optionally formed on the insulating layer 24 .

Also, the ambipolar electronic device 200 may include a 1-1 electrode layer 26 a and a 1-2 electrode layer 26 b formed of a material having a low work function and a 2-1 electrode layer 27 a and a 2-2 electrode layer 27 b formed of a material having a high work function respectively on regions of the gate insulating layer 22 on which some regions of stacked the 2D material layer 23 , the insulating layer 24 , and the surface material layer 25 are removed. The 1-1 electrode layer 26 a may formed to directly contact edge regions of the 2D material layer 23 , the insulating layer 24 , and the surface material layer 25 by forming on a first region of the gate insulating layer 22 exposed by removing some regions of the 2D material layer 23 , the insulating layer 24 , and the surface material layer 25 . The 2-2 electrode layer 27 b may be formed to directly contact edge regions of the 2D material layer 23 , the insulating layer 24 , and the surface material layer 25 by forming on a second region of the gate insulating layer 22 exposed by removing some regions of the 2D material layer 23 , the insulating layer 24 , and the surface material layer 25 .

The 1-2 electrode layer 26 b and the 2-1 electrode layer 27 a may be formed by contacting each other on a third region between the first and second regions on which 1-1 electrode layer 26 a and the 2-2 electrode layer 27 b respectively are formed. The second and third electrode layers 26 b and 27 a may be formed to directly contact edge regions of the 2D material layer 23 , the insulating layer 24 , and the surface material layer 25 by forming on the third region of the gate insulating layer 22 exposed by removing some regions of the 2D material layer 23 , the insulating layer 24 , and the surface material layer 25 are removed. The 1-2 electrode layer 26 b may be formed adjacent to the 1-1 electrode layer 26 a , and the 2-1 electrode layer 27 a may be formed adjacent to the 2-2 electrode layer 27 b.

The 1-1 electrode layer 26 a and a 1-2 electrode layer 26 b may include a conductive material having a low work function, that is, less than 5 eV, for example, Mo, and the 2-1 electrode layer 27 a and the 2-2 electrode layer 27 b may include a conductive material having a high work function, that is, greater than 5 eV, for example, Pd. Accordingly, a p-type contact may be formed on the edge regions of the 2D material layer 23 that contact the 1-1 electrode layer 26 a and a 1-2 electrode layer 26 b , and an n-type contact may be formed on the edge regions of the 2D material layer 23 that contact the 2-1 electrode layer 27 a and the 2-2 electrode layer 27 b . Accordingly, the ambipolar electronic device 200 according to some example embodiments of FIG. 4 may be formed as an electronic device having an ambipolar characteristic, for example, an inverter. In FIG. 5 , a circuit diagram of the ambipolar electronic device 200 of FIG. 4 , that is, an inverter is shown. In FIG. 5 , an input signal IN is applied through the gate electrode 21 , and an output signal OUT may be obtained through the 1-2 electrode layer 26 b and the 2-1 electrode layer 27 a.

Referring to FIG. 6 , a non-limiting example of the electronic device 200 in FIG. 4 was made using a gate insulating layer 22 formed of Al 2 O 3 , a 2D material layer 23 formed of MoS 2 , a 1-1 electrode layer 26 a and a 1-2 electrode layer 26 b formed of Pd, a 2-1 electrode layer 27 a and a 2-2 electrode layer 27 b formed of Mo. As shown in FIG. 6 , the electronic device 200 had a gain of about ˜14.7 at a source-drain voltage Vsd of 5 V.

An electronic device according to some example embodiments may be used in various types. Examples of the electronic device may be transistors of various structures, for example, a field effect transistor (FET) or a thin film transistor (TFT), and also, may be various electronic devices, such as a diode, a memory device, a logic device, a solar cell, or a display device.

According to some example embodiments of inventive concepts, a Fermi level pinning effect of a 2D material layer may be limited and/or prevented by contacting an edge of the 2D material layer with an electrode layer.

Also, a material for forming the electrode layer that contacts an edge of a 2D material layer may be appropriately selected according to work function, and thus, an electronic device having an ambipolar characteristic may be provided.

While some example embodiments have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the claims. Those of ordinary skill in this art know that the connection structure of the 2D material layer and an electrode layer may be applied to various electronic devices by modifying the connection structure. Therefore, the scope of inventive concepts is limited by the detailed description above.