Electrostatic discharging circuit and display device including the same

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2016-0012370, filed on Feb. 1, 2016 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated by reference herein in its entirety.

The present disclosure relates to a display device, and more specifically, to an electrostatic discharging circuit and a display device including the electrostatic discharging circuit.

When static electricity or an overvoltage/overcurrent is generated at input pads or output pads of a display device, an electrostatic discharging circuit may prevent stress caused by the discharging of the static electricity or the overvoltage/overcurrent to a power terminal.

The display device may reduce a gap between pads (e.g., the input pads or the output pads) by discharging the static electricity using the electrostatic discharging circuit. The electrostatic discharging circuit is implemented as a relatively small transistor. However, because a transistor has either a negative threshold voltage or a positive threshold voltage, as determined by materials included within the transistor, a leakage of a signal (e.g., a leakage current), during the normal operation of the display device, may be caused by the electrostatic discharging circuit, particularly where a negative threshold voltage transistor is used.

An electrostatic, discharging circuit includes a first transistor including a first electrode electrically connected to a signal line, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node. A second transistor includes a third electrode electrically connected to the signal line, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node. A first capacitor receives the first voltage and is electrically connected to the first node.

A display panel includes a pixel, pad receiving a signal from an external source, a signal line transferring the signal to the pixel, and an electrostatic discharging circuit disposed adjacent to the pad. The electrostatic discharging circuit includes a first transistor including a first electrode electrically connected to the signal line, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node, a second transistor including a third electrode electrically connected to the signal line, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node, and a first capacitor receiving the first voltage and electrically connected to the first node

A display device includes a display panel including a pixel, a first pad, and a signal line electrically connecting the pixel and the first pad, a driving integrated circuit configured to receive a driving control signal through a second pad and configured to provide the display panel with a gate signal or a data signal, a timing controller configured to generate the driving control signal, and an electrostatic discharging circuit disposed adjacent to the first pad or the second pad. The electrostatic discharging circuit includes a first transistor including a first electrode electrically connected to the first pad or the second pad, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node. A second transistor includes a third electrode electrically connected to the first pad or the second pad, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node. A first capacitor receives the first voltage and electrically connected to the first node.

A display device includes a display panel including a plurality of pixels, a data driver for providing data signals to the plurality of pixels, and a scan driver for providing scan signals to the plurality of pixels. The display panel, the data driver, or the scan driver includes a pad portion and the pad portion is connected to an electrostatic discharge circuit. The electrostatic discharge circuit includes a first transistor including a first electrode electrically connected to a signal line, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node. A second transistor includes a third electrode electrically connected to the signal line, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node. A first capacitor receives the first voltage and is electrically connected to the first node.

A more complete appreciation of the present disclosure and many of the attendant aspects thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein;

FIG. 1 is a block diagram illustrating a display device according to exemplary embodiments of the present invention;

FIG. 2 is a block diagram illustrating an example of an electrostatic discharging circuit included in the display device of FIG. 1 ;

FIG. 3 is a circuit diagram illustrating a comparative example of the electrostatic discharging circuit of FIG. 2 ;

FIG. 4 is a diagram illustrating an operation characteristic of a transistor included in the electrostatic discharging circuit of FIG. 3 ; and

FIGS. 5 through 7 are diagrams illustrating an example of the electrostatic discharging circuit of FIG. 2 .

Hereinafter, the present inventive concept will be explained in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a display device according to exemplary embodiments of the present invention.

Referring to FIG. 1 , the display device 100 may include a display panel 110 , a scan driver 120 , a data driver 130 , and a timing controller 140 . The display device 100 may display an image based on image data (e.g., first data DATA 1 ) provided from an external source. For example, the display device 100 may be an organic light emitting display device.

The display panel 110 may include a first pad block 111 , signal lines, and pixels PX. The first pad block 111 may receive signals (e.g., a scan signal and/or a data signal) provided from the external source (e.g., the scan driver 120 and/or the data driver 130 ). The signal lines may include scan lines S 1 through Sn, where n is a positive integer, and data lines D 1 through Dm, where in is a positive integer. Each pixel PX may be disposed in regions where the scan lines S 1 through Sn cross the data lines D 1 through Dm. The pixel PX may store a data signal (e.g., a data signal provided through the data lines D 1 through Dm) in response to a scan signal (e.g., a scan signal provided through the scan lines S 1 through Sn) and may emit lights based on a stored data signal.

In some exemplary embodiments of the present invention, the display panel 110 may include an electrostatic discharging circuit (e.g. a first electrostatic discharging circuit). Here, the electrostatic discharging circuit may be disposed adjacent to the first pad block 111 and may discharge static electricity (e.g. an electrostatic, an overvoltage, an overcurrent) generated at the first pad block 111 (e.g. a pad included in the first pad block 111 ) to a reference voltage. Here, the reference voltage may be a driving voltage of the display device 100 , a ground voltage, or another voltage. The electrostatic discharging circuit may prevent (e.g. eliminate) stress of elements included in the display panel 110 (e.g., the pixel PX), where the stress is caused by the static electricity. A configuration of the electrostatic discharging circuit will be described in detail with reference to FIG. 1 and FIG. 2 .

The scan driver 120 may generate the scan signal based on a scan driving control signal SCS. The scan driving control signal SCS may include a start pulse and clock signals. The scan driver 120 may include shift registers sequentially generating the scan signal based on the start pulse and the clock signals.

In some exemplary embodiments of the present invention, the scan driver 120 may include a second electrostatic discharging circuit. Similar to the electrostatic discharging circuit (e.g. the first electrostatic discharging circuit), the second electrostatic discharging circuit may be disposed adjacent to a second pad block 121 included in the scan driver 120 and may discharge static electricity (e.g. an electrostatic, an overvoltage, an overcurrent) generated at the second pad block 121 (e.g. a pad included in the second pad block 121 ) to a reference voltage.

The data driver 130 may generate the data signal in response to a data driving control signal DCS. The data driver 130 may convert image data of a digital format (e.g., second data DATA 2 ) into a data signal of an analog format. The data driver 130 may generate a digital signal based on predetermined grayscale voltages (e.g. preset gamma voltages), where the grayscale voltages are provided from a gamma circuit to the data driver 130 . The data driver 130 may provide the data signal to pixels included a particular pixel column.

In some exemplary embodiments of the present invention, the data driver 130 may include a third electrostatic discharging circuit. Similar to the second electrostatic discharging circuit, the third electrostatic discharging circuit may be disposed adjacent to a third pad block 131 included in the data driver 130 and may discharge static electricity (e.g. an electrostatic, an overvoltage, an overcurrent) generated at the third pad block 131 (e.g. a pad included in the second pad block 112 ) to a reference voltage.

The scan driver 120 and the data driver 130 may each be included in a driving integrated circuit.

The timing controller 140 may receive the image data (e.g., the first data DATA 1 ) and input control signals (e.g., a horizontal synchronous signal, a vertical synchronous signal, and clock signals) from an external source and may generate a compensated image data (e.g., the second data DATA 2 ) suitable to be displayed by the display panel 110 . The timing controller 140 may control the scan driver 120 and the data driver 130 . The timing controller 140 may generate the scan driving control signal SCS and the data driving control signal DCS based on the input control signals.

The display device 100 may further include a power supply. The power supply may generate a driving voltage to drive the display device 100 and may provide the driving voltage to the display panel 110 (e.g. to each of the pixels PX). Here, the driving voltage may be a power voltage required to drive the pixel PX, for example, the driving voltage may include a first power voltage ELVDD and a second power voltage ELVSS. The first power voltage ELVDD may be greater than the second power voltage ELVSS.

As described above, the display device 100 , according to exemplary embodiments of the present invention, may include an electrostatic discharging circuit adjacent to pad blocks 111 , 121 , and 131 and may discharge static electricity (or an electrostatic, an overvoltage, an overcurrent) generated at the pad blocks 111 , 121 , and 131 (e.g. a pad included in the pad blocks 111 , 121 , and 131 ) using the electrostatic discharging circuit. Therefore, the display device 100 may prevent (e.g. eliminate) stress of an element caused by the static electricity.

FIG. 2 is a block diagram illustrating an example of an electrostatic discharging circuit included in the display device of FIG. 1 .

Referring to FIG. 2 , the electrostatic discharging circuit 220 may be disposed adjacent to a pad 210 and may discharge static electricity (or an electrostatic, an overvoltage, an overcurrent) generated at the pad to a reference voltage. The electrostatic discharging circuit 220 may be included in a semiconductor circuit 200 . For example, the semiconductor circuit 200 may be a display panel 110 , or a driving integrated circuit (e.g., the scan driver 120 and/or the data driver 130 ).

The pad 210 may receive a signal SIGNAL provided from an external source and may transfer the signal SIGNAL through a signal line.

The electrostatic discharging circuit 220 may include a first clamping unit D 1 and a second clamping unit D 2 . The first clamping unit D 1 may be electrically connected between the signal line (e.g. the pad 210 ) and a first voltage VH and may discharge static electricity based on the first voltage VH when the static electricity is generated at the signal line (e.g. the pad 210 ). Here, the first voltage VH may be predetermined based on a normal range of the signal SIGNAL (e.g., a range in which the signal SIGNAL has a valid value). For example, the first voltage VH may be greater than or equal to a maximum value of the normal range.

For example, the first clamping unit D 1 may clamp (e.g. limit) the signal SIGNAL based on the first voltage VH when the signal SIGNAL is greater than the first voltage VH. For example, the first clamping unit D 1 may form an electrical connection between the signal line (e.g. the pad 210 ) and the first voltage VH and may output an overcurrent through the electrical connection to the first voltage VH.

Similarly, the second clamping unit D 2 may be electrically connected between the signal line (e.g. the pad 210 ) and a second voltage VL and may discharge static electricity based on the second voltage VL when the static electricity is generated at the signal line (e.g. the pad 210 ). Here, the second voltage VL may be predetermined based on the normal range of the signal SIGNAL. For example, the second voltage VL may be less than or equal to a minimum value of the normal range.

For example, the second clamping unit D 2 may clamp (e.g. limit) the signal SIGNAL based on the second voltage VL when the signal SIGNAL is less than the second voltage VL. For example, the second clamping unit D 2 may form an electrical connection between the signal line (e.g. the pad 210 ) and the second voltage VL and may reduce current from the second voltage VL through the electrical connection to the signal line.

As described with reference to FIG. 2 , the electrostatic discharging circuit 220 may control (e.g. compensate) the signal SIGNAL based on the first voltage VH and/or the second voltage VL when the signal SIGNAL is out of the normal range of the signal SIGNAL. Therefore, the electrostatic discharging circuit 220 may prevent e.g. eliminate) the static electricity generated at the pad 210 (e.g. static electricity coming through the pad 210 or the signal line).

FIG. 3 is a circuit diagram illustrating a comparative example of the electrostatic discharging circuit of FIG. 2 . FIG. 4 is a diagram illustrating an operation characteristic of a transistor included in the electrostatic discharging circuit of FIG. 3 .

Referring to FIGS. 2 and 3 , the first clamping unit D 1 may be implemented as a first transistor T 1 . The first transistor T 1 may include a first electrode electrically connected to the signal line, a second electrode electrically connected to the first voltage VH, and a gate electrode electrically connected to the signal line. Here, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

The first transistor T 1 may form an electrical connection between the signal line and the first voltage VH based on a gate-source voltage Vgs. For example, when the signal SIGNAL provided through the signal line is greater than the first voltage VH, an overcurrent (e.g., a current exceeding a normal current) may flow through the first transistor to the first voltage VH.

The first transistor T 1 may have a threshold voltage Vth and may operate abnormally as a result of a variation of the threshold voltage Vth of the first transistor T 1 .

Referring to FIG. 4 , the first transistor T 1 may have a positive threshold voltage (e.g., threshold voltage having a positive value) or a negative threshold voltage (e.g., a threshold voltage having a negative value) as a result of a characteristic of materials included in the first transistor T 1 (e.g., a characteristic of an oxide).

A first operation characteristic curve 411 may represent an operation characteristic of the first transistor T 1 having an ideal threshold voltage (e.g., 0 voltage (V)). According to the first operation characteristic curve 411 , a first current Id 1 flowing through the first transistor T 1 may be about 0 milliampere (mA) when the gate-source voltage Vgs of the first transistor T 1 is less than 0 V. For example, the first transistor T 1 might not form the electrical connection when the gate-source voltage Vgs of the first transistor T 1 is less than 0 V. The first current Id 1 flowing through the first transistor T 1 may have a certain value when the gate-source voltage Vgs of the first transistor T 1 is greater than 0 V. For example, the first transistor T 1 may form the electrical connection when the gate-source voltage Vgs of the first transistor T 1 is greater than 0 V.

A second operation characteristic curve 412 may represent an operation characteristic of the first transistor T 1 having a negative threshold voltage (e.g., a threshold voltage less than 0 V). According to the second operation characteristic curve 412 , a first current Id 1 flowing through the first transistor T 1 may have a certain value when the gate-source voltage Vgs applied to the first transistor T 1 is less than 0 V. Similarly, a third operation characteristic curve 413 may represent an operation characteristic of the first transistor T 1 having a positive threshold voltage (e.g., a threshold voltage greater than 0 V). According to the third operation characteristic curve 413 , a first current Id 1 flowing through the first transistor T 1 may be 0 mA When the gate-source voltage Vgs applied to the first transistor T 1 is 0 V (or. greater than 0 V).

In addition, the first transistor T 1 may be degraded over time, and the threshold voltage Vth may be shifted to a positive direction (e.g., to have more positive value) or to a negative direction (e.g., to have more negative value). For example, the first transistor T 1 may have an operation characteristic according to the first operation characteristic curve 411 , but the operation characteristic may be changed to be the same as or similar to an operation characteristic according to the second operation characteristic curve 412 or according to third operation characteristic curve 413 over time. In this case, the first transistor T 1 might not perform an electrostatic discharging function.

Referring again to FIG. 3 , the second clamping unit D 2 may be implemented as a second transistor T 2 . The second transistor T 2 may include a first electrode electrically connected to the second voltage VL, a second electrode electrically connected to the signal line, and a gate electrode electrically connected to the second voltage VL. Here, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

Similar to the first transistor T 1 , the second transistor T 2 may form an electrical connection between the signal line and the second voltage VL based on the gate-source voltage Vgs. For example, a lack of current may be provided from the second voltage VL through the electrical connection to the signal line when the signal SIGNAL provided through the signal line is less than the second voltage VL.

Similar to the first transistor T 1 , the second transistor T 2 may have a threshold voltage Vth, and the threshold voltage may have a positive value or a negative value. In addition, the threshold voltage Vth of the second transistor T 2 may be shifted to the positive direction or to the negative direction over time. Here, the second transistor T 2 might not perform (e.g. may perform abnormally) an electrostatic discharging function.

As described with reference to FIGS. 3 and 4 , an electrostatic discharging circuit implemented as a transistor (e.g., the first transistor T 1 or the second transistor T 2 ) might not perform (e.g. may perform abnormally) an electrostatic discharging function because the threshold voltage Vth of the transistor is variable and shifted over time.

Even though the threshold voltage Vth has a negative value or has shifted to the negative direction, the electrostatic discharging circuit 220 , according to exemplary embodiments of the present invention, may perform the electrostatic discharging function in a stable manner by compensating the threshold voltage Vth of a transistor (e.g., the first transistor T 1 and the second transistor T 2 ) included therein.

FIGS. 5 through 7 are diagrams illustrating an example of the electrostatic discharging circuit of FIG. 2 .

Referring to FIGS. 2 and 5 , the electrostatic discharging circuit 220 (e.g. the first clamping unit D 1 ) may include a first transistor T 1 , a second transistor T 2 , and a first capacitor C 1 .

The first transistor T 1 may include a first electrode electrically connected to the signal line, a second electrode electrically connected to the first voltage VH, and a gate electrode electrically connected to a first node N 1 . Here, the first electrode may be a source electrode, and the second electrode may be a drain electrode. The first transistor T 1 may form an electrical connection between the signal line and the first voltage VH based on a first node voltage at the first node N 1 .

The second transistor T 2 may include a first electrode electrically connected to the signal line, a second electrode electrically connected to the first node N 1 , and a gate electrode electrically connected to the first node N 1 . The second transistor T 2 may form an electrical connection between the signal line and the first node N 1 based on the first node voltage at the first node N 1 .

The first capacitor C 1 may be electrically connected between the first node N 1 and the first voltage VH and may store a current (e.g., an electron) transferred through the second transistor T 2 .

The first node voltage at the first node N 1 may be greater than the signal SIGNAL by a second threshold voltage Vth 2 of the second transistor T 2 (e.g., V_N 1 =SIGNAL+Vth 2 , where V_N 1 is the first node voltage) according to the second threshold voltage Vth 2 of the second transistor T 2 . The first capacitor C 1 may maintain the first node voltage at the first node N 1 .

A first current flowing through the first transistor T 1 may be proportional to a voltage difference between a first gate-source voltage Vgs 1 of the first transistor T 1 and a first threshold voltage Vth 1 of the first transistor T 1 (e.g. proportional to a square of the voltage difference). Here, the first gate-source voltage Vgs 1 of the first transistor T 1 may be a voltage difference between the first node voltage at the first node N 1 and the signal SIGNAL, for example, the first gate-source voltage Vgs 1 may be equal to the second threshold voltage Vth 2 (e.g., Vgs 1 =V_N 1 −SIGNAL=SIGNAL+Vth 2 −SIGNAL=Vth 2 ). Therefore, the first current flowing through the first transistor T 1 may be proportional to a voltage difference between the first threshold voltage Vth of the first transistor T 1 and the second threshold voltage Vth 2 of the second transistor T 2 (e.g. proportional to a square of the voltage difference).

The second threshold voltage Vth 2 of the second transistor T 2 may be equal to or similar to the first threshold voltage Vth 1 of the first transistor T 1 because the second transistor T 2 is disposed adjacent to the first transistor T 1 . Here, the first transistor T 1 may be operated according to the first operation characteristic curve 411 described above with reference to FIG. 4 . For example, even though the first transistor T 1 has the threshold voltage Vth having a negative value, the first transistor T 1 (e.g. the first clamping unit D 1 including the first transistor T 1 ) may be operated according to the first operation characteristic curve 411 because the first gate-source voltage Vgs 1 of the first transistor T 1 is compensated by the second threshold voltage Vth 2 of the second transistor T 2 .

In some exemplary embodiments of the present invention, the second threshold voltage Vth 2 of the second transistor T 2 may be greater than the first threshold voltage Vth 1 of the first transistor T 1 . Here, the first transistor T 1 (e.g. the first clamping unit D 1 including the first transistor T 1 ) may be operated according to the third operation characteristic curve 413 illustrated in FIG. 4 even though the first transistor T 1 and the second transistor T 2 have threshold voltages having a negative value.

For example, a second channel of the second transistor T 2 may be longer than a first channel of the first transistor T 1 . Here, the second threshold voltage Vth 2 of the second transistor T 2 may be greater than the first threshold voltage Vth 1 of the first transistor T 1 . Because a threshold voltage increases as a length of a channel increases.

Referring to FIG. 6 , the second transistor T 2 may include a first sub transistor T 2 - 1 and a second sub transistor T 2 - 2 . Here, the first sub transistor T 2 - 1 may be substantially the same as each of the second sub transistor T 2 - 2 and the first transistor T 1 . For example, a channel (e.g. a length and a width of a channel) of the first sub transistor T 2 - 1 may be substantially the same as (e.g. equal to) a channel (e.g. a length and a width of a channel) of the second sub transistor 12 - 2 . In addition, the channel of the first sub transistor T 2 - 1 may be substantially the same as (e.g. equal to) a channel of the first transistor T 1 .

The first sub transistor T 2 - 1 and the second sub transistor T 2 - 2 may be electrically connected in series between the first node N 1 and the signal line. The first sub transistor T 2 - 1 may include a first electrode electrically connected to a third node N 3 , a second electrode electrically connected to the first node N 1 , and a gate electrode electrically connected to the first node N 1 . The second sub transistor 12 - 2 may include a first electrode electrically connected to the signal line, a second electrode electrically connected to the third node N 3 , and a gate electrode electrically connected to the first node N 1 . The first sub transistor T 2 - 1 and the second sub transistor T 2 - 2 may form an electrical connection based on the first node voltage at the first node N 1 . A total length of a total channel of the first sub transistor T 2 - 1 and the second sub transistor T 2 - 2 may be two times a length of a first channel of the first transistor T 1 .

For example, the second channel of the second transistor T 2 may be narrower than the first channel of the first transistor T 1 . Here, the second threshold voltage Vth 2 of the second transistor T 2 may be greater than the first threshold voltage Vth 1 of the first transistor T 1 . Because a threshold voltage decreases as a width of a channel increases.

Referring to FIG. 7 , the first transistor T 1 may include a first auxiliary transistor T 1 - 1 (e.g. a third sub transistor) and a second auxiliary transistor T 1 - 2 (e.g. a fourth sub transistor). The first auxiliary transistor T 1 - 1 and the second auxiliary transistor T 1 - 2 may be electrically connected in parallel. Each of the first auxiliary transistor T 1 - 1 and the second auxiliary transistor T 1 - 2 may be the same as or substantially the same as the first transistor T 1 illustrated in FIG. 5 . The first auxiliary transistor T 1 - 1 may a first electrode electrically connected to the data line, a second electrode electrically connected to the first voltage VH, and a gate electrode electrically connected to the first node N 1 . Similar to the first auxiliary transistor T 1 - 1 , the second auxiliary transistor T 1 - 2 may a first electrode electrically connected to the data line, a second electrode electrically connected to the first voltage VH, and a gate electrode electrically connected to the first node N 1 . The first auxiliary transistor T 1 - 1 and the second auxiliary transistor T 1 - 2 may form an electrical connection based on the first node voltage at the first node N 1 , and a width of a total channel of the first auxiliary transistor T 1 - 1 and the second auxiliary transistor T 1 - 2 may be two times (e.g. twice) a width of the second channel of the second transistor T 2 .

As described above, the electrostatic discharging circuit 220 may include the second transistor T 2 having the second threshold voltage Vth 2 which is greater than the first threshold voltage Vth 1 of the first transistor T 1 . Therefore, the electrostatic discharging circuit 220 (e.g. the first transistor T 1 , the first clamping unit D 1 ) may perform the electrostatic discharging function according to the third operation characteristic curve 413 illustrated in FIG. 4 , even though the first transistor T 1 has the threshold voltage Vth having a negative value.

Referring again to FIG. 5 , the electrostatic discharging circuit 220 (e.g. the second clamping unit D 2 ) may include a third transistor T 3 , a fourth transistor T 4 , and a second capacitor C 2 .

The third transistor T 3 may include a first electrode electrically connected to the second voltage VL, a second electrode electrically connected to the signal line, and a gate electrode electrically connected to a second node N 2 . Here, the first electrode may be a source electrode, and the second electrode may be a drain electrode. The third transistor T 3 may form an electrical connection between the signal line and the second voltage VL based on a second node voltage at the second node N 2 .

The fourth transistor T 4 may include a first electrode electrically connected to the second voltage VL, a second electrode electrically connected to the second node N 2 , and a gate electrode electrically connected to a second node N 2 . The fourth transistor T 4 may form an electrical connection between the signal line and the second voltage VL based on the second node voltage at the second node N 2 .

The second capacitor C 2 may be electrically connected between the second node N 2 and the second voltage VL and may store a current transferred through the fourth transistor T 4 .

The second node voltage at the second node N 2 may be greater than the second voltage VL by a fourth threshold voltage Vth 4 of the fourth transistor T 4 (e.g., V_N 2 =VL+Vth 4 , where V_N 1 is the first node voltage) according to the fourth threshold voltage Vth 4 of the fourth transistor T 4 . The second capacitor C 2 may maintain the second node voltage at the second node N 2 .

A third current flowing through the third transistor T 3 may be proportional to a voltage difference between a third gate-source voltage Vgs 3 of the third transistor T 3 and a third threshold voltage Vth 3 of the third transistor T 3 (e.g. proportional to a square of the voltage difference). Here, the third gate-source voltage Vgs 3 of the third transistor T 3 may be a voltage difference between the second node voltage at the second node N 2 and the second voltage VL, for example, the third gate-source voltage Vgs 3 may be equal to the second third threshold voltage Vth 4 (e.g., Vgs 3 =V_N 2 −VL=VL+Vth 4 −VL=Vth 4 ).

The fourth threshold voltage Vth 4 of the fourth transistor T 4 may be equal to or similar to the third threshold voltage Vth 3 of the third transistor T 3 because the fourth transistor T 4 is disposed adjacent to the third transistor T 3 . Here, the third transistor T 3 may be operated according to the first operation characteristic curve 411 described with reference to FIG. 4 . For example, even though the third transistor T 3 has a threshold voltage having a negative value, the third transistor T 3 (e.g. the second clamping unit D 2 including the third transistor T 3 ) may be operated according to the first operation characteristic curve 411 because the third gate-source voltage Vgs 3 of the third transistor T 3 is compensated by the fourth threshold voltage Vth 4 of the fourth transistor T 4 .

As described with reference to FIG. 5 , the electrostatic discharging circuit 220 according to exemplary embodiments of the present invention may compensate a threshold voltage of a main transistor (e.g., the first transistor T 1 or the third transistor T 3 ) which forms an electrical connection using an auxiliary transistor (e.g., the second transistor T 2 or the fourth transistor T 4 ). Therefore, the electrostatic discharging circuit 220 may perform the electrostatic discharging function in a stable manner even though the threshold voltage Vth of the main transistor has a negative value or has shifted to the negative direction.

In some exemplary embodiments of the present invention, the fourth threshold voltage Vth 4 of the fourth transistor T 4 may be greater than the third threshold voltage Vth 3 of the third transistor T 3 . Here, the third transistor T 3 (e.g. the second clamping unit D 2 including the third transistor T 3 ) may be operated according to the third operation characteristic curve 413 illustrated in FIG. 4 even though the third transistor T 3 and the fourth transistor T 4 have threshold voltages having a negative value.

For example, a fourth channel of the fourth transistor T 4 may be longer than a third channel of the third transistor T 3 .

Referring to FIG. 6 , the fourth transistor T 4 may include a first sub transistor T 4 - 1 and a second sub transistor T 4 - 2 . The first sub transistor T 4 - 1 and the second sub trannsistor T 4 - 2 may be electrically connected in series between the second node N 2 and the second voltage VL. The first sub transistor T 4 - 1 may include a first electrode electrically connected to a fourth node N 4 , a second electrode electrically connected to the second node N 2 , and a gate electrode electrically connected to the second node N 2 . The second sub transistor T 4 - 2 may include a first electrode electrically connected to the second voltage, a second electrode electrically connected to the fourth node N 4 , and a gate electrode electrically connected to the second node N 2 .

For example, the fourth channel of the fourth transistor T 4 may be narrower than the third channel of the third transistor T 3 .

Referring to FIG. 7 , the third transistor T 3 may include a first auxiliary transistor T 3 - 1 (e.g. a third sub transistor) and a second auxiliary transistor T 3 - 2 (e.g. a fourth sub transistor). The first auxiliary transistor T 3 - 1 and the second auxiliary transistor T 3 - 2 may be electrically connected in parallel between the signal line and the second voltage VL. The first auxiliary transistor T 3 - 1 may include a first electrode electrically connected to the second voltage VL, a second electrode electrically connected to the data line, and a gate electrode electrically connected to the second node N 2 . Similar to the first auxiliary transistor T 3 - 1 , the second auxiliary transistor T 3 - 2 may include a first electrode electrically connected to the second voltage VL, a second electrode electrically connected to the data line, and a gate electrode electrically connected to the second node N 2 .

As described above, the electrostatic discharging circuit 220 may include the fourth transistor T 4 having the fourth threshold voltage Vth 4 which is greater than the third threshold voltage Vth 3 of the third transistor T 3 . Therefore, the electrostatic discharging circuit 220 (e.g. the third transistor T 3 , the second clamping unit D 2 ) may perform the electrostatic discharging function according to the third operation characteristic curve 413 illustrated in FIG. 4 , even though the third transistor T 3 and the fourth transistor T 4 have threshold voltages having a negative value.

The present inventive concept may be applied to any display device (e.g., an organic light emitting display device, a liquid crystal display device, etc). For example, the present inventive concept may be applied to a television, a computer monitor, a laptop, a digital camera, a cellular phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a navigation guidance system, a video phone, etc. The foregoing is illustrative of exemplary embodiments of the present invention, and is not to be construed as limiting thereof. Although a few exemplary embodiments of the present invention have been described, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and aspects of the present disclosure.